diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/quick/se/00.hello/ref | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/quick/se/00.hello/ref')
15 files changed, 3727 insertions, 3497 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index e5561895a..112157b30 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000041 # Nu sim_ticks 41083000 # Number of ticks simulated final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 217103 # Simulator instruction rate (inst/s) -host_op_rate 217013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1389706699 # Simulator tick rate (ticks/s) -host_mem_usage 253264 # Number of bytes of host memory used +host_inst_rate 202272 # Simulator instruction rate (inst/s) +host_op_rate 202193 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1294825774 # Simulator tick rate (ticks/s) +host_mem_usage 252636 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # By system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation -system.physmem.totQLat 6580250 # Total ticks spent queuing -system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6584250 # Total ticks spent queuing +system.physmem.totMemAccLat 16559250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12376.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31126.41 # Average memory access latency per DRAM burst system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s @@ -247,9 +247,9 @@ system.physmem_1.preEnergy 208725 # En system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 4023060 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 14292180 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ) @@ -262,19 +262,19 @@ system.physmem_1.memoryStateTime::PRE_PDN 464250 # T system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2003 # Number of BP lookups -system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups +system.cpu.branchPred.lookups 2002 # Number of BP lookups +system.cpu.branchPred.condPredicted 1237 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 378 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1602 # Number of BTB lookups system.cpu.branchPred.BTBHits 377 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 23.533084 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 322 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 333 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 319 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 114 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -292,10 +292,10 @@ system.cpu.dtb.data_hits 2249 # DT system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2263 # DTB accesses -system.cpu.itb.fetch_hits 2686 # ITB hits +system.cpu.itb.fetch_hits 2685 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2703 # ITB accesses +system.cpu.itb.fetch_accesses 2702 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -315,7 +315,7 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6413 # Number of instructions committed system.cpu.committedOps 6413 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1093 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 12.812412 # CPI: cycles per instruction system.cpu.ipc 0.078049 # IPC: instructions per cycle @@ -358,18 +358,18 @@ system.cpu.op_class_0::FloatMemWrite 7 0.11% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 6413 # Class of committed instruction -system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked -system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 12637 # Number of cycles that the object actually ticked +system.cpu.idleCycles 69529 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.987673 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.987673 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025388 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025388 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id @@ -395,12 +395,12 @@ system.cpu.dcache.overall_misses::cpu.data 221 # system.cpu.dcache.overall_misses::total 221 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10428500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10428500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18974000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18974000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18974000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18974000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -419,12 +419,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 83428 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85855.203620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85855.203620 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,12 +447,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 169 system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14538500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14538500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14538500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14538500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -463,65 +463,65 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83410.958904 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83410.958904 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.158440 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2321 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.376374 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.158440 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085527 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085527 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5736 # Number of data accesses +system.cpu.icache.tags.tag_accesses 5734 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5734 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits -system.cpu.icache.overall_hits::total 2322 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 2321 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2321 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2321 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2321 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2321 # number of overall hits +system.cpu.icache.overall_hits::total 2321 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30321500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30321500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30321500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30321500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30321500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30321500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2685 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2685 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2685 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2685 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2685 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2685 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135568 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.135568 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.135568 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.135568 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.135568 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.135568 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83300.824176 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 83300.824176 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 83300.824176 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 83300.824176 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,33 +534,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 364 system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29957500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29957500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135568 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.135568 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.135568 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82300.824176 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82300.824176 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 279.188916 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.158050 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 104.030866 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.008520 # Average percentage of cache occupancy @@ -589,18 +589,18 @@ system.cpu.l2cache.demand_misses::total 532 # nu system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 532 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5979500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5979500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29400000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 29400000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8304000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 8304000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 29400000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14283500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 43683500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 29400000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14283500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 43683500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) @@ -625,18 +625,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998124 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81910.958904 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81910.958904 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80991.735537 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80991.735537 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82111.842105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82111.842105 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,18 +655,18 @@ system.cpu.l2cache.demand_mshr_misses::total 532 system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5249500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5249500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25770000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25770000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25770000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12593500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 38363500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25770000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12593500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 38363500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses @@ -679,18 +679,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71910.958904 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71910.958904 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70991.735537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70991.735537 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -755,7 +755,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 532 # Request fanout histogram -system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 607000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) system.membus.respLayer1.occupancy 2825000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.9 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 3af1cbc4b..c57cc4c2c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,47 +4,47 @@ sim_seconds 0.000024 # Nu sim_ticks 23776000 # Number of ticks simulated final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4743 # Simulator instruction rate (inst/s) -host_op_rate 4743 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17659718 # Simulator tick rate (ticks/s) -host_mem_usage 236044 # Number of bytes of host memory used -host_seconds 1.35 # Real time elapsed on the host +host_inst_rate 135386 # Simulator instruction rate (inst/s) +host_op_rate 135348 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 503875461 # Simulator tick rate (ticks/s) +host_mem_usage 253920 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory -system.physmem.bytes_read::total 31040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 311 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory -system.physmem.num_reads::total 485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 839838493 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 484 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 837146703 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1305518170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 839838493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 839838493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 839838493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 1302826380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 837146703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 837146703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 837146703 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1305518170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 485 # Number of read requests accepted +system.physmem.bw_total::total 1302826380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 484 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 484 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 30976 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 31040 # Total read bytes from the system interface side +system.physmem.bytesReadSys 30976 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 69 # Per bank write bursts system.physmem.perBankRdBursts::1 32 # Per bank write bursts -system.physmem.perBankRdBursts::2 33 # Per bank write bursts +system.physmem.perBankRdBursts::2 32 # Per bank write bursts system.physmem.perBankRdBursts::3 47 # Per bank write bursts system.physmem.perBankRdBursts::4 42 # Per bank write bursts system.physmem.perBankRdBursts::5 20 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.readPktSize::2 0 # Re system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 485 # Read request sizes (log2) +system.physmem.readPktSize::6 484 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -92,7 +92,7 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 140 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see @@ -188,9 +188,9 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.044944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 230.274346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 313.082327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 347.325843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 230.027877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 312.328054 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation @@ -201,101 +201,101 @@ system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # By system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation -system.physmem.totQLat 8008750 # Total ticks spent queuing -system.physmem.totMemAccLat 17102500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16512.89 # Average queueing delay per DRAM burst +system.physmem.totQLat 8020750 # Total ticks spent queuing +system.physmem.totMemAccLat 17095750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16571.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35262.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 35321.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1302.83 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1302.83 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.20 # Data bus utilization in percentage -system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.18 # Data bus utilization in percentage +system.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 395 # Number of row buffer hits during reads +system.physmem.readRowHits 394 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48208.25 # Average gap between requests -system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem.avgGap 48307.85 # Average gap between requests +system.physmem.pageHitRate 81.40 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1756440 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3004470 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7623750 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 3000480 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 47040 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 7630020 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 131040 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) -system.physmem_0.averagePower 621.784975 # Core power per rank (mW) -system.physmem_0.totalIdleTime 16958250 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 14776935 # Total energy per rank (pJ) +system.physmem_0.averagePower 621.499816 # Core power per rank (mW) +system.physmem_0.totalIdleTime 16971750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5899500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16711500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 340500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5886000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 16729000 # Time in different power states system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 2975400 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 7630590 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68640 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14960400 # Total energy per rank (pJ) -system.physmem_1.averagePower 629.216130 # Core power per rank (mW) -system.physmem_1.totalIdleTime 16769000 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 14960310 # Total energy per rank (pJ) +system.physmem_1.averagePower 629.212344 # Core power per rank (mW) +system.physmem_1.totalIdleTime 16765250 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5875500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 16728000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5879250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 16724250 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2854 # Number of BP lookups -system.cpu.branchPred.condPredicted 1681 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2203 # Number of BTB lookups -system.cpu.branchPred.BTBHits 713 # Number of BTB hits +system.cpu.branchPred.lookups 2851 # Number of BP lookups +system.cpu.branchPred.condPredicted 1679 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 484 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2196 # Number of BTB lookups +system.cpu.branchPred.BTBHits 719 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.364957 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 441 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.741348 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 462 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 437 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 436 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2252 # DTB read hits +system.cpu.dtb.read_hits 2241 # DTB read hits system.cpu.dtb.read_misses 48 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2300 # DTB read accesses -system.cpu.dtb.write_hits 1038 # DTB write hits +system.cpu.dtb.read_accesses 2289 # DTB read accesses +system.cpu.dtb.write_hits 1046 # DTB write hits system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1066 # DTB write accesses -system.cpu.dtb.data_hits 3290 # DTB hits +system.cpu.dtb.write_accesses 1074 # DTB write accesses +system.cpu.dtb.data_hits 3287 # DTB hits system.cpu.dtb.data_misses 76 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3366 # DTB accesses -system.cpu.itb.fetch_hits 2295 # ITB hits +system.cpu.dtb.data_accesses 3363 # DTB accesses +system.cpu.itb.fetch_hits 2298 # ITB hits system.cpu.itb.fetch_misses 27 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2322 # ITB accesses +system.cpu.itb.fetch_accesses 2325 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -313,240 +313,240 @@ system.cpu.pwrStateResidencyTicks::ON 23776000 # Cu system.cpu.numCycles 47553 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8498 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 8497 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16552 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2851 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1186 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5772 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1050 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15458 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.071225 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2298 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.069804 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.455665 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12472 80.68% 80.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12480 80.66% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 299 1.93% 82.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 231 1.49% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 265 1.71% 85.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 295 1.91% 87.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 231 1.49% 89.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 280 1.81% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 147 0.95% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 8.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15458 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8341 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2446 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 15472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059954 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.348075 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8344 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4012 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2454 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 451 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 754 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 14992 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8500 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 451 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8504 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1836 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2476 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename +system.cpu.rename.RunCycles 2480 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14425 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1471 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10929 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17896 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17887 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1479 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10912 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17882 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17873 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6352 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6335 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1292 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. +system.cpu.rename.skidInsts 586 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2823 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1299 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 13035 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10770 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6676 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3655 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15458 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697115 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.442161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.696096 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.440906 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11418 73.86% 73.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 347 2.24% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11426 73.85% 73.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1307 8.45% 82.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 919 5.94% 88.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 676 4.37% 92.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 515 3.33% 95.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 346 2.24% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 202 1.31% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.34% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 28 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15472 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36 25.53% 99.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1 0.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 21 14.79% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 83 58.45% 73.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 26.06% 99.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1 0.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7185 66.68% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2474 22.96% 89.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 10.24% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7179 66.66% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2465 22.89% 89.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1113 10.33% 99.93% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10776 # Type of FU issued -system.cpu.iq.rate 0.226610 # Inst issue rate -system.cpu.iq.fu_busy_cnt 141 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 37147 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10770 # Type of FU issued +system.cpu.iq.rate 0.226484 # Inst issue rate +system.cpu.iq.fu_busy_cnt 142 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013185 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 37150 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19749 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9744 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10899 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1649 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1638 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 427 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 434 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 449 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 451 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1424 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13165 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 13146 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1292 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2823 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1299 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10290 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2300 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 486 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 389 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 499 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10283 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2289 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 487 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 84 # number of nop insts executed -system.cpu.iew.exec_refs 3376 # number of memory reference insts executed -system.cpu.iew.exec_branches 1642 # Number of branches executed -system.cpu.iew.exec_stores 1076 # Number of stores executed -system.cpu.iew.exec_rate 0.216390 # Inst execution rate -system.cpu.iew.wb_sent 9948 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9755 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5155 # num instructions producing a value +system.cpu.iew.exec_refs 3373 # number of memory reference insts executed +system.cpu.iew.exec_branches 1639 # Number of branches executed +system.cpu.iew.exec_stores 1084 # Number of stores executed +system.cpu.iew.exec_rate 0.216243 # Inst execution rate +system.cpu.iew.wb_sent 9942 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9754 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5150 # num instructions producing a value system.cpu.iew.wb_consumers 7025 # num instructions consuming a value -system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit +system.cpu.iew.wb_rate 0.205118 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.733096 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 6693 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14221 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.450179 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.361050 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 410 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14238 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.449642 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.359190 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11794 82.93% 82.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11808 82.93% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1161 8.15% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 469 3.29% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 204 1.43% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 134 0.94% 96.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 86 0.60% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 97 0.68% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 89 0.63% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 190 1.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14221 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14238 # Number of insts commited each cycle system.cpu.commit.committedInsts 6402 # Number of instructions committed system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -596,48 +596,48 @@ system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6402 # Class of committed instruction -system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached system.cpu.rob.rob_reads 26792 # The number of ROB reads -system.cpu.rob.rob_writes 27482 # The number of ROB writes +system.cpu.rob.rob_writes 27441 # The number of ROB writes system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32095 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 32081 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6385 # Number of Instructions Simulated system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12923 # number of integer regfile reads -system.cpu.int_regfile_writes 7437 # number of integer regfile writes +system.cpu.int_regfile_reads 13028 # number of integer regfile reads +system.cpu.int_regfile_writes 7426 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 110.182603 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2402 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 110.199847 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2391 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.884393 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.820809 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 110.182603 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026900 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 110.199847 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026904 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026904 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6051 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6051 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 6029 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6029 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1894 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1894 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1883 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1883 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2402 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2402 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2402 # number of overall hits -system.cpu.dcache.overall_hits::total 2402 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2391 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2391 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2391 # number of overall hits +system.cpu.dcache.overall_hits::total 2391 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses @@ -646,43 +646,43 @@ system.cpu.dcache.demand_misses::cpu.data 537 # n system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses system.cpu.dcache.overall_misses::total 537 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13953000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13953000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31158482 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31158482 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45111482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45111482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45111482 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45111482 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2074 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2074 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13954000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13954000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31258982 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31258982 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45212982 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45212982 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45212982 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45212982 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2063 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2063 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2939 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2939 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2939 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2939 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086789 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086789 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087252 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087252 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182715 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182715 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182715 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182715 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84006.484171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84006.484171 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3098 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.183402 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.183402 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.183402 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.183402 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77522.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77522.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87560.173669 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 87560.173669 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84195.497207 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84195.497207 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84195.497207 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84195.497207 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3108 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.729730 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits @@ -700,137 +700,137 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 173 system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9401500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9401500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7013500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7013500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16415000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16415000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16415000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16415000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048698 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048698 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9402500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9402500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7030000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7030000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16432500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16432500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16432500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16432500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048958 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048958 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.058864 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.058864 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93084.158416 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93084.158416 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97409.722222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97409.722222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059085 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059085 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059085 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059085 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93094.059406 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93094.059406 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97638.888889 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97638.888889 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94985.549133 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 94985.549133 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94985.549133 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 94985.549133 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 160.538154 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1837 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.869010 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 160.011089 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1840 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 312 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.897436 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.538154 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078388 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078388 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 160.011089 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078130 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078130 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4903 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4903 # Number of data accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.152344 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4908 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4908 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1837 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1837 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1837 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1837 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits -system.cpu.icache.overall_hits::total 1837 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1840 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1840 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1840 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1840 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1840 # number of overall hits +system.cpu.icache.overall_hits::total 1840 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses system.cpu.icache.overall_misses::total 458 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35506500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35506500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35506500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35506500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35506500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35506500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2295 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2295 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2295 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199564 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199564 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77525.109170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77525.109170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77525.109170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77525.109170 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35481000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35481000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35481000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35481000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35481000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35481000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2298 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2298 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2298 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2298 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2298 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2298 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199304 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.199304 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.199304 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.199304 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.199304 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.199304 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77469.432314 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77469.432314 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77469.432314 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77469.432314 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77469.432314 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77469.432314 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 145 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 145 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 145 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 145 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 145 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 145 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26274500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26274500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26274500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26274500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26274500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26274500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83944.089457 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83944.089457 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 312 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 312 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 312 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26195000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26195000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26195000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26195000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26195000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26195000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135770 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.135770 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.135770 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83958.333333 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83958.333333 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83958.333333 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83958.333333 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83958.333333 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83958.333333 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 270.308724 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 484 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002066 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.559983 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 110.259003 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004900 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.032476 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 110.276248 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004884 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.008265 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::total 0.008249 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014771 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4364 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4364 # Number of data accesses system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits @@ -840,64 +840,64 @@ system.cpu.l2cache.overall_hits::cpu.inst 1 # n system.cpu.l2cache.overall_hits::total 1 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 312 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 312 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 311 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 311 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 311 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses +system.cpu.l2cache.demand_misses::total 484 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 311 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses -system.cpu.l2cache.overall_misses::total 485 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25791500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25791500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25791500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 41935500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25791500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 41935500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 484 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6919000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6919000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25713500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25713500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9242500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9242500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25713500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 16161500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 41875000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25713500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 16161500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 41875000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 313 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 312 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 312 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996805 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996795 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997938 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82665.064103 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82665.064103 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86464.948454 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86464.948454 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997938 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96097.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96097.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82680.064309 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82680.064309 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91509.900990 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91509.900990 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82680.064309 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93419.075145 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86518.595041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82680.064309 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93419.075145 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86518.595041 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -906,119 +906,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 311 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 311 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 484 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22671500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22671500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22671500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37085500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22671500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37085500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6199000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6199000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22603500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22603500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8232500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8232500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22603500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14431500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 37035000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22603500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14431500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 37035000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996795 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997938 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72665.064103 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72665.064103 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997938 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86097.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86097.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72680.064309 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72680.064309 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81509.900990 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81509.900990 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72680.064309 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83419.075145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76518.595041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72680.064309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83419.075145 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76518.595041 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 413 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 312 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002058 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 485 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002062 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045408 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 484 99.79% 99.79% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 485 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 242500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 468000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 484 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 413 # Transaction distribution +system.membus.trans_dist::ReadResp 412 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 968 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 485 # Request fanout histogram +system.membus.snoop_fanout::samples 484 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 484 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 485 # Request fanout histogram -system.membus.reqLayer0.occupancy 595000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 484 # Request fanout histogram +system.membus.reqLayer0.occupancy 593000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2572250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2566000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 10.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 70a6e8611..effdd0b8b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000112 # Nu sim_ticks 112490 # Number of ticks simulated final_tick 112490 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 109209 # Simulator instruction rate (inst/s) -host_op_rate 109187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1917933 # Simulator tick rate (ticks/s) -host_mem_usage 416076 # Number of bytes of host memory used +host_inst_rate 109524 # Simulator instruction rate (inst/s) +host_op_rate 109501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1923375 # Simulator tick rate (ticks/s) +host_mem_usage 415960 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated @@ -414,13 +414,35 @@ system.ruby.miss_latency_hist_seqr::stdev 35.333412 system.ruby.miss_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1731 system.ruby.Directory.incomplete_times_seqr 1730 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997813 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743091 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999387 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999396 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.984319 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.075242 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999991 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061480 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999947 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.995333 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.986612 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.996053 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.092150 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.743802 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.685128 system.ruby.network.routers0.msg_count.Control::2 1731 @@ -431,6 +453,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 13848 system.ruby.network.routers0.msg_bytes.Data::2 124344 system.ruby.network.routers0.msg_bytes.Response_Data::4 124632 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743268 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.995609 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998755 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.685128 system.ruby.network.routers1.msg_count.Control::2 1731 @@ -441,6 +469,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 13848 system.ruby.network.routers1.msg_bytes.Data::2 124344 system.ruby.network.routers1.msg_bytes.Response_Data::4 124632 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.743695 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.993386 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.998107 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.988888 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.996755 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.743428 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015352 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.991146 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015388 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.997440 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030740 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.743571 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.685128 system.ruby.network.routers2.msg_count.Control::2 1731 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 4822d2cee..680b47747 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32719500 # Number of ticks simulated -final_tick 32719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32617500 # Number of ticks simulated +final_tick 32617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128948 # Simulator instruction rate (inst/s) -host_op_rate 150916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 915725978 # Simulator tick rate (ticks/s) -host_mem_usage 269308 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 159604 # Simulator instruction rate (inst/s) +host_op_rate 186772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1129633158 # Simulator tick rate (ticks/s) +host_mem_usage 268376 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory -system.physmem.bytes_read::total 26944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 596586134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 226898333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 823484466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 596586134 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596586134 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 596586134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 226898333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 823484466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 421 # Number of read requests accepted +system.physmem.num_reads::total 420 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 596489614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 227607879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 824097494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 596489614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 596489614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 596489614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 227607879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 824097494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 420 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,7 +46,7 @@ system.physmem.perBankRdBursts::0 91 # Pe system.physmem.perBankRdBursts::1 52 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 22 # Per bank write bursts +system.physmem.perBankRdBursts::4 21 # Per bank write bursts system.physmem.perBankRdBursts::5 41 # Per bank write bursts system.physmem.perBankRdBursts::6 36 # Per bank write bursts system.physmem.perBankRdBursts::7 12 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 32621500 # Total gap between requests +system.physmem.totGap 32519500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 421 # Read request sizes (log2) +system.physmem.readPktSize::6 420 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,7 +91,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -188,95 +188,95 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 374.857143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 257.842659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 316.227871 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20 28.57% 45.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 373.942857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.068407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.910277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 12.86% 74.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.86% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.29% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 5.71% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation -system.physmem.totQLat 5175000 # Total ticks spent queuing -system.physmem.totMemAccLat 13068750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12292.16 # Average queueing delay per DRAM burst +system.physmem.totQLat 5148000 # Total ticks spent queuing +system.physmem.totMemAccLat 13023000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12257.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31042.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 823.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31007.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 824.10 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 823.48 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 824.10 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.43 # Data bus utilization in percentage -system.physmem.busUtilRead 6.43 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.44 # Data bus utilization in percentage +system.physmem.busUtilRead 6.44 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 347 # Number of row buffer hits during reads +system.physmem.readRowHits 346 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 77485.75 # Average gap between requests -system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined +system.physmem.avgGap 77427.38 # Average gap between requests +system.physmem.pageHitRate 82.38 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2263380 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2256240 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4410090 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 4399260 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 59520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10437840 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 10401930 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 20155260 # Total energy per rank (pJ) -system.physmem_0.averagePower 615.992054 # Core power per rank (mW) -system.physmem_0.totalIdleTime 22842000 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 20101380 # Total energy per rank (pJ) +system.physmem_0.averagePower 616.275926 # Core power per rank (mW) +system.physmem_0.totalIdleTime 22764750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 30000 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8749750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 22896000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8725000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 22818750 # Time in different power states system.physmem_1.actEnergy 178500 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 91080 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1743060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 96480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 12022440 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 876000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 1740780 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 96960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 12060060 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 806400 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 18208680 # Total energy per rank (pJ) -system.physmem_1.averagePower 556.500000 # Core power per rank (mW) -system.physmem_1.totalIdleTime 28380000 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 18174900 # Total energy per rank (pJ) +system.physmem_1.averagePower 557.213152 # Core power per rank (mW) +system.physmem_1.totalIdleTime 28278000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 141000 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 2280750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 2099750 # Time in different power states system.physmem_1.memoryStateTime::ACT 2887500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26370250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1968 # Number of BP lookups -system.cpu.branchPred.condPredicted 1177 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups -system.cpu.branchPred.BTBHits 322 # Number of BTB hits +system.physmem_1.memoryStateTime::ACT_PDN 26449250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 1965 # Number of BP lookups +system.cpu.branchPred.condPredicted 1175 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1668 # Number of BTB lookups +system.cpu.branchPred.BTBHits 324 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.409283 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 19.424460 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 137 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectMisses 129 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 32719500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 65439 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 32617500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 65235 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1187 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.210423 # CPI: cycles per instruction -system.cpu.ipc 0.070371 # IPC: instructions per cycle +system.cpu.cpi 14.166124 # CPI: cycles per instruction +system.cpu.ipc 0.070591 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction @@ -446,25 +446,25 @@ system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10731 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54708 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 10712 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54523 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.904844 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.828759 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.904844 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021217 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021217 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.828759 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021198 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021198 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits @@ -567,59 +567,59 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658 system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 162.619345 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1965 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.102484 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 162.068358 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1966 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.124611 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.619345 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079404 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079404 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 162.068358 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079135 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079135 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4896 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4896 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1965 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1965 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1965 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1965 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1965 # number of overall hits -system.cpu.icache.overall_hits::total 1965 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses -system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26079500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26079500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26079500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26079500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26079500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26079500 # number of overall miss cycles +system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4895 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4895 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1966 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1966 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1966 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1966 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1966 # number of overall hits +system.cpu.icache.overall_hits::total 1966 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses +system.cpu.icache.overall_misses::total 321 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25981000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25981000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25981000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25981000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2287 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2287 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2287 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 2287 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 2287 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2287 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140796 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.140796 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.140796 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.140796 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.140796 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.140796 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80992.236025 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80992.236025 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80992.236025 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80992.236025 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140359 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.140359 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.140359 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.140359 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.140359 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.140359 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.694704 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80937.694704 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80937.694704 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80937.694704 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -628,49 +628,49 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 4 # number of writebacks system.cpu.icache.writebacks::total 4 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25757500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25757500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25757500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25757500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25757500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25757500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140796 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.140796 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.140796 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79992.236025 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79992.236025 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25660000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25660000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140359 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.140359 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.140359 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79937.694704 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79937.694704 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 224.400944 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 223.784324 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 420 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.100000 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 155.496620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 68.904325 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004745 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002103 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.947993 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 68.836332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002101 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006829 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012817 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4180 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4180 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits @@ -685,66 +685,66 @@ system.cpu.l2cache.overall_hits::cpu.data 22 # n system.cpu.l2cache.overall_hits::total 39 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 304 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 304 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses +system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses -system.cpu.l2cache.overall_misses::total 429 # number of overall misses +system.cpu.l2cache.overall_misses::total 428 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3423500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3423500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25079000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25079000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24983000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 24983000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6647000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 6647000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24983000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10070500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25079000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 35053500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24983000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10070500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35149500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35053500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 321 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 321 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 321 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 321 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947040 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947040 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947040 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947040 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82226.229508 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82226.229508 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82180.921053 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82180.921053 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81933.566434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81900.700935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81933.566434 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81900.700935 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -759,120 +759,120 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 8 system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 304 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 304 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22029000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22029000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22029000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30343500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22029000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30343500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72226.229508 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72226.229508 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 648 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 940 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100642 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 481500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 420 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 378 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 377 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 421 # Request fanout histogram +system.membus.snoop_fanout::samples 420 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 489500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 420 # Request fanout histogram +system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2238250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2233000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 5d8a28b22..bd3252a40 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18422500 # Number of ticks simulated -final_tick 18422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18517500 # Number of ticks simulated +final_tick 18517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76941 # Simulator instruction rate (inst/s) -host_op_rate 90095 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 308579581 # Simulator tick rate (ticks/s) -host_mem_usage 270584 # Number of bytes of host memory used +host_inst_rate 74881 # Simulator instruction rate (inst/s) +host_op_rate 87684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 301872470 # Simulator tick rate (ticks/s) +host_mem_usage 270416 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 958827521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 420355543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1379183064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 958827521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 958827521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 958827521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 420355543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1379183064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 397 # Number of read requests accepted +system.physmem.num_reads::total 396 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 950452275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 418199001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1368651276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 950452275 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 950452275 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 950452275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 418199001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1368651276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side +system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,7 +51,7 @@ system.physmem.perBankRdBursts::5 32 # Pe system.physmem.perBankRdBursts::6 35 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 9 # Per bank write bursts +system.physmem.perBankRdBursts::9 8 # Per bank write bursts system.physmem.perBankRdBursts::10 28 # Per bank write bursts system.physmem.perBankRdBursts::11 42 # Per bank write bursts system.physmem.perBankRdBursts::12 10 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18337000 # Total gap between requests +system.physmem.totGap 18432000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 397 # Read request sizes (log2) +system.physmem.readPktSize::6 396 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -188,95 +188,95 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 407.864407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 273.934367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.219630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 16.95% 16.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 28.81% 45.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 13.56% 59.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.86% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 406.779661 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 269.610222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.645206 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.39% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 5.08% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 5.08% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8 13.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 5196750 # Total ticks spent queuing -system.physmem.totMemAccLat 12640500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13090.05 # Average queueing delay per DRAM burst +system.physmem.totQLat 5212000 # Total ticks spent queuing +system.physmem.totMemAccLat 12637000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13161.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31840.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1379.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31911.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1368.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1379.18 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1368.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.77 # Data bus utilization in percentage -system.physmem.busUtilRead 10.77 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.69 # Data bus utilization in percentage +system.physmem.busUtilRead 10.69 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.87 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 330 # Number of row buffer hits during reads +system.physmem.readRowHits 329 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46188.92 # Average gap between requests -system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem.avgGap 46545.45 # Average gap between requests +system.physmem.pageHitRate 83.08 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3077430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5255970 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 3085980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 37920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5290170 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 19200 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12170160 # Total energy per rank (pJ) -system.physmem_0.averagePower 660.613923 # Core power per rank (mW) -system.physmem_0.totalIdleTime 11420000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states +system.physmem_0.totalEnergy 12213390 # Total energy per rank (pJ) +system.physmem_0.averagePower 659.559336 # Core power per rank (mW) +system.physmem_0.totalIdleTime 11496500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 29500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 53500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6303750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 11521750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 49250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6316250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 11602500 # Time in different power states system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 749700 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1466040 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 65760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6124080 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 616800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 1457490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 66240 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6092730 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 686400 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10487985 # Total energy per rank (pJ) -system.physmem_1.averagePower 569.303026 # Core power per rank (mW) -system.physmem_1.totalIdleTime 14986000 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 10511025 # Total energy per rank (pJ) +system.physmem_1.averagePower 567.626569 # Core power per rank (mW) +system.physmem_1.totalIdleTime 15098500 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1605250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2751250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13430000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2844 # Number of BP lookups -system.cpu.branchPred.condPredicted 1749 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2408 # Number of BTB lookups -system.cpu.branchPred.BTBHits 867 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 1787250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2733750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13360500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2820 # Number of BP lookups +system.cpu.branchPred.condPredicted 1728 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 468 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2384 # Number of BTB lookups +system.cpu.branchPred.BTBHits 844 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 36.004983 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 35.402685 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 322 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 266 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 260 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 253 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectMisses 247 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,11 +397,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -431,7 +431,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -461,7 +461,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -491,7 +491,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -521,245 +521,245 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 36846 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 37036 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12314 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2844 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1194 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5108 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7733 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12373 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2820 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 985 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1962 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13535 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.094422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13616 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.093052 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.461769 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10839 80.08% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 264 1.95% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 185 1.37% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 204 1.51% 84.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 283 2.09% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 398 2.94% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 139 1.03% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.28% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1050 7.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10916 80.17% 80.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 271 1.99% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 182 1.34% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 206 1.51% 85.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 259 1.90% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 398 2.92% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 138 1.01% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 192 1.41% 92.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1054 7.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13535 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.334202 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6279 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4644 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2146 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 13616 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.076142 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.334080 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6341 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4657 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2138 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 909 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12150 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12250 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 826 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6573 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 835 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2033 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1361 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename +system.cpu.rename.RunCycles 2036 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1364 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11552 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 178 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 181 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1169 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11641 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52345 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12355 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1170 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11673 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 53030 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12530 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6147 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6179 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 40 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2197 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1543 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 442 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10296 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8096 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4835 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12334 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8207 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4962 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12830 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13535 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.598153 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.329974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13616 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.602747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.340306 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10320 76.25% 76.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1163 8.59% 84.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 763 5.64% 90.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 482 3.56% 94.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 344 2.54% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 273 2.02% 98.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 120 0.89% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 60 0.44% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10392 76.32% 76.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1145 8.41% 84.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 762 5.60% 90.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 485 3.56% 93.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 356 2.61% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.04% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 127 0.93% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 61 0.45% 99.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13535 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13616 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 6.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 66 44.00% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62 41.33% 91.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 91.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 13 8.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.42% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 83 50.00% 55.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 61 36.75% 92.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 92.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 13 7.83% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5023 62.04% 62.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1876 23.17% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1154 14.25% 99.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 33 0.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5024 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1962 23.91% 85.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1178 14.35% 99.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 33 0.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8096 # Type of FU issued -system.cpu.iq.rate 0.219725 # Inst issue rate -system.cpu.iq.fu_busy_cnt 150 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018528 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14935 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7404 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8207 # Type of FU issued +system.cpu.iq.rate 0.221595 # Inst issue rate +system.cpu.iq.fu_busy_cnt 166 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020227 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30145 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15189 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7438 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8200 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1170 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1266 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 605 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 696 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10222 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2197 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1543 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 707 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10349 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 356 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7806 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1768 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 290 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 93 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 267 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7885 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1840 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2921 # number of memory reference insts executed -system.cpu.iew.exec_branches 1491 # Number of branches executed -system.cpu.iew.exec_stores 1153 # Number of stores executed -system.cpu.iew.exec_rate 0.211855 # Inst execution rate -system.cpu.iew.wb_sent 7533 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7436 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3503 # num instructions producing a value -system.cpu.iew.wb_consumers 6835 # num instructions consuming a value -system.cpu.iew.wb_rate 0.201813 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512509 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4843 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 3007 # number of memory reference insts executed +system.cpu.iew.exec_branches 1490 # Number of branches executed +system.cpu.iew.exec_stores 1167 # Number of stores executed +system.cpu.iew.exec_rate 0.212901 # Inst execution rate +system.cpu.iew.wb_sent 7581 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7470 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3518 # num instructions producing a value +system.cpu.iew.wb_consumers 6872 # num instructions consuming a value +system.cpu.iew.wb_rate 0.201696 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511932 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4970 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12682 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.424066 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266213 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12743 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.422036 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.264076 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10636 83.87% 83.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 879 6.93% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 416 3.28% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 218 1.72% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.88% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10698 83.95% 83.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 879 6.90% 90.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 416 3.26% 94.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 216 1.70% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 111 0.87% 96.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 54 0.43% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.43% 98.84% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12682 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12743 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -810,120 +810,120 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22637 # The number of ROB reads -system.cpu.rob.rob_writes 21308 # The number of ROB writes -system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23311 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22825 # The number of ROB reads +system.cpu.rob.rob_writes 21580 # The number of ROB writes +system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23420 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.023955 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.023955 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124627 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124627 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7656 # number of integer regfile reads -system.cpu.int_regfile_writes 4268 # number of integer regfile writes +system.cpu.cpi 8.065331 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.065331 # CPI: Total CPI of All Threads +system.cpu.ipc 0.123987 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.123987 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7779 # number of integer regfile reads +system.cpu.int_regfile_writes 4297 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27780 # number of cc regfile reads -system.cpu.cc_regfile_writes 3273 # number of cc regfile writes -system.cpu.misc_regfile_reads 2974 # number of misc regfile reads +system.cpu.cc_regfile_reads 28140 # number of cc regfile reads +system.cpu.cc_regfile_writes 3276 # number of cc regfile writes +system.cpu.misc_regfile_reads 3029 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 88.014551 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2093 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.889702 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2158 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.238095 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.680272 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 88.014551 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021488 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021488 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.889702 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021457 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021457 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5335 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5335 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5471 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5471 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2072 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2072 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2072 # number of overall hits -system.cpu.dcache.overall_hits::total 2072 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits +system.cpu.dcache.overall_hits::total 2137 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses -system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11345000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11345000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24463500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24463500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses +system.cpu.dcache.overall_misses::total 502 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11381500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11381500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24478000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24478000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35808500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35808500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35808500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35808500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1658 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1658 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 35859500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35859500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35859500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35859500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1726 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2571 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2571 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2571 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2571 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110374 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.110374 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2639 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2639 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2639 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2639 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.107764 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.194088 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.194088 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.194088 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.194088 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61994.535519 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61994.535519 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77416.139241 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77416.139241 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.190224 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.190224 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.190224 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.190224 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61190.860215 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61190.860215 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77462.025316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77462.025316 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71760.521042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71760.521042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71433.266932 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71433.266932 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -932,140 +932,140 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7355500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7355500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7338000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7338000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11023500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11023500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11023500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11023500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063329 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063329 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11006000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11006000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11006000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11006000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060834 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060834 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057176 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057176 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70052.380952 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70052.380952 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055703 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055703 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69885.714286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69885.714286 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 149.507349 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.671994 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1587 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.416382 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.507349 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073002 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073002 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 148.671994 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4218 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4218 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits -system.cpu.icache.overall_hits::total 1577 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses -system.cpu.icache.overall_misses::total 385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28997500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28997500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28997500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28997500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28997500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28997500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1962 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1962 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1962 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1962 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196228 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.196228 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.196228 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.196228 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.196228 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.196228 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75318.181818 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75318.181818 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75318.181818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75318.181818 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 493 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4257 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4257 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1587 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1587 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1587 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1587 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1587 # number of overall hits +system.cpu.icache.overall_hits::total 1587 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 395 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 395 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 395 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 395 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 395 # number of overall misses +system.cpu.icache.overall_misses::total 395 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 29663500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 29663500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 29663500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 29663500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 29663500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 29663500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1982 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199294 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.199294 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.199294 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.199294 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.199294 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.199294 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75097.468354 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75097.468354 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75097.468354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75097.468354 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 422 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 98.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 105.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 2 # number of writebacks system.cpu.icache.writebacks::total 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23482000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23482000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23482000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23482000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23482000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23482000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149847 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149847 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149847 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79870.748299 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79870.748299 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 102 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 102 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 102 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 102 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23439000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23439000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23439000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23439000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23439000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23439000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.147830 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.147830 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.147830 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79996.587031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79996.587031 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 214.408451 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 213.492112 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.098485 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.281348 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 74.127103 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004281 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002262 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.462705 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 74.029407 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004256 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002259 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006515 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3924 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3924 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits @@ -1080,66 +1080,66 @@ system.cpu.l2cache.overall_hits::cpu.data 20 # n system.cpu.l2cache.overall_hits::total 38 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 275 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 275 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses +system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 403 # number of overall misses +system.cpu.l2cache.overall_misses::total 402 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3603000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3603000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22833000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22833000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22833000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10564000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33397000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22833000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10564000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33397000 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22791500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22791500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6943500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6943500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22791500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10546500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33338000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22791500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10546500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33338000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 293 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.913636 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.913636 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82728.260870 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82728.260870 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81894.117647 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81894.117647 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82870.967742 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82870.967742 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82878.181818 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82878.181818 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.235294 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.235294 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82930.348259 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82930.348259 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1154,120 +1154,120 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 6 system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20073000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20073000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5729500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5729500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20073000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28985500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20073000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28985500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20041500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20041500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5712000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5712000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20041500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8895000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28936500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20041500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8895000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28936500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72728.260870 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72728.260870 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72525.316456 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72525.316456 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72878.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72878.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.797468 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.797468 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 442 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 223000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 396 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 355 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 354 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::samples 396 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 486500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 396 # Request fanout histogram +system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2098750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2091500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 307f14079..bc5d2d1fc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20302000 # Number of ticks simulated final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10367 # Simulator instruction rate (inst/s) -host_op_rate 12141 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45828431 # Simulator tick rate (ticks/s) -host_mem_usage 248616 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host +host_inst_rate 93691 # Simulator instruction rate (inst/s) +host_op_rate 109699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 414022055 # Simulator tick rate (ticks/s) +host_mem_usage 265936 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -205,12 +205,12 @@ system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # By system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 6124000 # Total ticks spent queuing -system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6135000 # Total ticks spent queuing +system.physmem.totMemAccLat 14478750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13786.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32536.52 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s @@ -232,28 +232,28 @@ system.physmem_0.preEnergy 170775 # En system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3562500 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 5660100 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ) system.physmem_0.averagePower 656.916882 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank +system.physmem_0.totalIdleTime 12261000 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7351250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12409250 # Time in different power states system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 1478010 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 7415130 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ) @@ -267,12 +267,12 @@ system.physmem_1.memoryStateTime::ACT 2792000 # Ti system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2438 # Number of BP lookups -system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 449 # Number of BTB hits +system.cpu.branchPred.condPredicted 1441 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 523 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 913 # Number of BTB lookups +system.cpu.branchPred.BTBHits 446 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.849945 # BTB Hit Percentage system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. @@ -405,80 +405,80 @@ system.cpu.pwrStateResidencyTicks::ON 20302000 # Cu system.cpu.numCycles 40605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8314 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1089 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3900 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 180 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15914 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.856227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.206589 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9531 59.89% 59.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2501 15.72% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3361 21.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15914 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle +system.cpu.fetch.rate 0.282231 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5816 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5174 # Number of cycles decode is running +system.cpu.decode.RunCycles 5171 # Number of cycles decode is running system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 385 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 538 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 10171 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 385 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6927 # Number of cycles rename is idle system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4185 # Number of cycles rename is running +system.cpu.rename.RunCycles 4182 # Number of cycles rename is running system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename +system.cpu.rename.RenamedInsts 9091 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 462 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedOperands 9449 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41113 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3955 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued +system.cpu.iq.iqInstsIssued 7227 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 183 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 8218 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15914 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.454128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.844358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,147 +487,147 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15914 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7222 # Type of FU issued -system.cpu.iq.rate 0.177860 # Inst issue rate +system.cpu.iq.FU_type_0::total 7227 # Type of FU issued +system.cpu.iq.rate 0.177983 # Inst issue rate system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.198976 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31940 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 6623 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8632 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 349 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 385 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1287 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 320 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6823 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2442 # number of memory reference insts executed -system.cpu.iew.exec_branches 1297 # Number of branches executed +system.cpu.iew.exec_refs 2443 # number of memory reference insts executed +system.cpu.iew.exec_branches 1299 # Number of branches executed system.cpu.iew.exec_stores 1024 # Number of stores executed -system.cpu.iew.exec_rate 0.167836 # Inst execution rate -system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6631 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2981 # num instructions producing a value -system.cpu.iew.wb_consumers 5426 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back +system.cpu.iew.exec_rate 0.168033 # Inst execution rate +system.cpu.iew.wb_sent 6684 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6639 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2983 # num instructions producing a value +system.cpu.iew.wb_consumers 5430 # num instructions consuming a value +system.cpu.iew.wb_rate 0.163502 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549355 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 364 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15346 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.350450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.989791 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle @@ -635,7 +635,7 @@ system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15346 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,33 +686,33 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23226 # The number of ROB reads -system.cpu.rob.rob_writes 16730 # The number of ROB writes -system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23224 # The number of ROB reads +system.cpu.rob.rob_writes 16731 # The number of ROB writes +system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6765 # number of integer regfile reads -system.cpu.int_regfile_writes 3787 # number of integer regfile writes +system.cpu.int_regfile_reads 6850 # number of integer regfile reads +system.cpu.int_regfile_writes 3795 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24202 # number of cc regfile reads -system.cpu.cc_regfile_writes 2924 # number of cc regfile writes -system.cpu.misc_regfile_reads 2558 # number of misc regfile reads +system.cpu.cc_regfile_reads 24229 # number of cc regfile reads +system.cpu.cc_regfile_writes 2927 # number of cc regfile writes +system.cpu.misc_regfile_reads 2559 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.085192 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1923 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.447552 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164229 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id @@ -720,38 +720,38 @@ system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1181 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1181 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits -system.cpu.dcache.overall_hits::total 1906 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1903 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1903 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1903 # number of overall hits +system.cpu.dcache.overall_hits::total 1903 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses -system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 361 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 361 # number of overall misses +system.cpu.dcache.overall_misses::total 361 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12060000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20076500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20076500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20076500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20076500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -764,26 +764,26 @@ system.cpu.dcache.demand_accesses::cpu.data 2264 # system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.125833 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.159452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.159452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -792,16 +792,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1 # number of writebacks system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 217 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 217 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -810,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7989500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7989500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10584000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10584000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10584000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10584000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -826,67 +826,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77567.961165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77567.961165 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 137.523624 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3532 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.812709 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.523624 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.268601 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.268601 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8101 # Number of data accesses +system.cpu.icache.tags.tag_accesses 8095 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8095 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits -system.cpu.icache.overall_hits::total 3536 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses -system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 3532 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3532 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3532 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3532 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3532 # number of overall hits +system.cpu.icache.overall_hits::total 3532 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25091490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25091490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25091490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25091490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25091490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25091490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3898 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3898 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3898 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3898 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093894 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.093894 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.093894 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.093894 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.093894 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.093894 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68555.983607 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68555.983607 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68555.983607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68555.983607 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 9833 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked @@ -895,36 +895,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134 system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 44 # number of writebacks system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22025990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22025990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22025990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22025990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22025990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22025990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076706 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076706 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076706 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73665.518395 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73665.518395 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -934,16 +934,16 @@ system.cpu.l2cache.prefetcher.pfRemovedFull 0 # system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 17.362749 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9.237342 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.125407 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.001060 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -981,16 +981,16 @@ system.cpu.l2cache.overall_misses::cpu.data 133 # system.cpu.l2cache.overall_misses::total 424 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21666500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21666500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7828000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7828000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21666500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10288000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31954500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21666500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10288000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31954500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) @@ -1019,16 +1019,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74455.326460 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74455.326460 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75364.386792 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75364.386792 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1064,17 +1064,17 @@ system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6912500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6912500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19864000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9192500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29056500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19864000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9192500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1094,17 +1094,17 @@ system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1173,7 +1173,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 445 # Request fanout histogram system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2338250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 888fdd0d2..00c469890 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24405000 # Number of ticks simulated final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38911 # Simulator instruction rate (inst/s) -host_op_rate 38904 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189891987 # Simulator tick rate (ticks/s) -host_mem_usage 234100 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 119579 # Simulator instruction rate (inst/s) +host_op_rate 119550 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 583509526 # Simulator tick rate (ticks/s) +host_mem_usage 251420 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # By system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation -system.physmem.totQLat 7577250 # Total ticks spent queuing -system.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 7589250 # Total ticks spent queuing +system.physmem.totMemAccLat 16383000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16181.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34931.77 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s @@ -228,9 +228,9 @@ system.physmem_0.preEnergy 98670 # En system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 1603980 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 8337960 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ) @@ -247,29 +247,29 @@ system.physmem_1.preEnergy 333960 # En system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4214580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 89760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6593190 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 180480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 4208310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 89280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6602310 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 178560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 16490310 # Total energy per rank (pJ) -system.physmem_1.averagePower 675.693915 # Core power per rank (mW) +system.physmem_1.totalEnergy 16490760 # Total energy per rank (pJ) +system.physmem_1.averagePower 675.712354 # Core power per rank (mW) system.physmem_1.totalIdleTime 14889250 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 122500 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 470250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states system.physmem_1.memoryStateTime::ACT 8563750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 14468500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 14474500 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2188 # Number of BP lookups -system.cpu.branchPred.condPredicted 1456 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 424 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 587 # Number of BTB hits +system.cpu.branchPred.lookups 2177 # Number of BP lookups +system.cpu.branchPred.condPredicted 1448 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 422 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups +system.cpu.branchPred.BTBHits 589 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 252 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 33.108488 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. @@ -299,91 +299,91 @@ system.cpu.pwrStateResidencyTicks::ON 24405000 # Cu system.cpu.numCycles 48811 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5447 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 868 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 9085 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12947 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2177 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 842 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2046 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 261 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.853911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.140587 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 279 1.84% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 100 0.66% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 140 0.92% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.04% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11809 77.89% 77.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1506 9.93% 87.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 111 0.73% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 164 1.08% 89.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 279 1.84% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 101 0.67% 92.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 136 0.90% 93.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.04% 94.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 898 5.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2768 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 15162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.044601 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.265248 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8416 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3447 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2766 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 141 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 392 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 589 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12000 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11962 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 392 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8568 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 617 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2740 # Number of cycles rename is running +system.cpu.rename.RunCycles 2736 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11562 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11523 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6927 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13556 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13323 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 6897 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13509 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13276 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3635 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3605 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2464 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8995 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8118 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8108 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4006 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1995 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15162 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.534758 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.264874 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.35% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11839 78.08% 78.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1338 8.82% 86.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 727 4.79% 91.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 451 2.97% 94.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 343 2.26% 96.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 283 1.87% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 110 0.73% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.34% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15162 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available @@ -423,58 +423,58 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4767 58.79% 58.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2271 28.01% 86.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1063 13.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8118 # Type of FU issued -system.cpu.iq.rate 0.166315 # Inst issue rate +system.cpu.iq.FU_type_0::total 8108 # Type of FU issued +system.cpu.iq.rate 0.166110 # Inst issue rate system.cpu.iq.fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.022200 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31574 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13019 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7329 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8286 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1329 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed @@ -483,45 +483,45 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 392 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 487 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10600 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2464 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 335 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 436 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7776 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2123 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1596 # number of nop insts executed -system.cpu.iew.exec_refs 3178 # number of memory reference insts executed -system.cpu.iew.exec_branches 1363 # Number of branches executed +system.cpu.iew.exec_nop 1594 # number of nop insts executed +system.cpu.iew.exec_refs 3172 # number of memory reference insts executed +system.cpu.iew.exec_branches 1361 # Number of branches executed system.cpu.iew.exec_stores 1049 # Number of stores executed -system.cpu.iew.exec_rate 0.159595 # Inst execution rate -system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7339 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2867 # num instructions producing a value -system.cpu.iew.wb_consumers 4274 # num instructions consuming a value -system.cpu.iew.wb_rate 0.150355 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.159308 # Inst execution rate +system.cpu.iew.wb_sent 7424 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7331 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2863 # num instructions producing a value +system.cpu.iew.wb_consumers 4269 # num instructions consuming a value +system.cpu.iew.wb_rate 0.150192 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.670649 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4961 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.394599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.198950 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.394792 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.199270 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12101 84.66% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 885 6.19% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 521 3.65% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12095 84.66% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 883 6.18% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 522 3.65% 94.50% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 254 1.78% 96.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 160 1.12% 97.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 166 1.16% 98.56% # Number of insts commited each cycle @@ -531,7 +531,7 @@ system.cpu.commit.committed_per_cycle::8 102 0.71% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14293 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14286 # Number of insts commited each cycle system.cpu.commit.committedInsts 5640 # Number of instructions committed system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -582,46 +582,46 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5640 # Class of committed instruction system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 24800 # The number of ROB reads -system.cpu.rob.rob_writes 22133 # The number of ROB writes +system.cpu.rob.rob_reads 24772 # The number of ROB reads +system.cpu.rob.rob_writes 22085 # The number of ROB writes system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 33649 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4999 # Number of Instructions Simulated system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10560 # number of integer regfile reads -system.cpu.int_regfile_writes 5141 # number of integer regfile writes +system.cpu.int_regfile_reads 10585 # number of integer regfile reads +system.cpu.int_regfile_writes 5135 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 161 # number of misc regfile reads system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.124976 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2389 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.064286 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.124976 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022247 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022247 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 5940 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5940 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits -system.cpu.dcache.overall_hits::total 2395 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits +system.cpu.dcache.overall_hits::total 2389 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses @@ -638,22 +638,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 46928999 system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2900 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2900 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2900 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2900 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083542 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083542 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.176207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.176207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.176207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.176207 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency @@ -692,14 +692,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048276 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048276 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048276 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048276 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency @@ -710,57 +710,57 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 160.153151 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.858434 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.846386 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.115290 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078181 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078181 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 160.153151 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078200 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078200 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4432 # Number of data accesses +system.cpu.icache.tags.tag_accesses 4424 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4424 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits -system.cpu.icache.overall_hits::total 1613 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits +system.cpu.icache.overall_hits::total 1609 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35529000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35529000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35529000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35529000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35529000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35529000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213171 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.213171 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.213171 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.213171 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.213171 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.213171 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81302.059497 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 81302.059497 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 81302.059497 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 81302.059497 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35547000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35547000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35547000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35547000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35547000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35547000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2046 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2046 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2046 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213587 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.213587 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.213587 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.213587 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.213587 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.213587 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81343.249428 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 81343.249428 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 81343.249428 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 81343.249428 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 81343.249428 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 81343.249428 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,36 +781,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 332 system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28124000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28124000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28124000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28124000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28124000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28124000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162268 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.162268 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.162268 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84710.843373 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84710.843373 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84710.843373 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84710.843373 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84710.843373 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84710.843373 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 253.368786 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.183576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 91.185210 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004949 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007732 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id @@ -840,16 +840,16 @@ system.cpu.l2cache.overall_misses::cpu.data 140 # system.cpu.l2cache.overall_misses::total 469 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27593000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27593000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27593000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 40389500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27593000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40389500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) @@ -878,16 +878,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83869.300912 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83869.300912 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83869.300912 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86118.336887 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83869.300912 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86118.336887 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -908,16 +908,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 140 system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24303000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24303000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24303000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 35699500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24303000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 35699500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses @@ -932,16 +932,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73869.300912 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73869.300912 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index b83fdc852..4dafeb8f4 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000106 # Nu sim_ticks 106125 # Number of ticks simulated final_tick 106125 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 110492 # Simulator instruction rate (inst/s) -host_op_rate 110472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2077956 # Simulator tick rate (ticks/s) -host_mem_usage 415232 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 95829 # Simulator instruction rate (inst/s) +host_op_rate 95814 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1802278 # Simulator tick rate (ticks/s) +host_mem_usage 414992 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -401,13 +401,35 @@ system.ruby.miss_latency_hist_seqr::stdev 37.614530 system.ruby.miss_latency_hist_seqr | 577 39.20% 39.20% | 834 56.66% 95.86% | 40 2.72% 98.57% | 8 0.54% 99.12% | 8 0.54% 99.66% | 5 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1472 system.ruby.Directory.incomplete_times_seqr 1471 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997663 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.765826 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999350 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999359 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.983246 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.072357 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999991 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.055406 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999943 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.995053 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.985696 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995816 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.083033 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.766579 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 6.925795 system.ruby.network.routers0.msg_count.Control::2 1472 @@ -418,6 +440,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 11776 system.ruby.network.routers0.msg_bytes.Data::2 105696 system.ruby.network.routers0.msg_bytes.Response_Data::4 105984 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.766014 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.995307 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998681 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 6.925795 system.ruby.network.routers1.msg_count.Control::2 1472 @@ -428,6 +456,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 11776 system.ruby.network.routers1.msg_bytes.Data::2 105696 system.ruby.network.routers1.msg_bytes.Response_Data::4 105984 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.766466 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.992933 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.997993 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.988127 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.996561 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.766184 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.013833 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.990540 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.013870 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.997286 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.027703 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.766334 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 6.925795 system.ruby.network.routers2.msg_count.Control::2 1472 diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 1c774fd71..f6ed1582b 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21268000 # Number of ticks simulated -final_tick 21268000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21189000 # Number of ticks simulated +final_tick 21189000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49400 # Simulator instruction rate (inst/s) -host_op_rate 49392 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 181337178 # Simulator tick rate (ticks/s) -host_mem_usage 231948 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 143245 # Simulator instruction rate (inst/s) +host_op_rate 143198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 523712790 # Simulator tick rate (ticks/s) +host_mem_usage 249592 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory system.physmem.bytes_read::total 28352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1032160993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 300921572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1333082565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1032160993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1032160993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1032160993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 300921572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1333082565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 1029968380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308084383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1338052763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1029968380 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1029968380 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1029968380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308084383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1338052763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -47,7 +47,7 @@ system.physmem.perBankRdBursts::1 42 # Pe system.physmem.perBankRdBursts::2 55 # Per bank write bursts system.physmem.perBankRdBursts::3 58 # Per bank write bursts system.physmem.perBankRdBursts::4 53 # Per bank write bursts -system.physmem.perBankRdBursts::5 62 # Per bank write bursts +system.physmem.perBankRdBursts::5 61 # Per bank write bursts system.physmem.perBankRdBursts::6 52 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 9 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21217500 # Total gap between requests +system.physmem.totGap 21128500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445 # Read request sizes (log2) +system.physmem.readPktSize::6 444 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -92,9 +92,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,93 +187,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.573333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.062906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 340.509998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23 30.67% 30.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 24.00% 54.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 14.67% 69.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 2.67% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.00% 76.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 5.33% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.67% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 4.00% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 12.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation -system.physmem.totQLat 5980000 # Total ticks spent queuing -system.physmem.totMemAccLat 14323750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13438.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.631579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 212.894378 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 337.912685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 22.37% 53.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12 15.79% 69.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 2.63% 72.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 3.95% 76.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 5.26% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.63% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation +system.physmem.totQLat 5920000 # Total ticks spent queuing +system.physmem.totMemAccLat 14245000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13333.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32188.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1339.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32083.33 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1341.07 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1339.10 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1341.07 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.46 # Data bus utilization in percentage -system.physmem.busUtilRead 10.46 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.48 # Data bus utilization in percentage +system.physmem.busUtilRead 10.48 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 360 # Number of row buffer hits during reads +system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47679.78 # Average gap between requests -system.physmem.pageHitRate 80.90 # Row buffer hit rate, read and write combined +system.physmem.avgGap 47586.71 # Average gap between requests +system.physmem.pageHitRate 80.63 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 528360 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 254265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2877420 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2870280 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3922170 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3925590 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5666370 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 5657820 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 38400 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 14570505 # Total energy per rank (pJ) -system.physmem_0.averagePower 685.066353 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12593250 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 14532315 # Total energy per rank (pJ) +system.physmem_0.averagePower 685.810052 # Core power per rank (mW) +system.physmem_0.totalIdleTime 12505250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 167250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8137250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12426000 # Time in different power states -system.physmem_1.actEnergy 78540 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 30360 # Energy for precharge commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 100250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8146250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12405000 # Time in different power states +system.physmem_1.actEnergy 85680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 34155 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 299880 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 747840 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1408800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6431880 # Energy for active power-down per rank (pJ) +system.physmem_1.actBackEnergy 759810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1412160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6380010 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 712320 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10938900 # Total energy per rank (pJ) -system.physmem_1.averagePower 514.317955 # Core power per rank (mW) -system.physmem_1.totalIdleTime 13775500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3585000 # Time in different power states +system.physmem_1.totalEnergy 10913295 # Total energy per rank (pJ) +system.physmem_1.averagePower 515.021000 # Core power per rank (mW) +system.physmem_1.totalIdleTime 13660000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3594000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 1854750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1201500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 14106750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2411 # Number of BP lookups -system.cpu.branchPred.condPredicted 1982 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::ACT 1229000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13991250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2458 # Number of BP lookups +system.cpu.branchPred.condPredicted 2033 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2056 # Number of BTB lookups -system.cpu.branchPred.BTBHits 693 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2104 # Number of BTB lookups +system.cpu.branchPred.BTBHits 724 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.706226 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 227 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 130 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 19 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 111 # Number of indirect misses. +system.cpu.branchPred.BTBHitPct 34.410646 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 228 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 36 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 18 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 117 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 37 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -295,244 +295,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21268000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42537 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21189000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 42379 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7674 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13369 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2411 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4149 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 849 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7639 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13455 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2458 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4277 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1861 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12420 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.076409 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.475819 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1865 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.075368 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.471061 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10086 81.21% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 166 1.34% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 214 1.72% 84.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 147 1.18% 85.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 241 1.94% 87.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 150 1.21% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 280 2.25% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 148 1.19% 92.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 988 7.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10164 81.23% 81.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 163 1.30% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 210 1.68% 84.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 146 1.17% 85.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 247 1.97% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 148 1.18% 88.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 304 2.43% 90.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.26% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 972 7.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12420 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.056680 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.314291 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7247 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2821 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1946 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.058000 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.317492 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7217 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2933 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1957 # Number of cycles decode is running system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 276 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 324 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 791 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 276 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7415 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 463 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1897 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11042 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu.decode.DecodedInsts 11520 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 456 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7386 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 930 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 461 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1556 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11074 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1522 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9711 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17897 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17871 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1496 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9775 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17991 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17965 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4713 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4777 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 381 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1937 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1590 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 402 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1923 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8808 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3474 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12420 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.709179 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.511732 # Number of insts issued each cycle +system.cpu.memDep0.conflictingStores 32 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8807 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4477 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3567 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.703884 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.500750 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9305 74.92% 74.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 969 7.80% 82.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 656 5.28% 88.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 462 3.72% 91.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 429 3.45% 95.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 293 2.36% 97.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 212 1.71% 99.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.52% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 30 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9387 75.02% 75.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 964 7.70% 82.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 667 5.33% 88.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 467 3.73% 91.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 439 3.51% 95.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 290 2.32% 97.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 213 1.70% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 56 0.45% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 29 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12420 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12512 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12 6.06% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 88 44.44% 50.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 87 43.94% 94.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 11 5.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 12 6.22% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 87 45.08% 51.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83 43.01% 94.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 11 5.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5530 62.78% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1439 16.34% 99.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5542 62.93% 62.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1815 20.61% 83.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1422 16.15% 99.70% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 2 0.02% 99.73% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 24 0.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8808 # Type of FU issued -system.cpu.iq.rate 0.207067 # Inst issue rate -system.cpu.iq.fu_busy_cnt 198 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30220 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14647 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8115 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8807 # Type of FU issued +system.cpu.iq.rate 0.207815 # Inst issue rate +system.cpu.iq.fu_busy_cnt 193 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021914 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30293 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14716 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8133 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8967 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8961 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 39 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 84 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 976 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 544 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 962 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 524 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 276 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 722 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 71 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1937 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1590 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 818 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10269 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1923 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8463 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1703 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 345 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8488 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1719 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 319 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3080 # number of memory reference insts executed -system.cpu.iew.exec_branches 1358 # Number of branches executed -system.cpu.iew.exec_stores 1377 # Number of stores executed -system.cpu.iew.exec_rate 0.198956 # Inst execution rate -system.cpu.iew.wb_sent 8242 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8142 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4448 # num instructions producing a value -system.cpu.iew.wb_consumers 7158 # num instructions consuming a value -system.cpu.iew.wb_rate 0.191410 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.621403 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 3083 # number of memory reference insts executed +system.cpu.iew.exec_branches 1364 # Number of branches executed +system.cpu.iew.exec_stores 1364 # Number of stores executed +system.cpu.iew.exec_rate 0.200288 # Inst execution rate +system.cpu.iew.wb_sent 8262 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8160 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4466 # num instructions producing a value +system.cpu.iew.wb_consumers 7207 # num instructions consuming a value +system.cpu.iew.wb_rate 0.192548 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.619675 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4479 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11718 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.494282 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.358473 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11808 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.490515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.351526 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9553 81.52% 81.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 850 7.25% 88.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 527 4.50% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 215 1.83% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 176 1.50% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 112 0.96% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 126 1.08% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 49 0.42% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9643 81.66% 81.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 845 7.16% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 531 4.50% 93.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 215 1.82% 95.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 177 1.50% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 110 0.93% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 132 1.12% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 50 0.42% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 105 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11808 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -582,310 +582,310 @@ system.cpu.commit.op_class_0::FloatMemWrite 19 0.33% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21844 # The number of ROB reads -system.cpu.rob.rob_writes 21175 # The number of ROB writes -system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30117 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 21974 # The number of ROB reads +system.cpu.rob.rob_writes 21247 # The number of ROB writes +system.cpu.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29867 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.344095 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.344095 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136164 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136164 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13368 # number of integer regfile reads -system.cpu.int_regfile_writes 7153 # number of integer regfile writes +system.cpu.cpi 7.316816 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.316816 # CPI: Total CPI of All Threads +system.cpu.ipc 0.136671 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.136671 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13468 # number of integer regfile reads +system.cpu.int_regfile_writes 7187 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.389343 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2206 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.627451 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 66.953799 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2204 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 104 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.192308 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.389343 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015720 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015720 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5390 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5390 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1485 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1485 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 66.953799 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.016346 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.016346 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.025391 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5386 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5386 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2206 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2206 # number of overall hits -system.cpu.dcache.overall_hits::total 2206 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2204 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2204 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2204 # number of overall hits +system.cpu.dcache.overall_hits::total 2204 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses -system.cpu.dcache.overall_misses::total 438 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8211000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8211000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32489496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32489496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40700496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40700496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40700496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40700496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1598 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8129500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8129500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32497996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32497996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40627496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40627496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40627496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40627496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1595 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2644 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2644 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2644 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2644 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070713 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070713 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2641 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2641 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2641 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2641 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070219 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070219 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165658 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165658 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165658 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165658 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72663.716814 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72663.716814 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99967.680000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 99967.680000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92923.506849 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92923.506849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92923.506849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92923.506849 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 612 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.165468 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165468 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165468 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165468 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72584.821429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72584.821429 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99993.833846 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 99993.833846 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 92969.098398 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 92969.098398 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 102 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.222222 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 334 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 334 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 334 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 332 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 332 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 332 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 104 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 104 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 104 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 104 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4669500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4669500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4693998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4693998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9363498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9363498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9363498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9363498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035670 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035670 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 105 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 105 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 105 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 105 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4818000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4818000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4694498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4694498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9512498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9512498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9512498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9512498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036364 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036364 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039334 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.039334 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039334 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.039334 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81921.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81921.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99872.297872 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99872.297872 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90033.634615 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90033.634615 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90033.634615 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90033.634615 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039758 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.039758 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039758 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.039758 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83068.965517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83068.965517 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99882.936170 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99882.936170 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.912200 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1425 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 168.700112 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1435 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.083095 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.111748 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.912200 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082477 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082477 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 168.700112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082373 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082373 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4071 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4071 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1425 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1425 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1425 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1425 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1425 # number of overall hits -system.cpu.icache.overall_hits::total 1425 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 436 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 436 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 436 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 436 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 436 # number of overall misses -system.cpu.icache.overall_misses::total 436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33901500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33901500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33901500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33901500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33901500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33901500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1861 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1861 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1861 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1861 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234283 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.234283 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234283 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.234283 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234283 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.234283 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77755.733945 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77755.733945 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77755.733945 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77755.733945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77755.733945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77755.733945 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4079 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4079 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits +system.cpu.icache.overall_hits::total 1435 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 430 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 430 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 430 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 430 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 430 # number of overall misses +system.cpu.icache.overall_misses::total 430 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33426000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33426000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33426000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33426000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33426000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33426000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1865 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1865 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1865 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1865 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230563 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.230563 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.230563 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.230563 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.230563 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.230563 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77734.883721 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77734.883721 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77734.883721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77734.883721 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 569 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 113.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 113.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28298000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28298000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28298000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28298000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28298000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28298000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188071 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188071 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188071 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80851.428571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80851.428571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80851.428571 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 80851.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80851.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 80851.428571 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28154000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28154000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28154000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28154000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28154000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28154000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.187668 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.187668 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.187668 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80440 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80440 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 231.224808 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 232.210591 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.018059 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.022573 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.706281 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 63.518527 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001938 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007056 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.990617 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 65.219974 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001990 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007087 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits +system.cpu.l2cache.tags.tag_accesses 4083 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4083 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits +system.cpu.l2cache.demand_hits::total 10 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 8 # number of overall hits +system.cpu.l2cache.overall_hits::total 10 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 344 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 344 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses -system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4620000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4620000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27705000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27705000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4563000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4563000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27705000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9183000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36888000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27705000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9183000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36888000 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 342 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 342 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 56 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 342 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 103 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 342 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 103 # number of overall misses +system.cpu.l2cache.overall_misses::total 445 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4620500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4620500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27538000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27538000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4709000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4709000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27538000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9329500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36867500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27538000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9329500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36867500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 57 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 57 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 58 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 58 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 104 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 105 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 455 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 104 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 105 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 455 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.982857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.964912 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.964912 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980769 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.982379 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980769 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.982379 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98297.872340 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98297.872340 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80537.790698 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80537.790698 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82963.636364 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82963.636364 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80537.790698 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90029.411765 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82708.520179 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80537.790698 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90029.411765 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82708.520179 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.977143 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.977143 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.965517 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.965517 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.977143 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.978022 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.977143 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.978022 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98308.510638 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98308.510638 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80520.467836 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80520.467836 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84089.285714 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84089.285714 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80520.467836 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82848.314607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80520.467836 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82848.314607 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -894,119 +894,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4150000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24275000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24275000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4033000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4033000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24275000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8183000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32458000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24275000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8183000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32458000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 342 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 342 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 56 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24128000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24128000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4159000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4159000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24128000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32437500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24128000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8309500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32437500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964912 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.982379 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.982379 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88297.872340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88297.872340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70566.860465 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70566.860465 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73327.272727 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73327.272727 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70566.860465 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80225.490196 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72775.784753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70566.860465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80225.490196 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72775.784753 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.977143 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.965517 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.978022 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.978022 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88308.510638 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88308.510638 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70549.707602 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70549.707602 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74267.857143 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74267.857143 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 455 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 57 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 209 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 454 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.017621 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.131715 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 455 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021978 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.146773 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 446 98.24% 98.24% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8 1.76% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 97.80% 97.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10 2.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 454 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 227000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 455 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 227500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 156000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 444 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 396 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 398 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 887 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 445 # Request fanout histogram +system.membus.snoop_fanout::samples 444 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 445 # Request fanout histogram +system.membus.snoop_fanout::total 444 # Request fanout histogram system.membus.reqLayer0.occupancy 553000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2325250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 10.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2325750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt index 6dc71361b..7c3cea8ee 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu sim_ticks 14435000 # Number of ticks simulated final_tick 14435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 13240 # Simulator instruction rate (inst/s) -host_op_rate 13237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119615611 # Simulator tick rate (ticks/s) -host_mem_usage 232036 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 136295 # Simulator instruction rate (inst/s) +host_op_rate 136181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1229999304 # Simulator tick rate (ticks/s) +host_mem_usage 249560 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 1597 # Number of instructions simulated sim_ops 1597 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -261,16 +261,16 @@ system.pwrStateResidencyTicks::UNDEFINED 14435000 # Cu system.cpu.branchPred.lookups 995 # Number of BP lookups system.cpu.branchPred.condPredicted 543 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 945 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 944 # Number of BTB lookups system.cpu.branchPred.BTBHits 100 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.582011 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 10.593220 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 204 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 202 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 11 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 193 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectMisses 191 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt index 25d8ca24a..4e1344fa0 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu sim_ticks 7939500 # Number of ticks simulated final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22942 # Simulator instruction rate (inst/s) -host_op_rate 22935 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 114711600 # Simulator tick rate (ticks/s) -host_mem_usage 232976 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 81718 # Simulator instruction rate (inst/s) +host_op_rate 81674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 408398393 # Simulator tick rate (ticks/s) +host_mem_usage 251348 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 1587 # Number of instructions simulated sim_ops 1587 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -258,18 +258,18 @@ system.physmem_1.memoryStateTime::PRE_PDN 0 # T system.physmem_1.memoryStateTime::ACT 0 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1252 # Number of BP lookups -system.cpu.branchPred.condPredicted 681 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1255 # Number of BP lookups +system.cpu.branchPred.condPredicted 684 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1186 # Number of BTB lookups -system.cpu.branchPred.BTBHits 300 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1188 # Number of BTB lookups +system.cpu.branchPred.BTBHits 302 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.295110 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 25.420875 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 253 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 228 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 254 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 24 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 230 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -296,9 +296,9 @@ system.cpu.numCycles 15880 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 4970 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1252 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 325 # Number of branches that fetch has predicted taken +system.cpu.fetch.Insts 4974 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1255 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 326 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -307,71 +307,71 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 1 # system.cpu.fetch.CacheLines 803 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.117607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.502607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.118507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.504003 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91 2.05% 86.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 45 1.01% 87.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 71 1.60% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 65 1.46% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 1.44% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90 2.02% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 45 1.01% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 71 1.60% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 65 1.46% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 1.46% 91.52% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078841 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.312972 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 3140 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 349 # Number of cycles decode is blocked +system.cpu.fetch.branchRate 0.079030 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.313224 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 3139 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 350 # Number of cycles decode is blocked system.cpu.decode.RunCycles 756 # Number of cycles decode is running system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 187 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 287 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3862 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 3866 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 3239 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 107 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 3237 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 108 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 672 # Number of cycles rename is running +system.cpu.rename.RunCycles 673 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3496 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 3508 # Number of instructions processed by rename system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.RenamedOperands 2449 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4481 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4481 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 2456 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4500 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4500 # Number of integer rename lookups system.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1372 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 1379 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 82 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 548 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 547 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3003 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 3013 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2694 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2703 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1432 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 769 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 1442 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 770 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.605802 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.426720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.607826 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.430977 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185 4.16% 89.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 180 4.05% 93.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 147 3.31% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 65 1.46% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 57 1.28% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 182 4.09% 88.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 180 4.05% 93.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 148 3.33% 96.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 66 1.48% 97.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 58 1.30% 99.15% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle @@ -417,73 +417,73 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1755 65.14% 65.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 512 19.01% 84.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 417 15.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1765 65.30% 65.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 511 18.90% 84.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 417 15.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2694 # Type of FU issued -system.cpu.iq.rate 0.169647 # Inst issue rate +system.cpu.iq.FU_type_0::total 2703 # Type of FU issued +system.cpu.iq.rate 0.170214 # Inst issue rate system.cpu.iq.fu_busy_cnt 70 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025984 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 9926 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4453 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2310 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.025897 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 9944 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4473 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2318 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2755 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 2764 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 259 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 258 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 191 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 192 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 106 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 107 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3020 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 3030 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 548 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 547 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall @@ -491,41 +491,41 @@ system.cpu.iew.memOrderViolationEvents 1 # Nu system.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2452 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 472 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 242 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2459 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 471 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 244 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 847 # number of memory reference insts executed -system.cpu.iew.exec_branches 563 # Number of branches executed +system.cpu.iew.exec_refs 846 # number of memory reference insts executed +system.cpu.iew.exec_branches 566 # Number of branches executed system.cpu.iew.exec_stores 375 # Number of stores executed -system.cpu.iew.exec_rate 0.154408 # Inst execution rate -system.cpu.iew.wb_sent 2361 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2310 # cumulative count of insts written-back -system.cpu.iew.wb_producers 793 # num instructions producing a value -system.cpu.iew.wb_consumers 1130 # num instructions consuming a value -system.cpu.iew.wb_rate 0.145466 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.701770 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 1436 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.154849 # Inst execution rate +system.cpu.iew.wb_sent 2369 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2318 # cumulative count of insts written-back +system.cpu.iew.wb_producers 798 # num instructions producing a value +system.cpu.iew.wb_consumers 1140 # num instructions consuming a value +system.cpu.iew.wb_rate 0.145970 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.700000 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 1446 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 4156 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.381858 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.174026 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 4155 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.381949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.175996 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 3562 85.71% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 208 5.00% 90.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 146 3.51% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 85 2.05% 96.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 60 1.44% 97.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34 0.82% 98.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 3563 85.75% 85.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 208 5.01% 90.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 142 3.42% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86 2.07% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 60 1.44% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 35 0.84% 98.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 4156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 4155 # Number of insts commited each cycle system.cpu.commit.committedInsts 1587 # Number of instructions committed system.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,8 +576,8 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1587 # Class of committed instruction system.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 7041 # The number of ROB reads -system.cpu.rob.rob_writes 6340 # The number of ROB writes +system.cpu.rob.rob_reads 7050 # The number of ROB reads +system.cpu.rob.rob_writes 6361 # The number of ROB writes system.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1587 # Number of Instructions Simulated @@ -586,14 +586,14 @@ system.cpu.cpi 10.006301 # CP system.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads system.cpu.ipc 0.099937 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3068 # number of integer regfile reads -system.cpu.int_regfile_writes 1663 # number of integer regfile writes +system.cpu.int_regfile_reads 3116 # number of integer regfile reads +system.cpu.int_regfile_writes 1668 # number of integer regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 626 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 625 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 18.969697 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 18.939394 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy @@ -601,17 +601,17 @@ system.cpu.dcache.tags.occ_percent::total 0.005903 # A system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1497 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1497 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 1495 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1495 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 432 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 432 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 431 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 431 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 626 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 626 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 626 # number of overall hits -system.cpu.dcache.overall_hits::total 626 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 625 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 625 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 625 # number of overall hits +system.cpu.dcache.overall_hits::total 625 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 21 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses @@ -628,22 +628,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7406500 system.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 453 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 452 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 452 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 732 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 732 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 732 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 732 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046358 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.046358 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 731 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046460 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.046460 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.144809 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.144809 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.144809 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.144809 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.145007 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.145007 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.145007 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.145007 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency @@ -682,14 +682,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500 system.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035320 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035320 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.046448 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.046448 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.046512 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.046512 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79527.777778 # average WriteReq mshr miss latency diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt index e859af8d4..d3136e926 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27947 # Number of ticks simulated final_tick 27947 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19868 # Simulator instruction rate (inst/s) -host_op_rate 19863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 349695 # Simulator tick rate (ticks/s) -host_mem_usage 390760 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 89967 # Simulator instruction rate (inst/s) +host_op_rate 89916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1582597 # Simulator tick rate (ticks/s) +host_mem_usage 409032 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 1587 # Number of instructions simulated sim_ops 1587 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -397,13 +397,35 @@ system.ruby.miss_latency_hist_seqr::stdev 27.345330 system.ruby.miss_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% system.ruby.miss_latency_hist_seqr::total 438 system.ruby.Directory.incomplete_times_seqr 437 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.986546 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.686704 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.997531 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.997567 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 1727 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 438 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 2165 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.904322 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077501 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999964 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.062402 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999785 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.981215 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.918205 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.984113 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.093316 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.689566 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.800479 system.ruby.network.routers0.msg_count.Control::2 438 @@ -414,6 +436,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 3504 system.ruby.network.routers0.msg_bytes.Data::2 31248 system.ruby.network.routers0.msg_bytes.Response_Data::4 31536 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.687419 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.973021 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.994991 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.800479 system.ruby.network.routers1.msg_count.Control::2 438 @@ -424,6 +452,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 3504 system.ruby.network.routers1.msg_bytes.Data::2 31248 system.ruby.network.routers1.msg_bytes.Response_Data::4 31536 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.689137 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.959425 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.992379 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.932017 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.986940 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.688064 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015529 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.945756 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015672 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.989695 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.031201 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.688636 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.800479 system.ruby.network.routers2.msg_count.Control::2 438 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index c1f6ae8aa..90c8ea4fc 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu sim_ticks 86746 # Number of ticks simulated final_tick 86746 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 115505 # Simulator instruction rate (inst/s) -host_op_rate 115448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1879120 # Simulator tick rate (ticks/s) -host_mem_usage 414144 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 122857 # Simulator instruction rate (inst/s) +host_op_rate 122829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1999767 # Simulator tick rate (ticks/s) +host_mem_usage 415460 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -381,13 +381,35 @@ system.ruby.miss_latency_hist_seqr::stdev 35.397665 system.ruby.miss_latency_hist_seqr | 610 47.32% 47.32% | 633 49.11% 96.43% | 36 2.79% 99.22% | 1 0.08% 99.30% | 6 0.47% 99.77% | 2 0.16% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1289 system.ruby.Directory.incomplete_times_seqr 1288 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.995735 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.745697 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999205 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999216 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.969659 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077916 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999988 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059345 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999931 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.993948 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.974063 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.994882 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.088925 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.746619 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.418209 system.ruby.network.routers0.msg_count.Control::2 1289 @@ -398,6 +420,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.745928 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.991446 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998386 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.418209 system.ruby.network.routers1.msg_count.Control::2 1289 @@ -408,6 +436,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.746481 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.987135 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.997545 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.978443 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.995792 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.746135 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.982801 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996680 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029672 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.746320 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.418209 system.ruby.network.routers2.msg_count.Control::2 1289 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index ff0e9261d..136389a07 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,55 +1,55 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22466500 # Number of ticks simulated -final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 22516500 # Number of ticks simulated +final_tick 22516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24766 # Simulator instruction rate (inst/s) -host_op_rate 44863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103395613 # Simulator tick rate (ticks/s) -host_mem_usage 253532 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 69174 # Simulator instruction rate (inst/s) +host_op_rate 125309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 289442861 # Simulator tick rate (ticks/s) +host_mem_usage 271352 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 26752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory +system.physmem.bytes_read::total 26688 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 418 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 789085972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 401664701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1190750673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 789085972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 789085972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 789085972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 401664701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1190750673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 418 # Number of read requests accepted +system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory +system.physmem.num_reads::total 417 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 787333733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 397930407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1185264140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 787333733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 787333733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 787333733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 397930407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1185264140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 418 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26752 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26752 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 32 # Per bank write bursts +system.physmem.perBankRdBursts::0 31 # Per bank write bursts system.physmem.perBankRdBursts::1 1 # Per bank write bursts system.physmem.perBankRdBursts::2 5 # Per bank write bursts system.physmem.perBankRdBursts::3 8 # Per bank write bursts -system.physmem.perBankRdBursts::4 50 # Per bank write bursts +system.physmem.perBankRdBursts::4 51 # Per bank write bursts system.physmem.perBankRdBursts::5 44 # Per bank write bursts system.physmem.perBankRdBursts::6 21 # Per bank write bursts -system.physmem.perBankRdBursts::7 37 # Per bank write bursts +system.physmem.perBankRdBursts::7 36 # Per bank write bursts system.physmem.perBankRdBursts::8 24 # Per bank write bursts system.physmem.perBankRdBursts::9 71 # Per bank write bursts system.physmem.perBankRdBursts::10 64 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22337000 # Total gap between requests +system.physmem.totGap 22387500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 418 # Read request sizes (log2) +system.physmem.readPktSize::6 417 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -92,9 +92,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,336 +187,336 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.568421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.892164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 259.040400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 37 38.95% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 23 24.21% 63.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 16.84% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.32% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.11% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.16% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation -system.physmem.totQLat 6799250 # Total ticks spent queuing -system.physmem.totMemAccLat 14636750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16266.15 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 239.673469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.283411 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.721287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41 41.84% 41.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22 22.45% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 16.33% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 7.14% 87.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 1.02% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.06% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.04% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.04% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4 4.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation +system.physmem.totQLat 6651000 # Total ticks spent queuing +system.physmem.totMemAccLat 14469750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15949.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35016.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 34699.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1185.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1185.26 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.30 # Data bus utilization in percentage -system.physmem.busUtilRead 9.30 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.26 # Data bus utilization in percentage +system.physmem.busUtilRead 9.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 310 # Number of row buffer hits during reads +system.physmem.readRowHits 307 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53437.80 # Average gap between requests -system.physmem.pageHitRate 74.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 285600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1413720 # Energy for read commands per rank (pJ) +system.physmem.avgGap 53687.05 # Average gap between requests +system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 307020 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140415 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1406580 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2399130 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7645980 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 138240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 2488050 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 7581570 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 138720 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13267425 # Total energy per rank (pJ) -system.physmem_0.averagePower 590.516301 # Core power per rank (mW) -system.physmem_0.totalIdleTime 17035500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states +system.physmem_0.totalEnergy 13319955 # Total energy per rank (pJ) +system.physmem_0.averagePower 591.537915 # Core power per rank (mW) +system.physmem_0.totalIdleTime 16888750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 359250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 4794250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16769500 # Time in different power states -system.physmem_1.actEnergy 485520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 361000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 4997500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 16620500 # Time in different power states +system.physmem_1.actEnergy 478380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 231495 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2962290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7183140 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 2961150 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 80160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 7211640 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ) -system.physmem_1.averagePower 612.009347 # Core power per rank (mW) -system.physmem_1.totalIdleTime 14672000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 109000 # Time in different power states +system.physmem_1.totalEnergy 13762905 # Total energy per rank (pJ) +system.physmem_1.averagePower 611.209282 # Core power per rank (mW) +system.physmem_1.totalIdleTime 15691750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6091750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 15742250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 3488 # Number of BP lookups -system.cpu.branchPred.condPredicted 3488 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 571 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2960 # Number of BTB lookups +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 6065500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 15828000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 3542 # Number of BP lookups +system.cpu.branchPred.condPredicted 3542 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 576 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 3006 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 360 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 94 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2960 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 483 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2477 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 410 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 386 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 97 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3006 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 514 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2492 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 416 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22466500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44934 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22516500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 45034 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12177 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15717 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3488 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 843 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10477 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 12047 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16169 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3542 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 900 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 10333 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 78 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1414 # Number of stall cycles due to pending traps +system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1582 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 24836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.141770 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.668775 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 2077 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 24737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.175931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.701309 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20599 82.94% 82.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 175 0.70% 83.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 165 0.66% 84.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 0.91% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 209 0.84% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 222 0.89% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 269 1.08% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 159 0.64% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2813 11.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20389 82.42% 82.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 0.72% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 168 0.68% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 246 0.99% 84.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 215 0.87% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 220 0.89% 86.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 262 1.06% 87.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 167 0.68% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2892 11.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 24836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077625 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.349780 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12221 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8128 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3370 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 24737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.078652 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.359040 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12032 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8141 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3437 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26405 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 26977 # Number of instructions handled by decode system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12481 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1971 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1213 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3524 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4987 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24875 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 82 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4849 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 27762 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 60616 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 34638 # Number of integer rename lookups +system.cpu.rename.IdleCycles 12302 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2135 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1085 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3589 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4966 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 25351 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 77 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 4831 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 28444 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61768 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 35524 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16699 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1436 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2622 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1598 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21775 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18112 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 144 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12051 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16553 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.710701 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 17381 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 24 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1430 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2685 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1593 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 22118 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18234 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 157 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12393 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17118 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 24737 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.737114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.712019 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19689 79.28% 79.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1202 4.84% 84.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 867 3.49% 87.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 814 3.28% 93.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 136 0.55% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19548 79.02% 79.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1204 4.87% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 865 3.50% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 579 2.34% 89.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 831 3.36% 93.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 615 2.49% 95.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 628 2.54% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 340 1.37% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127 0.51% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 24836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 24737 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 223 79.93% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 41 14.70% 94.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 5.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 218 79.85% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 40 14.65% 94.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 5.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14478 79.94% 79.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2258 12.47% 92.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1357 7.49% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14605 80.10% 80.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.03% 80.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2269 12.44% 92.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1341 7.35% 99.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 4 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18112 # Type of FU issued -system.cpu.iq.rate 0.403080 # Inst issue rate -system.cpu.iq.fu_busy_cnt 279 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015404 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 61475 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 33854 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16418 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18234 # Type of FU issued +system.cpu.iq.rate 0.404894 # Inst issue rate +system.cpu.iq.fu_busy_cnt 273 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014972 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 61627 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 34538 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16576 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18385 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18501 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 199 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1569 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1632 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 663 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 658 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1482 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 1518 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21798 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2622 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1598 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 22140 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2685 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1593 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 680 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 798 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17038 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2047 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 127 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 676 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 803 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17166 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2051 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1068 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3306 # number of memory reference insts executed -system.cpu.iew.exec_branches 1731 # Number of branches executed -system.cpu.iew.exec_stores 1259 # Number of stores executed -system.cpu.iew.exec_rate 0.379178 # Inst execution rate -system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16422 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11018 # num instructions producing a value -system.cpu.iew.wb_consumers 17146 # num instructions consuming a value -system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642599 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 3303 # number of memory reference insts executed +system.cpu.iew.exec_branches 1740 # Number of branches executed +system.cpu.iew.exec_stores 1252 # Number of stores executed +system.cpu.iew.exec_rate 0.381179 # Inst execution rate +system.cpu.iew.wb_sent 16892 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16580 # cumulative count of insts written-back +system.cpu.iew.wb_producers 11141 # num instructions producing a value +system.cpu.iew.wb_consumers 17351 # num instructions consuming a value +system.cpu.iew.wb_rate 0.368166 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642096 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12392 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.307612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 22646 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.430407 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.314219 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19537 85.71% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1003 4.40% 90.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 565 2.48% 92.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 124 0.54% 98.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.32% 98.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 248 1.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19391 85.63% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1011 4.46% 90.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 560 2.47% 92.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 726 3.21% 95.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 383 1.69% 97.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 128 0.57% 98.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 118 0.52% 98.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.33% 98.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 255 1.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 22793 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 22646 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -566,283 +566,283 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 248 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 44342 # The number of ROB reads -system.cpu.rob.rob_writes 45672 # The number of ROB writes -system.cpu.timesIdled 156 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20098 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 44530 # The number of ROB reads +system.cpu.rob.rob_writes 46401 # The number of ROB writes +system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20297 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.352045 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.352045 # CPI: Total CPI of All Threads -system.cpu.ipc 0.119731 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.119731 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21663 # number of integer regfile reads -system.cpu.int_regfile_writes 13219 # number of integer regfile writes +system.cpu.cpi 8.370632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.370632 # CPI: Total CPI of All Threads +system.cpu.ipc 0.119465 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.119465 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21947 # number of integer regfile reads +system.cpu.int_regfile_writes 13377 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8286 # number of cc regfile reads -system.cpu.cc_regfile_writes 5066 # number of cc regfile writes -system.cpu.misc_regfile_reads 7640 # number of misc regfile reads +system.cpu.cc_regfile_reads 8355 # number of cc regfile reads +system.cpu.cc_regfile_writes 5130 # number of cc regfile writes +system.cpu.misc_regfile_reads 7644 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.537314 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 81.908470 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2549 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 18.207143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.537314 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5567 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5567 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2520 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2520 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2520 # number of overall hits -system.cpu.dcache.overall_hits::total 2520 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses -system.cpu.dcache.overall_misses::total 193 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10224000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10224000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7069500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7069500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17293500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17293500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17293500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17293500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1778 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 81.908470 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019997 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019997 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5608 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5608 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1687 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1687 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2549 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2549 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2549 # number of overall hits +system.cpu.dcache.overall_hits::total 2549 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 185 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 185 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 185 # number of overall misses +system.cpu.dcache.overall_misses::total 185 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9812000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9812000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6772000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6772000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16584000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16584000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16584000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16584000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1799 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065804 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065804 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.071139 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87384.615385 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87384.615385 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93019.736842 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 93019.736842 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 89603.626943 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 89603.626943 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2734 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2734 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2734 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2734 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062257 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062257 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078075 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078075 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067666 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067666 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067666 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067666 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87607.142857 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87607.142857 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 92767.123288 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 92767.123288 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 89643.243243 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 89643.243243 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 89643.243243 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 89643.243243 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6993500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6993500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13439500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13439500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13439500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13439500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036558 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036558 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051972 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051972 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99169.230769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99169.230769 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92019.736842 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92019.736842 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 45 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6699000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6699000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13118000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13118000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037243 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.037243 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.078075 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.078075 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051207 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051207 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95805.970149 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95805.970149 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91767.123288 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91767.123288 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.259615 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.523512 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1695 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.097122 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.259615 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063603 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063603 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 130.523512 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063732 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063732 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4330 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4330 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1641 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1641 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1641 # number of overall hits -system.cpu.icache.overall_hits::total 1641 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses -system.cpu.icache.overall_misses::total 385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30145000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30145000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30145000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30145000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30145000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30145000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190030 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.190030 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.190030 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.190030 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.190030 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.190030 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78298.701299 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78298.701299 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78298.701299 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78298.701299 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4432 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1695 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1695 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1695 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1695 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1695 # number of overall hits +system.cpu.icache.overall_hits::total 1695 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 382 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 382 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 382 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 382 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 382 # number of overall misses +system.cpu.icache.overall_misses::total 382 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30098500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30098500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30098500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30098500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30098500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30098500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2077 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2077 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2077 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2077 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2077 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2077 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183919 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183919 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183919 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183919 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183919 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183919 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78791.884817 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 78791.884817 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 78791.884817 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 78791.884817 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 78791.884817 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 78791.884817 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 104 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 104 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 104 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 104 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 104 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23205500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23205500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23205500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23205500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23205500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23205500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137216 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.137216 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.137216 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83473.021583 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83473.021583 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23308500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23308500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23308500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23308500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23308500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23308500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133847 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.133847 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.133847 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.525180 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.525180 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.525180 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.525180 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.525180 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.525180 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 211.895854 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 212.529421 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002392 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 417 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002398 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.292642 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603212 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003976 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002490 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006467 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012756 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3770 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3770 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.555666 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 81.973755 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003984 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002502 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006486 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012726 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3761 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3761 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 67 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 67 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 418 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.l2cache.overall_misses::total 418 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6879500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6879500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22776500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22776500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6348000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6348000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22776500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13227500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36004000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22776500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13227500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36004000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses +system.cpu.l2cache.overall_misses::total 417 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6589500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6589500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22879500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22879500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6317500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6317500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22879500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12907000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35786500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22879500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12907000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35786500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 67 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 67 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 419 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 419 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses @@ -851,52 +851,52 @@ system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997613 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997613 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90519.736842 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90519.736842 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82225.631769 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82225.631769 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97661.538462 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97661.538462 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86133.971292 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86133.971292 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90267.123288 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90267.123288 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82597.472924 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82597.472924 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94291.044776 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94291.044776 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82597.472924 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92192.857143 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85818.944844 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82597.472924 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92192.857143 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85818.944844 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 67 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 67 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 418 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6119500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6119500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20006500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20006500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5698000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5698000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20006500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11817500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31824000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20006500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11817500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31824000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5859500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5859500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20109500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20109500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5647500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5647500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20109500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11507000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31616500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20109500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11507000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31616500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses @@ -905,91 +905,91 @@ system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80519.736842 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80519.736842 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72225.631769 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72225.631769 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87661.538462 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87661.538462 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 419 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80267.123288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80267.123288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72597.472924 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72597.472924 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84291.044776 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84291.044776 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 343 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 76 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 76 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 67 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 838 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 419 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002387 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.048853 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 418 99.76% 99.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 419 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 342 # Transaction distribution -system.membus.trans_dist::ReadExReq 76 # Transaction distribution -system.membus.trans_dist::ReadExResp 76 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 342 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 344 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 344 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 418 # Request fanout histogram +system.membus.snoop_fanout::samples 417 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 418 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 418 # Request fanout histogram -system.membus.reqLayer0.occupancy 506000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2231250 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 417 # Request fanout histogram +system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2226500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 9.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index c59c92e77..87a90ab33 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000092 # Nu sim_ticks 91859 # Number of ticks simulated final_tick 91859 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 91408 # Simulator instruction rate (inst/s) -host_op_rate 165563 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1559913 # Simulator tick rate (ticks/s) -host_mem_usage 432272 # Number of bytes of host memory used +host_inst_rate 94122 # Simulator instruction rate (inst/s) +host_op_rate 170479 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1606243 # Simulator tick rate (ticks/s) +host_mem_usage 432368 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -388,13 +388,35 @@ system.ruby.miss_latency_hist_seqr::stdev 33.880423 system.ruby.miss_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1377 system.ruby.Directory.incomplete_times_seqr 1376 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 # Average number of cycles messages are stalled in this MB +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 # Average number of cycles messages are stalled in this MB system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096364 # Average number of messages in buffer +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 # Average number of messages in buffer +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 # Average number of cycles messages are stalled in this MB +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 # Average number of cycles messages are stalled in this MB system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 # Average number of messages in buffer +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 # Average number of cycles messages are stalled in this MB system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.network.routers0.percent_links_utilized 7.484297 system.ruby.network.routers0.msg_count.Control::2 1377 @@ -405,6 +427,12 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 # Average number of cycles messages are stalled in this MB system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.network.routers1.percent_links_utilized 7.484297 system.ruby.network.routers1.msg_count.Control::2 1377 @@ -415,6 +443,24 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 # Average number of cycles messages are stalled in this MB +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 # Average number of cycles messages are stalled in this MB +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 # Average number of messages in buffer +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 # Average number of cycles messages are stalled in this MB system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.network.routers2.percent_links_utilized 7.484297 system.ruby.network.routers2.msg_count.Control::2 1377 |