diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/quick/se/00.hello/ref | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/quick/se/00.hello/ref')
14 files changed, 1683 insertions, 1655 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 58b2620bf..54de45ea3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21900500 # Number of ticks simulated final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94413 # Simulator instruction rate (inst/s) -host_op_rate 94393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 324370159 # Simulator tick rate (ticks/s) -host_mem_usage 297000 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 101932 # Simulator instruction rate (inst/s) +host_op_rate 101910 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 350189482 # Simulator tick rate (ticks/s) +host_mem_usage 296592 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index e7401ee31..d82a69683 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32545500 # Number of ticks simulated -final_tick 32545500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000036 # Number of seconds simulated +sim_ticks 35667500 # Number of ticks simulated +final_tick 35667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 507828 # Simulator instruction rate (inst/s) -host_op_rate 507304 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2581337246 # Simulator tick rate (ticks/s) -host_mem_usage 294696 # Number of bytes of host memory used +host_inst_rate 607241 # Simulator instruction rate (inst/s) +host_op_rate 606492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3381446720 # Simulator tick rate (ticks/s) +host_mem_usage 294520 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546680801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330368254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877049054 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546680801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546680801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546680801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330368254 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877049054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 498829467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 301450901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 800280367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 498829467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498829467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 498829467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 301450901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 800280367 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 65091 # number of cpu cycles simulated +system.cpu.numCycles 71335 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 65091 # Number of busy cycles +system.cpu.num_busy_cycles 71335 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -122,17 +122,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.756988 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.427155 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.756988 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.427155 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025251 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025251 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses @@ -152,14 +152,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5890000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5890000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4526000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4526000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10416000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -176,14 +176,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5130000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3942000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3942000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9072000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9072000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9072000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9072000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4453000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4453000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -216,27 +216,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.992231 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.519931 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.992231 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.519931 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062266 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062266 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses system.cpu.icache.tags.data_accesses 13081 # Number of data accesses @@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15304500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15304500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15304500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15304500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15304500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15304500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17250500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17250500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17250500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54854.838710 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54854.838710 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54854.838710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54854.838710 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61829.749104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,39 +290,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15025500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15025500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15025500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15025500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15025500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15025500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53854.838710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53854.838710 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.470347 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 183.843350 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.998222 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.472125 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.517941 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.325409 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003892 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005610 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses @@ -344,18 +344,18 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4987500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4987500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4343500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4343500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5652500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5652500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9996000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26537500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9996000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26537500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) @@ -380,18 +380,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.121076 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,18 +412,18 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3102500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3102500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4037500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4037500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7140000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18955500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7140000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18955500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3613500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3613500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4702500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4702500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8316000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22077500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8316000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22077500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses @@ -436,18 +436,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -479,11 +479,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -504,8 +504,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.9 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index c4983f8bd..bedd68076 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000012 # Nu sim_ticks 12363500 # Number of ticks simulated final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79745 # Simulator instruction rate (inst/s) -host_op_rate 79707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 412680664 # Simulator tick rate (ticks/s) -host_mem_usage 295680 # Number of bytes of host memory used +host_inst_rate 83593 # Simulator instruction rate (inst/s) +host_op_rate 83552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 432562452 # Simulator tick rate (ticks/s) +host_mem_usage 295260 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 6bacfac4e..9e7b361e2 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16524500 # Number of ticks simulated -final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18239500 # Number of ticks simulated +final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 315037 # Simulator instruction rate (inst/s) -host_op_rate 314537 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2013954906 # Simulator tick rate (ticks/s) -host_mem_usage 293376 # Number of bytes of host memory used +host_inst_rate 407753 # Simulator instruction rate (inst/s) +host_op_rate 406852 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2874172707 # Simulator tick rate (ticks/s) +host_mem_usage 293212 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 631305032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 317589034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 948894066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 631305032 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 631305032 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 631305032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 317589034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 948894066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 571945503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 287727186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 859672688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 571945503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 571945503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 571945503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 287727186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 859672688 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 33049 # number of cpu cycles simulated +system.cpu.numCycles 36479 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 33049 # Number of busy cycles +system.cpu.num_busy_cycles 36479 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -122,17 +122,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.431392 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 47.277997 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.431392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011580 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 47.277997 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011542 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011542 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses @@ -152,14 +152,14 @@ system.cpu.dcache.demand_misses::cpu.data 82 # n system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1674000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1674000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 5084000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 5084000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 5084000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 5084000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -176,14 +176,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 82 system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1458000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4428000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4428000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1647000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1647000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5002000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5002000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5002000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5002000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -216,27 +216,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 80.038009 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 80.038009 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039081 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039081 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 79.677134 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.038905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.038905 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses system.cpu.icache.tags.data_accesses 5335 # Number of data accesses @@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8965500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8965500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8965500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8965500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8965500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10106500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10106500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10106500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10106500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10106500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10106500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses @@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55003.067485 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55003.067485 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55003.067485 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62003.067485 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62003.067485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62003.067485 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,39 +290,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8802500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 8802500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8802500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 8802500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8802500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 8802500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9943500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9943500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9943500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9943500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9943500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9943500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54003.067485 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54003.067485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61003.067485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61003.067485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 107.126637 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.141583 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.985054 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003269 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.770969 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.878617 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002434 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003255 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses @@ -338,18 +338,18 @@ system.cpu.l2cache.demand_misses::total 245 # nu system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8558000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 8558000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1606500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1606500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9699000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 9699000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9699000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4879000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14578000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9699000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4879000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14578000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses) @@ -374,18 +374,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52502.040816 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59502.040816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59502.040816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,18 +406,18 @@ system.cpu.l2cache.demand_mshr_misses::total 245 system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6928000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6928000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6928000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3485000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10413000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6928000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3485000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10413000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1336500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1336500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8069000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8069000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8069000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4059000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12128000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8069000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4059000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12128000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -430,18 +430,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -475,7 +475,7 @@ system.cpu.toL2Bus.snoop_fanout::total 245 # Re system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 218 # Transaction distribution @@ -498,8 +498,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 245 # Request fanout histogram system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1225500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.4 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index ffa31a0bc..084d8789f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000030 # Nu sim_ticks 29949500 # Number of ticks simulated final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110305 # Simulator instruction rate (inst/s) -host_op_rate 129095 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 716958322 # Simulator tick rate (ticks/s) -host_mem_usage 313816 # Number of bytes of host memory used +host_inst_rate 117235 # Simulator instruction rate (inst/s) +host_op_rate 137200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 761957462 # Simulator tick rate (ticks/s) +host_mem_usage 313960 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated @@ -567,6 +567,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 3 # number of writebacks +system.cpu.icache.writebacks::total 3 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses @@ -609,6 +611,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 2 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits @@ -643,6 +647,8 @@ system.cpu.l2cache.demand_miss_latency::total 31692000 system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) @@ -749,7 +755,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution @@ -757,22 +763,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30080 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 0d7cf1bb4..120cb7565 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17170000 # Number of ticks simulated final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50361 # Simulator instruction rate (inst/s) -host_op_rate 58973 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188251031 # Simulator tick rate (ticks/s) -host_mem_usage 313812 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 54905 # Simulator instruction rate (inst/s) +host_op_rate 64292 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 205230571 # Simulator tick rate (ticks/s) +host_mem_usage 313448 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -979,6 +979,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 86.400000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 93 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 93 # number of demand (read+write) MSHR hits @@ -1178,18 +1180,18 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.102041 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.303046 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 396 89.80% 89.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 45 10.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 221500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 8015f8322..985aedbbf 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17778000 # Number of ticks simulated -final_tick 17778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18741000 # Number of ticks simulated +final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58925 # Simulator instruction rate (inst/s) -host_op_rate 69000 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 228057572 # Simulator tick rate (ticks/s) -host_mem_usage 310616 # Number of bytes of host memory used +host_inst_rate 59386 # Simulator instruction rate (inst/s) +host_op_rate 69540 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 242288300 # Simulator tick rate (ticks/s) +host_mem_usage 309720 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 18432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 25984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18432 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 288 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975587805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 388795140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 97198785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1461581730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975587805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975587805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975587805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 388795140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 97198785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1461581730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407 # Number of read requests accepted +system.physmem.num_reads::total 441 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 983512086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 430286538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 92204258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1506002881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 983512086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 983512086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 983512086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 430286538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 92204258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1506002881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 442 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 442 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26048 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28288 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26048 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28288 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 88 # Per bank write bursts -system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::0 101 # Per bank write bursts +system.physmem.perBankRdBursts::1 48 # Per bank write bursts system.physmem.perBankRdBursts::2 19 # Per bank write bursts system.physmem.perBankRdBursts::3 44 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 32 # Per bank write bursts -system.physmem.perBankRdBursts::6 37 # Per bank write bursts +system.physmem.perBankRdBursts::4 19 # Per bank write bursts +system.physmem.perBankRdBursts::5 37 # Per bank write bursts +system.physmem.perBankRdBursts::6 46 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 7 # Per bank write bursts -system.physmem.perBankRdBursts::10 26 # Per bank write bursts +system.physmem.perBankRdBursts::9 8 # Per bank write bursts +system.physmem.perBankRdBursts::10 27 # Per bank write bursts system.physmem.perBankRdBursts::11 47 # Per bank write bursts system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 7 # Per bank write bursts +system.physmem.perBankRdBursts::13 8 # Per bank write bursts system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17764500 # Total gap between requests +system.physmem.totGap 18727500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407 # Read request sizes (log2) +system.physmem.readPktSize::6 442 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,11 +94,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see @@ -190,79 +190,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 419.796610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 279.431145 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.786751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8 13.56% 13.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 32.20% 45.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 15.25% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 5.08% 66.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.39% 69.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 5.08% 74.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3121500 # Total ticks spent queuing -system.physmem.totMemAccLat 10752750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7669.53 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 425.650794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 288.378165 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.476918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21 33.33% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5 7.94% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 3434000 # Total ticks spent queuing +system.physmem.totMemAccLat 11721500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2210000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7769.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26419.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1465.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26519.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1509.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1465.18 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1509.42 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.45 # Data bus utilization in percentage -system.physmem.busUtilRead 11.45 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.79 # Data bus utilization in percentage +system.physmem.busUtilRead 11.79 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 340 # Number of row buffer hits during reads +system.physmem.readRowHits 370 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43647.42 # Average gap between requests -system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined +system.physmem.avgGap 42369.91 # Average gap between requests +system.physmem.pageHitRate 83.71 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10769580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14349765 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.276555 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 315250 # Time in different power states +system.physmem_0.actBackEnergy 10786680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 37500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14457615 # Total energy per rank (pJ) +system.physmem_0.averagePower 913.160587 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15294250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10147140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 598500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12757005 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.747987 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 956000 # Time in different power states +system.physmem_1.actBackEnergy 9859005 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 851250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12737220 # Total energy per rank (pJ) +system.physmem_1.averagePower 804.498342 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2184750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14370250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13949750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2336 # Number of BP lookups -system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2341 # Number of BP lookups +system.cpu.branchPred.condPredicted 1389 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 837 # Number of BTB lookups -system.cpu.branchPred.BTBHits 442 # Number of BTB hits +system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups +system.cpu.branchPred.BTBHits 447 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.807646 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 289 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.341289 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,84 +380,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 35557 # number of cpu cycles simulated +system.cpu.numCycles 37483 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6181 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11260 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7643 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 6059 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11274 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2341 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8204 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3826 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 175 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15133 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.869491 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.207772 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 363 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3834 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 177 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.845843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.199579 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8934 59.04% 59.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2459 16.25% 75.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.44% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3219 21.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9385 60.16% 60.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2463 15.79% 75.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 526 3.37% 79.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3227 20.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15133 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065697 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.316675 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5932 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3662 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5040 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 15601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.062455 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.300776 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5749 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4322 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5029 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9865 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1623 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7001 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 962 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1967 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4096 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8887 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9880 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1586 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6811 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1118 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2339 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4089 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 875 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 417 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9238 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40311 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9765 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 772 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9259 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40331 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9781 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3744 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1809 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3765 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 29 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1800 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1272 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8352 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsAdded 8358 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3013 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7853 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15133 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.472345 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.858310 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3018 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7856 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 15601 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.458176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.848338 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10931 72.23% 72.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1952 12.90% 85.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1600 10.57% 95.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 604 3.99% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 46 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11391 73.01% 73.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1965 12.60% 85.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1598 10.24% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 601 3.85% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 46 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,149 +465,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15601 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 412 28.91% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 465 32.63% 61.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 548 38.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 413 28.70% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 475 33.01% 61.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 551 38.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4470 62.53% 62.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1081 15.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4480 62.67% 62.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1582 22.13% 84.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1078 15.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 7148 # Type of FU issued -system.cpu.iq.rate 0.201029 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1425 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199356 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11395 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6553 # Number of integer instruction queue wakeup accesses +system.cpu.iq.rate 0.190700 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1439 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.201315 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31476 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11405 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6562 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8545 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8559 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 782 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 773 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 334 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8405 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 385 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8410 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1809 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 1800 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1272 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6744 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 6751 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1398 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2427 # number of memory reference insts executed -system.cpu.iew.exec_branches 1272 # Number of branches executed -system.cpu.iew.exec_stores 1023 # Number of stores executed -system.cpu.iew.exec_rate 0.189667 # Inst execution rate -system.cpu.iew.wb_sent 6611 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6569 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2977 # num instructions producing a value -system.cpu.iew.wb_consumers 5378 # num instructions consuming a value +system.cpu.iew.exec_refs 2419 # number of memory reference insts executed +system.cpu.iew.exec_branches 1275 # Number of branches executed +system.cpu.iew.exec_stores 1021 # Number of stores executed +system.cpu.iew.exec_rate 0.180108 # Inst execution rate +system.cpu.iew.wb_sent 6621 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6578 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2993 # num instructions producing a value +system.cpu.iew.wb_consumers 5408 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.184746 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.553552 # average fanout of values written-back +system.cpu.iew.wb_rate 0.175493 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553439 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2574 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2586 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14591 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.368583 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.017117 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.357176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.003286 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11942 81.84% 81.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1388 9.51% 91.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 601 4.12% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 167 1.14% 98.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.53% 99.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 46 0.32% 99.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.23% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12412 82.43% 82.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1386 9.21% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 592 3.93% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 296 1.97% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 173 1.15% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.52% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 45 0.30% 99.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 32 0.21% 99.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15057 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,242 +654,246 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22343 # The number of ROB reads -system.cpu.rob.rob_writes 16451 # The number of ROB writes -system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20424 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22821 # The number of ROB reads +system.cpu.rob.rob_writes 16478 # The number of ROB writes +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21882 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.743249 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.743249 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129145 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129145 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6720 # number of integer regfile reads -system.cpu.int_regfile_writes 3747 # number of integer regfile writes +system.cpu.cpi 8.162674 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.162674 # CPI: Total CPI of All Threads +system.cpu.ipc 0.122509 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.122509 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6722 # number of integer regfile reads +system.cpu.int_regfile_writes 3755 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23965 # number of cc regfile reads -system.cpu.cc_regfile_writes 2898 # number of cc regfile writes -system.cpu.misc_regfile_reads 2607 # number of misc regfile reads +system.cpu.cc_regfile_reads 23977 # number of cc regfile reads +system.cpu.cc_regfile_writes 2903 # number of cc regfile writes +system.cpu.misc_regfile_reads 2611 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.271040 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.551975 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1908 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.342657 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.271040 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164592 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164592 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 84.551975 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.165141 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.165141 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4692 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4692 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1173 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1173 # number of ReadReq hits +system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4677 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4677 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1166 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1166 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits -system.cpu.dcache.overall_hits::total 1895 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1888 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1888 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1888 # number of overall hits +system.cpu.dcache.overall_hits::total 1888 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses -system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9210000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9210000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 125500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16927500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16927500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16927500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16927500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses +system.cpu.dcache.overall_misses::total 357 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10689500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10689500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7727500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7727500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18417000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18417000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18417000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18417000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2253 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2253 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2253 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2253 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124627 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124625 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.124625 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55149.700599 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55149.700599 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47283.519553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47283.519553 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.159020 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.159020 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.159020 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.159020 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64394.578313 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64394.578313 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40458.115183 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40458.115183 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51588.235294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51588.235294 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 846 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 46.055556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu.dcache.writebacks::total 1 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 213 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 103 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8293500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8293500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8293500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9436000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9436000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9436000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9436000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077327 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077327 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064143 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.064143 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67854.368932 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67854.368932 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59682.926829 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59682.926829 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 3470 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.722973 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.212207 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.266039 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.266039 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.647063 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.268842 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.268842 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7943 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7943 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3460 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3460 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3460 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3460 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3460 # number of overall hits -system.cpu.icache.overall_hits::total 3460 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # 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number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077406 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077406 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077406 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63476.327703 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63476.327703 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 43 # number of writebacks +system.cpu.icache.writebacks::total 43 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 297 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021240 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7941 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7941 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7643 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7643 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 33 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 468 # number of overall MSHR misses system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16642000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16642000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16642000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23570000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16642000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2133000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2133000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17760500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17760500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5946500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5946500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17760500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8079500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17760500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8079500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25195926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27465926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.918919 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.764706 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.973064 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.941043 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61183.823529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61183.823529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61384.615385 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61384.615385 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62026.315789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58868.985981 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 1.061224 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 30677.849057 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71100 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71100 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61455.017301 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61455.017301 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61942.708333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61942.708333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62265.060241 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58687.876068 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 21 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 21 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_snoops 409 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 102 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 623 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 64 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 546 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.133700 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.340641 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 913 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 452 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 893 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.549832 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.582857 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 473 86.63% 86.63% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 73 13.37% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 443 49.61% 49.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 409 45.80% 95.41% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41 4.59% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 546 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 442999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 215495 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 893 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 286500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 444499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 375 # Transaction distribution +system.membus.trans_dist::ReadResp 410 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 812 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25920 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 882 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 882 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 407 # Request fanout histogram +system.membus.snoop_fanout::samples 442 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 407 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 442 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 514944 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2135000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.0 # Layer utilization (%) +system.membus.snoop_fanout::total 442 # Request fanout histogram +system.membus.reqLayer0.occupancy 559944 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2320000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index d4b2570c8..26cb25dcb 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25848500 # Number of ticks simulated -final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 28298500 # Number of ticks simulated +final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 341128 # Simulator instruction rate (inst/s) -host_op_rate 397821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1927554064 # Simulator tick rate (ticks/s) -host_mem_usage 312280 # Number of bytes of host memory used +host_inst_rate 321731 # Simulator instruction rate (inst/s) +host_op_rate 375194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1990329160 # Simulator tick rate (ticks/s) +host_mem_usage 311896 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51697 # number of cpu cycles simulated +system.cpu.numCycles 56597 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4566 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles +system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1008 # Number of branches fetched @@ -208,17 +208,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -270,14 +270,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,27 +310,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses system.cpu.icache.tags.data_accesses 9453 # Number of data accesses @@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses @@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,45 +378,47 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses @@ -442,18 +444,18 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11818000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 11818000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4305000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4305000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) @@ -478,18 +480,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,18 +512,18 @@ system.cpu.l2cache.demand_mshr_misses::total 350 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9568000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9568000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3485000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3485000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9568000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5312500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14880500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9568000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5312500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14880500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses @@ -534,18 +536,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -565,23 +567,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -602,8 +604,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 350 # Request fanout histogram system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.8 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index c52a652eb..b3842d82b 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22451000 # Number of ticks simulated -final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 22454000 # Number of ticks simulated +final_tick 22454000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76638 # Simulator instruction rate (inst/s) -host_op_rate 76622 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 344943613 # Simulator tick rate (ticks/s) -host_mem_usage 294148 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 82798 # Simulator instruction rate (inst/s) +host_op_rate 82780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 372464129 # Simulator tick rate (ticks/s) +host_mem_usage 294232 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20992 # Nu system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 935014031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 401942007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1336956038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 935014031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 935014031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 935014031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 401942007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1336956038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 934889107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 401888305 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1336777412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 934889107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 934889107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 934889107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 401888305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1336777412 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22364000 # Total gap between requests +system.physmem.totGap 22367000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2345000 # To system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1336.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 1336.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1336.96 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1336.78 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 10.44 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 355 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47684.43 # Average gap between requests +system.physmem.avgGap 47690.83 # Average gap between requests system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) @@ -279,7 +279,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 44903 # number of cpu cycles simulated +system.cpu.numCycles 44909 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss @@ -308,8 +308,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.045231 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.274547 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.045225 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.274511 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2707 # Number of cycles decode is running @@ -436,7 +436,7 @@ system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 7937 # Type of FU issued -system.cpu.iq.rate 0.176759 # Inst issue rate +system.cpu.iq.rate 0.176735 # Inst issue rate system.cpu.iq.fu_busy_cnt 176 # FU busy when requested system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads @@ -480,13 +480,13 @@ system.cpu.iew.exec_nop 1483 # nu system.cpu.iew.exec_refs 3098 # number of memory reference insts executed system.cpu.iew.exec_branches 1353 # Number of branches executed system.cpu.iew.exec_stores 1053 # Number of stores executed -system.cpu.iew.exec_rate 0.170835 # Inst execution rate +system.cpu.iew.exec_rate 0.170812 # Inst execution rate system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit system.cpu.iew.wb_count 7279 # cumulative count of insts written-back system.cpu.iew.wb_producers 2832 # num instructions producing a value system.cpu.iew.wb_consumers 4198 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.162105 # insts written-back per cycle +system.cpu.iew.wb_rate 0.162083 # insts written-back per cycle system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit @@ -558,27 +558,27 @@ system.cpu.commit.bw_lim_events 116 # nu system.cpu.rob.rob_reads 23467 # The number of ROB reads system.cpu.rob.rob_writes 21056 # The number of ROB writes system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30642 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 30648 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4986 # Number of Instructions Simulated system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.005816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.005816 # CPI: Total CPI of All Threads -system.cpu.ipc 0.111039 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.111039 # IPC: Total IPC of All Threads +system.cpu.cpi 9.007020 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.007020 # CPI: Total CPI of All Threads +system.cpu.ipc 0.111025 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.111025 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 10418 # number of integer regfile reads system.cpu.int_regfile_writes 5064 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 158 # number of misc regfile reads system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.670819 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.676519 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.670819 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022136 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022136 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.676519 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022138 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022138 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id @@ -683,14 +683,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943 system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 156.398029 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 156.413207 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 156.398029 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.076366 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.076366 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 156.413207 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.076374 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.076374 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id @@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst 432 # n system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses system.cpu.icache.overall_misses::total 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32419500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32419500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32419500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32419500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32419500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32419500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32422500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32422500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32422500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32422500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32422500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32422500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses @@ -727,12 +727,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.218292 system.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75045.138889 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75045.138889 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75045.138889 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75045.138889 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75052.083333 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75052.083333 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75052.083333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75052.083333 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,6 +741,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 17 # number of writebacks +system.cpu.icache.writebacks::total 17 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits @@ -753,33 +755,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 331 system.cpu.icache.demand_mshr_misses::total 331 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 331 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 331 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25901500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25901500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25901500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25901500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25901500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25901500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25904500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25904500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25904500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25904500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25904500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25904500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167256 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.167256 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.167256 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78252.265861 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78252.265861 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78261.329305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78261.329305 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 215.838012 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 215.857139 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.321641 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.516370 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.337319 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.519820 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004832 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001755 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006587 # Average percentage of cache occupancy @@ -789,6 +791,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -809,16 +813,18 @@ system.cpu.l2cache.overall_misses::cpu.data 141 # system.cpu.l2cache.overall_misses::total 469 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25373500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25373500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25375000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25375000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7455000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 7455000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25373500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25375000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 11462500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25373500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 36837500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25375000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 11462500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36836000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36837500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 331 # number of ReadCleanReq accesses(hits+misses) @@ -845,16 +851,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77358.231707 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77358.231707 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77362.804878 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77362.804878 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78541.577825 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78544.776119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78541.577825 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78544.776119 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -877,16 +883,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 141 system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22093500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22093500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22095000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22095000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6545000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6545000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22093500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22095000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10052500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32146000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22093500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32147500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22095000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10052500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32147500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for ReadCleanReq accesses @@ -901,16 +907,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67358.231707 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67358.231707 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67362.804878 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67362.804878 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -919,7 +925,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution @@ -927,23 +933,23 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 91 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) @@ -967,7 +973,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 469 # Request fanout histogram -system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.1 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index d99d61508..d2f7b8e7a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30902500 # Number of ticks simulated -final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 33912500 # Number of ticks simulated +final_tick 33912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 459853 # Simulator instruction rate (inst/s) -host_op_rate 459290 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2521006690 # Simulator tick rate (ticks/s) -host_mem_usage 291832 # Number of bytes of host memory used +host_inst_rate 492168 # Simulator instruction rate (inst/s) +host_op_rate 491565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2961014581 # Simulator tick rate (ticks/s) +host_mem_usage 292188 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 430 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 552952451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 258547733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 811500184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552952451 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552952451 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552952451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 258547733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 811500184 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -49,7 +49,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 61805 # number of cpu cycles simulated +system.cpu.numCycles 67825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -68,7 +68,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61805 # Number of busy cycles +system.cpu.num_busy_cycles 67825 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -108,17 +108,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.152837 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.067027 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.152837 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021033 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021033 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.067027 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021012 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021012 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses @@ -138,14 +138,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) @@ -162,14 +162,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,14 +186,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4698000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4698000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7398000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7398000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7398000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7398000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -202,27 +202,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 129.096971 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 129.022312 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 129.096971 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063036 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063036 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 129.022312 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062999 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses system.cpu.icache.tags.data_accesses 11547 # Number of data accesses @@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 295 # n system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses system.cpu.icache.overall_misses::total 295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses @@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -270,48 +270,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 13 # number of writebacks +system.cpu.icache.writebacks::total 13 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15846500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15846500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15846500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15846500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15846500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15846500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53716.949153 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53716.949153 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.690355 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 183.581605 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.238740 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.451615 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005606 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.156658 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 53.424948 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003972 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005602 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -330,18 +334,20 @@ system.cpu.l2cache.demand_misses::total 430 # nu system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 430 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 15383000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4567500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4567500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses) @@ -366,18 +372,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995370 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.706485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,18 +404,18 @@ system.cpu.l2cache.demand_mshr_misses::total 430 system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2125000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2125000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12453000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12453000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3697500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3697500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12453000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5822500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18275500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12453000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5822500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18275500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses @@ -422,18 +428,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.706485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.706485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -442,7 +448,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution @@ -450,27 +456,27 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28480 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 432 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution @@ -491,8 +497,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 430 # Request fanout histogram system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.0 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2150000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 1b72b1558..685331601 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000020 # Nu sim_ticks 19923000 # Number of ticks simulated final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93968 # Simulator instruction rate (inst/s) -host_op_rate 93947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 323084408 # Simulator tick rate (ticks/s) -host_mem_usage 291680 # Number of bytes of host memory used +host_inst_rate 101947 # Simulator instruction rate (inst/s) +host_op_rate 101922 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 350504038 # Simulator tick rate (ticks/s) +host_mem_usage 292056 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index a369fae45..22edb2de4 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27803500 # Number of ticks simulated -final_tick 27803500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000031 # Number of seconds simulated +sim_ticks 30526500 # Number of ticks simulated +final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 506128 # Simulator instruction rate (inst/s) -host_op_rate 505504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2635153066 # Simulator tick rate (ticks/s) -host_mem_usage 292480 # Number of bytes of host memory used +host_inst_rate 511867 # Simulator instruction rate (inst/s) +host_op_rate 511179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2925956101 # Simulator tick rate (ticks/s) +host_mem_usage 292840 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 586976460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308450375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895426835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 586976460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 586976460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 586976460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308450375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895426835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 55607 # number of cpu cycles simulated +system.cpu.numCycles 61053 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 55606.998000 # Number of busy cycles +system.cpu.num_busy_cycles 61052.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -90,17 +90,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.111103 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.111103 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses @@ -120,14 +120,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2929000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2929000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7384000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7384000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7384000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7384000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3300000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5022000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5022000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8322000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8322000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8322000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8322000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -144,14 +144,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54240.740741 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54240.740741 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54696.296296 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54696.296296 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61111.111111 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61111.111111 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61644.444444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61644.444444 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7249000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7249000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3246000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3246000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4941000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4941000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8187000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8187000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8187000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8187000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -184,27 +184,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53240.740741 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53240.740741 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.031458 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.031458 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057144 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses system.cpu.icache.tags.data_accesses 10999 # Number of data accesses @@ -220,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14053500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14053500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14053500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14053500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14053500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14053500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15838500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15838500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15838500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15838500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15838500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15838500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -238,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54682.879377 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54682.879377 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54682.879377 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54682.879377 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61628.404669 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61628.404669 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61628.404669 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61628.404669 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -258,39 +258,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13796500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13796500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13796500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13796500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13796500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13796500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15581500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15581500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15581500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15581500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15581500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15581500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53682.879377 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53682.879377 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.152541 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.493414 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659127 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses @@ -316,18 +316,18 @@ system.cpu.l2cache.demand_misses::total 389 # nu system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 389 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13388000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13388000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4819500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4819500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15173000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 15173000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15173000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23146000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15173000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23146000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses) @@ -352,18 +352,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.992347 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.285347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.285347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,18 +384,18 @@ system.cpu.l2cache.demand_mshr_misses::total 389 system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10838000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10838000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10838000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16533000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10838000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16533000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4009500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4009500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12623000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12623000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12623000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19256000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12623000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19256000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses @@ -408,18 +408,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -451,9 +451,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 308 # Transaction distribution @@ -476,8 +476,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 389 # Request fanout histogram system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.0 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index b13c74560..73aebadd7 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000021 # Nu sim_ticks 20818000 # Number of ticks simulated final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48919 # Simulator instruction rate (inst/s) -host_op_rate 88616 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189245943 # Simulator tick rate (ticks/s) -host_mem_usage 313416 # Number of bytes of host memory used +host_inst_rate 50154 # Simulator instruction rate (inst/s) +host_op_rate 90851 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 194020392 # Simulator tick rate (ticks/s) +host_mem_usage 314048 # Number of bytes of host memory used host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index a52dc699f..c28a44ceb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28359500 # Number of ticks simulated -final_tick 28359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000031 # Number of seconds simulated +sim_ticks 30886500 # Number of ticks simulated +final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279983 # Simulator instruction rate (inst/s) -host_op_rate 506758 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1473373857 # Simulator tick rate (ticks/s) -host_mem_usage 311136 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 150745 # Simulator instruction rate (inst/s) +host_op_rate 272977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864611035 # Simulator tick rate (ticks/s) +host_mem_usage 310988 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 512279836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302403075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 814682910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512279836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512279836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512279836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302403075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 814682910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56719 # number of cpu cycles simulated +system.cpu.numCycles 61773 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56718.998000 # Number of busy cycles +system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -93,17 +93,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.792611 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.792611 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses @@ -123,14 +123,14 @@ system.cpu.dcache.demand_misses::cpu.data 134 # n system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) @@ -147,14 +147,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,14 +171,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 134 system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4266000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4266000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7236000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7236000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7236000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7236000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4819000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4819000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8174000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8174000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses @@ -187,27 +187,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.543720 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.543720 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses system.cpu.icache.tags.data_accesses 13956 # Number of data accesses @@ -223,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12499500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12499500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12499500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12499500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12499500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12499500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14088500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14088500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14088500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14088500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14088500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14088500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -241,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54822.368421 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54822.368421 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54822.368421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54822.368421 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61791.666667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61791.666667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61791.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -261,39 +261,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12271500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12271500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12271500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12271500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12271500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12271500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13860500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13860500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53822.368421 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53822.368421 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.010901 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.539859 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.471042 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses @@ -315,18 +315,18 @@ system.cpu.l2cache.demand_misses::total 361 # nu system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11918000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 11918000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4700500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4700500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13507000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13507000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13507000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13507000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21480000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) @@ -351,18 +351,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.385042 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.385042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,18 +383,18 @@ system.cpu.l2cache.demand_mshr_misses::total 361 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3357500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3357500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9648000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9648000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9648000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15343000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9648000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15343000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses @@ -407,18 +407,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -452,7 +452,7 @@ system.cpu.toL2Bus.snoop_fanout::total 362 # Re system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 282 # Transaction distribution @@ -477,8 +477,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 361 # Request fanout histogram system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.4 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- |