diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/quick/se/00.hello/ref | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/quick/se/00.hello/ref')
37 files changed, 3611 insertions, 2391 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 0bab63428..a216e15cb 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu sim_ticks 25552000 # Number of ticks simulated final_tick 25552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78801 # Simulator instruction rate (inst/s) -host_op_rate 78787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 314994021 # Simulator tick rate (ticks/s) -host_mem_usage 262608 # Number of bytes of host memory used +host_inst_rate 78387 # Simulator instruction rate (inst/s) +host_op_rate 78372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 313333088 # Simulator tick rate (ticks/s) +host_mem_usage 263656 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,27 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.629630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 196.201768 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.982069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16 29.63% 29.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 29.63% 59.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 12.96% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 7.41% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.85% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.85% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.70% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7 12.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54 # Bytes accessed per row activation -system.physmem.totQLat 2560250 # Total ticks spent queuing -system.physmem.totMemAccLat 12605250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 86 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.418605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 204.922237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.300576 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27 31.40% 31.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21 24.42% 55.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10 11.63% 67.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 9.30% 76.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 1.16% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.49% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 8.14% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.33% 91.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7 8.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86 # Bytes accessed per row activation +system.physmem.totQLat 3845750 # Total ticks spent queuing +system.physmem.totMemAccLat 12639500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.totBankLat 7700000 # Total ticks spent accessing banks -system.physmem.avgQLat 5458.96 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16417.91 # Average bank access latency per DRAM burst +system.physmem.avgQLat 8199.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26876.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26949.89 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1174.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1174.70 # Average system read bandwidth in MiByte/s @@ -223,7 +222,11 @@ system.physmem.readRowHitRate 80.60 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 54450.96 # Average gap between requests system.physmem.pageHitRate 80.60 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.memoryStateTime::IDLE 13500 # Time in different power states +system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 22839000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.membus.throughput 1172197871 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution @@ -237,7 +240,7 @@ system.membus.data_through_bus 29952 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4371250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4371000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 17.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1632 # Number of BP lookups @@ -304,9 +307,9 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11596 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11594 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 469 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 43730 # Number of cycles cpu's stages were not processed system.cpu.runCycles 7375 # Number of cycles cpu stages are processed. system.cpu.activity 14.431073 # Percentage of cycles cpu is active @@ -343,14 +346,14 @@ system.cpu.stage4.idleCycles 46641 # Nu system.cpu.stage4.runCycles 4464 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 8.734957 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.169993 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.073249 # Cycle average of tags in use system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.169993 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069419 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069419 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.073249 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069372 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id @@ -369,12 +372,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25349750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25349750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25349750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25349750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25349750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25349750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24875750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24875750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24875750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24875750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24875750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24875750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -387,12 +390,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71407.746479 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71407.746479 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71407.746479 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71407.746479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71407.746479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71407.746479 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70072.535211 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70072.535211 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70072.535211 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70072.535211 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -413,24 +416,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21532500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21532500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21532500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21532500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21532500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21532500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21058500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21058500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21058500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21058500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21058500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21058500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71299.668874 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71299.668874 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71299.668874 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71299.668874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71299.668874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71299.668874 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69730.132450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69730.132450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 1174702567 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution @@ -449,19 +452,19 @@ system.cpu.toL2Bus.reqLayer0.occupancy 235000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 508000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 274750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 198.925679 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 198.803908 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.205920 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.719759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004340 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001731 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006071 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.109548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.694360 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004337 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001730 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006067 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id @@ -485,17 +488,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6927250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28141250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4931500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4931500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21214000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11858750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33072750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21214000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11858750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33072750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20740000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7180750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27920750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5181250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5181250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12362000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33102000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20740000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12362000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33102000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -518,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70478.405316 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72918.421053 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71063.762626 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67554.794521 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67554.794521 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70478.405316 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70587.797619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70517.590618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70478.405316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70587.797619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70517.590618 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68903.654485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75586.842105 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70506.944444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70976.027397 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70976.027397 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70579.957356 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70579.957356 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17443000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5745750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23188750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4029500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4029500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17443000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9775250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27218250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17443000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9775250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27218250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5998750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22968250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16969500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10277000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27246500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16969500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10277000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27246500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -570,27 +573,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57950.166113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.578947 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58557.449495 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55198.630137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55198.630137 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57950.166113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58186.011905 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58034.648188 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57950.166113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58186.011905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58034.648188 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56377.076412 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63144.736842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58000.631313 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58606.164384 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58606.164384 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.450623 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.396801 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.450623 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025256 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025256 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.396801 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025243 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025243 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id @@ -613,14 +616,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7371250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7371250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21672250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21672250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29043500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29043500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29043500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29043500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7625750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7625750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22645250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22645250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30271000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30271000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30271000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30271000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -637,19 +640,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75992.268041 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75992.268041 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61920.714286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61920.714286 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64974.272931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64974.272931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64974.272931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64974.272931 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78615.979381 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78615.979381 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64700.714286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64700.714286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67720.357942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67720.357942 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.730769 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.307692 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -669,14 +672,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7028750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7028750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5009000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5009000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12037750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12037750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12037750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12037750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7282250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7282250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5258750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5258750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12541000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12541000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12541000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12541000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -685,14 +688,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73986.842105 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73986.842105 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68616.438356 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68616.438356 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71653.273810 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71653.273810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71653.273810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71653.273810 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76655.263158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76655.263158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72037.671233 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72037.671233 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 8bfd28333..33f9c5fe9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21078000 # Number of ticks simulated -final_tick 21078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21025000 # Number of ticks simulated +final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72140 # Simulator instruction rate (inst/s) -host_op_rate 72127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 238549554 # Simulator tick rate (ticks/s) -host_mem_usage 265696 # Number of bytes of host memory used +host_inst_rate 72274 # Simulator instruction rate (inst/s) +host_op_rate 72262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238397605 # Simulator tick rate (ticks/s) +host_mem_usage 265716 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 950374798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 528323370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1478698169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 950374798 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 950374798 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 950374798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 528323370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1478698169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 952770511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 529655172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1482425684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 952770511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 952770511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 952770511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 529655172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1482425684 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 488 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21045000 # Total gap between requests +system.physmem.totGap 20992000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.393443 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.167058 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.898610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21 34.43% 34.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 26.23% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 9.84% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 6.56% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.92% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.64% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 16.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation -system.physmem.totQLat 3243750 # Total ticks spent queuing -system.physmem.totMemAccLat 13328750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.218426 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.360278 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 24.05% 50.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.27% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation +system.physmem.totQLat 4394750 # Total ticks spent queuing +system.physmem.totMemAccLat 13544750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers -system.physmem.totBankLat 7645000 # Total ticks spent accessing banks -system.physmem.avgQLat 6647.03 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15665.98 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9005.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27313.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1481.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27755.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1481.73 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.58 # Data bus utilization in percentage -system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.61 # Data bus utilization in percentage +system.physmem.busUtilRead 11.61 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 394 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43125.00 # Average gap between requests +system.physmem.avgGap 43016.39 # Average gap between requests system.physmem.pageHitRate 80.74 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1478698169 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15304250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1482425684 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -234,10 +238,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 618500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 4556750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2894 # Number of BP lookups system.cpu.branchPred.condPredicted 1702 # Number of conditional branches predicted @@ -252,22 +256,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2078 # DTB read hits +system.cpu.dtb.read_hits 2077 # DTB read hits system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2125 # DTB read accesses +system.cpu.dtb.read_accesses 2124 # DTB read accesses system.cpu.dtb.write_hits 1062 # DTB write hits system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1093 # DTB write accesses -system.cpu.dtb.data_hits 3140 # DTB hits +system.cpu.dtb.data_hits 3139 # DTB hits system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3218 # DTB accesses -system.cpu.itb.fetch_hits 2388 # ITB hits +system.cpu.dtb.data_accesses 3217 # DTB accesses +system.cpu.itb.fetch_hits 2387 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2427 # ITB accesses +system.cpu.itb.fetch_accesses 2426 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -281,95 +285,95 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42157 # number of cpu cycles simulated +system.cpu.numCycles 42051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8510 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16605 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 8515 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16590 # Number of instructions fetch has processed system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2968 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1911 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1405 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 1438 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2388 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.109663 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.506678 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.106000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.503194 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11994 80.15% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.13% 82.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.56% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 214 1.43% 85.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 255 1.70% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 241 1.61% 88.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.76% 90.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 184 1.23% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1260 8.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12032 80.21% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.12% 82.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.56% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 214 1.43% 85.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.70% 87.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 241 1.61% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.76% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 183 1.22% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1259 8.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068648 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.393885 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9327 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1567 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2770 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.068821 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.394521 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9332 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1599 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2769 # Number of cycles decode is running system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1226 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 243 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15343 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15335 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1226 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9537 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2628 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 341 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14637 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 9542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 708 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2627 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 344 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14630 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10979 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18262 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18253 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 301 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10973 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18255 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18246 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6409 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6403 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 843 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 874 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2768 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12974 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12973 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10780 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10779 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6201 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3613 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.720396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.363744 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.718600 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361398 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10463 69.92% 69.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1623 10.85% 80.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1158 7.74% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 756 5.05% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 501 3.35% 96.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 1.80% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 146 0.98% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10485 69.90% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1646 10.97% 80.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1153 7.69% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 753 5.02% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 501 3.34% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 269 1.79% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15000 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available @@ -405,7 +409,7 @@ system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7243 67.19% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7243 67.20% 67.21% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued @@ -434,39 +438,39 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2399 22.25% 89.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2398 22.25% 89.49% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1133 10.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10780 # Type of FU issued -system.cpu.iq.rate 0.255711 # Inst issue rate +system.cpu.iq.FU_type_0::total 10779 # Type of FU issued +system.cpu.iq.rate 0.256332 # Inst issue rate system.cpu.iq.fu_busy_cnt 112 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010390 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36671 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19208 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.010391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36705 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19206 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 9602 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10879 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10878 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1585 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 127 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 132 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1226 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 247 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13092 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 13091 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2768 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall @@ -475,43 +479,43 @@ system.cpu.iew.memOrderViolationEvents 16 # Nu system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 504 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10072 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 10071 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3231 # number of memory reference insts executed +system.cpu.iew.exec_refs 3230 # number of memory reference insts executed system.cpu.iew.exec_branches 1589 # Number of branches executed system.cpu.iew.exec_stores 1095 # Number of stores executed -system.cpu.iew.exec_rate 0.238916 # Inst execution rate +system.cpu.iew.exec_rate 0.239495 # Inst execution rate system.cpu.iew.wb_sent 9755 # cumulative count of insts sent to commit system.cpu.iew.wb_count 9612 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5080 # num instructions producing a value -system.cpu.iew.wb_consumers 6838 # num instructions consuming a value +system.cpu.iew.wb_producers 5069 # num instructions producing a value +system.cpu.iew.wb_consumers 6811 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.228005 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.228580 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.744237 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6701 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6700 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13738 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465060 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.277866 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.463845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273398 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10960 79.78% 79.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1479 10.77% 90.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 519 3.78% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 236 1.72% 96.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 157 1.14% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 106 0.77% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 104 0.76% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 34 0.25% 98.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10981 79.72% 79.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1489 10.81% 90.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 532 3.86% 94.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 235 1.71% 96.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 155 1.13% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 100 0.73% 97.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.77% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.24% 98.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 143 1.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13738 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13774 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -522,26 +526,61 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 6389 # Class of committed instruction system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26334 # The number of ROB reads -system.cpu.rob.rob_writes 27415 # The number of ROB writes +system.cpu.rob.rob_reads 26369 # The number of ROB reads +system.cpu.rob.rob_writes 27413 # The number of ROB writes system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27193 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 27051 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 6.615976 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.615976 # CPI: Total CPI of All Threads -system.cpu.ipc 0.151149 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.151149 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12785 # number of integer regfile reads +system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12784 # number of integer regfile reads system.cpu.int_regfile_writes 7268 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1481734510 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -556,61 +595,61 @@ system.cpu.toL2Bus.data_through_bus 31232 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 278250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.411930 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1899 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 159.423717 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.047771 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.411930 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077838 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 159.423717 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077844 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5090 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5090 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1899 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1899 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1899 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1899 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1899 # number of overall hits -system.cpu.icache.overall_hits::total 1899 # number of overall hits +system.cpu.icache.tags.tag_accesses 5088 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5088 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits +system.cpu.icache.overall_hits::total 1898 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses system.cpu.icache.overall_misses::total 489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31431750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31431750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31431750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31431750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31431750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31431750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2388 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2388 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2388 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2388 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204774 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204774 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204774 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204774 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204774 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204774 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64277.607362 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64277.607362 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64277.607362 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64277.607362 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31330250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31330250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31330250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31330250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31330250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31330250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64070.040900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64070.040900 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64070.040900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64070.040900 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,34 +670,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22098000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22098000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22098000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22098000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22098000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22098000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131910 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131910 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131910 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70152.380952 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70152.380952 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22016000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22016000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22016000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22016000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22016000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22016000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69892.063492 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69892.063492 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 219.244506 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.258059 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.494883 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59.749622 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004867 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.507047 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.751013 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004868 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006691 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id @@ -684,17 +723,17 @@ system.cpu.l2cache.demand_misses::total 488 # nu system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7725500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29497500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5467500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5467500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13193000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34965000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21772000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13193000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34965000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21690000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29408000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21690000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13435750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35125750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21690000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13435750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35125750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) @@ -717,17 +756,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69337.579618 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76490.099010 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.313253 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74897.260274 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74897.260274 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71649.590164 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71649.590164 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69076.433121 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76415.841584 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70862.650602 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78325.342466 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78325.342466 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71978.995902 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71978.995902 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -747,17 +786,17 @@ system.cpu.l2cache.demand_mshr_misses::total 488 system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17823000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6485500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4573000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4573000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17823000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11058500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28881500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17823000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11058500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28881500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17737500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6477000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24214500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4818250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4818250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11295250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29032750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17737500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11295250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29032750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses @@ -769,41 +808,41 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56761.146497 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64212.871287 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58574.698795 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56488.853503 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64128.712871 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58348.192771 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66003.424658 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66003.424658 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.267771 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.231811 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2229 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.810345 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.267771 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026188 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026188 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 107.231811 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026180 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026180 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5694 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5694 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5692 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5692 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits -system.cpu.dcache.overall_hits::total 2230 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2229 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2229 # number of overall hits +system.cpu.dcache.overall_hits::total 2229 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -812,43 +851,43 @@ system.cpu.dcache.demand_misses::cpu.data 530 # n system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses system.cpu.dcache.overall_misses::total 530 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11467500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11467500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23223733 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23223733 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34691233 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34691233 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34691233 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34691233 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11460500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11460500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25449978 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25449978 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36910478 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36910478 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36910478 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36910478 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090237 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.090237 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090285 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.090285 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.192029 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.192029 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.192029 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.192029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67061.403509 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67061.403509 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64690.064067 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64690.064067 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65455.156604 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65455.156604 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1533 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.192099 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.192099 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.192099 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.192099 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67020.467836 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67020.467836 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70891.303621 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70891.303621 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69642.411321 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69642.411321 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1529 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.862069 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.970588 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -868,30 +907,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5462500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5462500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13377500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13377500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13377500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13377500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7907500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7907500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5712750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5712750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13620250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13620250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13620250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13620250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053854 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053854 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77598.039216 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77598.039216 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75868.055556 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75868.055556 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77524.509804 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77524.509804 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79343.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 53f3ae2a8..60119bd53 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3208000 # Number of ticks simulated final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105446 # Simulator instruction rate (inst/s) -host_op_rate 105415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52907298 # Simulator tick rate (ticks/s) -host_mem_usage 268408 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 172950 # Simulator instruction rate (inst/s) +host_op_rate 172880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 86758979 # Simulator tick rate (ticks/s) +host_mem_usage 253924 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 6417 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 913b33750..351b1338b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu sim_ticks 138616 # Number of ticks simulated final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14698 # Simulator instruction rate (inst/s) -host_op_rate 14697 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 318804 # Simulator tick rate (ticks/s) -host_mem_usage 174728 # Number of bytes of host memory used -host_seconds 0.43 # Real time elapsed on the host +host_inst_rate 36011 # Simulator instruction rate (inst/s) +host_op_rate 36008 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 781041 # Simulator tick rate (ticks/s) +host_mem_usage 161164 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -210,6 +210,41 @@ system.cpu.num_busy_cycles 138616 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.369871 system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index f70111f0d..a76851914 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000118 # Nu sim_ticks 117611 # Number of ticks simulated final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 21881 # Simulator instruction rate (inst/s) -host_op_rate 21879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 402676 # Simulator tick rate (ticks/s) -host_mem_usage 177980 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 31716 # Simulator instruction rate (inst/s) +host_op_rate 31714 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 583663 # Simulator tick rate (ticks/s) +host_mem_usage 164416 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,6 +200,41 @@ system.cpu.num_busy_cycles 117611 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.786874 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1109 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 253 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index e6916bab3..706264b43 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000114 # Nu sim_ticks 113627 # Number of ticks simulated final_tick 113627 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 28822 # Simulator instruction rate (inst/s) -host_op_rate 28819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 512426 # Simulator tick rate (ticks/s) -host_mem_usage 175880 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 50343 # Simulator instruction rate (inst/s) +host_op_rate 50337 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 894983 # Simulator tick rate (ticks/s) +host_mem_usage 161272 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -186,6 +186,41 @@ system.cpu.num_busy_cycles 113627 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.473611 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1178 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 66f09eeb4..29b31fb1d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000093 # Nu sim_ticks 93341 # Number of ticks simulated final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 31508 # Simulator instruction rate (inst/s) -host_op_rate 31505 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 460155 # Simulator tick rate (ticks/s) -host_mem_usage 175808 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 52665 # Simulator instruction rate (inst/s) +host_op_rate 52659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 769125 # Simulator tick rate (ticks/s) +host_mem_usage 161200 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -185,6 +185,41 @@ system.cpu.num_busy_cycles 93341 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.199848 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index d0515d3c9..17ffa2150 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000144 # Nu sim_ticks 143853 # Number of ticks simulated final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14935 # Simulator instruction rate (inst/s) -host_op_rate 14935 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 336198 # Simulator tick rate (ticks/s) -host_mem_usage 174340 # Number of bytes of host memory used -host_seconds 0.43 # Real time elapsed on the host +host_inst_rate 53676 # Simulator instruction rate (inst/s) +host_op_rate 53669 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1208067 # Simulator tick rate (ticks/s) +host_mem_usage 160752 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -160,6 +160,41 @@ system.cpu.num_busy_cycles 143853 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.011692 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 72bd7571c..e6ec389d1 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu sim_ticks 32544000 # Number of ticks simulated final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163681 # Simulator instruction rate (inst/s) -host_op_rate 163603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 832819326 # Simulator tick rate (ticks/s) -host_mem_usage 277116 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 550056 # Simulator instruction rate (inst/s) +host_op_rate 549394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2794675827 # Simulator tick rate (ticks/s) +host_mem_usage 262632 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 65088 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 88231a1ee..5be5fa9ed 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12006500 # Number of ticks simulated -final_tick 12006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11975500 # Number of ticks simulated +final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60243 # Simulator instruction rate (inst/s) -host_op_rate 60220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 302796832 # Simulator tick rate (ticks/s) -host_mem_usage 264400 # Number of bytes of host memory used +host_inst_rate 56599 # Simulator instruction rate (inst/s) +host_op_rate 56579 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 283759448 # Simulator tick rate (ticks/s) +host_mem_usage 265424 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1002123850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 453087911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1455211760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1002123850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1002123850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1002123850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 453087911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1455211760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1004717966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 454260782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1458978748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1004717966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1004717966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1004717966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 454260782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1458978748 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 273 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11917000 # Total gap between requests +system.physmem.totGap 11886000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,33 +186,33 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 24 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 464 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 290.487911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.347726 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4 16.67% 41.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 12.50% 54.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 4.17% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 8.33% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 8.33% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 25.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 24 # Bytes accessed per row activation -system.physmem.totQLat 1638000 # Total ticks spent queuing -system.physmem.totMemAccLat 7265500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 38 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.368421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.223359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 366.580725 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14 36.84% 36.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5 13.16% 50.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 10.53% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 5.26% 65.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 5.26% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 5.26% 76.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 5.26% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 2.63% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 15.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38 # Bytes accessed per row activation +system.physmem.totQLat 2067500 # Total ticks spent queuing +system.physmem.totMemAccLat 7186250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers -system.physmem.totBankLat 4262500 # Total ticks spent accessing banks -system.physmem.avgQLat 6000.00 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15613.55 # Average bank access latency per DRAM burst +system.physmem.avgQLat 7573.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26613.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1455.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26323.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1458.98 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1455.21 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1458.98 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.37 # Data bus utilization in percentage -system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.40 # Data bus utilization in percentage +system.physmem.busUtilRead 11.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,10 +220,14 @@ system.physmem.readRowHits 225 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43652.01 # Average gap between requests +system.physmem.avgGap 43538.46 # Average gap between requests system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.18 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1455211760 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem.memoryStateTime::REF 260000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 7796750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1458978748 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 249 # Transaction distribution system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution @@ -234,9 +238,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 344500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2552500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2556250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1176 # Number of BP lookups @@ -281,42 +285,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 24014 # number of cpu cycles simulated +system.cpu.numCycles 23952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 4342 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 531 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.907925 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.314691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.909929 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.316850 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6513 84.34% 84.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.69% 85.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 115 1.49% 86.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.23% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 176 2.28% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 76 0.98% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.83% 91.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.84% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 565 7.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6496 84.31% 84.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.69% 85.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 115 1.49% 86.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.23% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 2.28% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 76 0.99% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.83% 91.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.84% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.048971 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.291955 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5487 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 579 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 7705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.292710 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5480 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 569 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1153 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing @@ -325,9 +329,9 @@ system.cpu.decode.BranchMispred 81 # Nu system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5585 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 5578 # Number of cycles rename is idle system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1063 # Number of cycles rename is running system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 5900 # Number of instructions processed by rename @@ -354,23 +358,23 @@ system.cpu.iq.iqSquashedInstsIssued 54 # Nu system.cpu.iq.iqSquashedInstsExamined 2341 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 1389 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7722 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.523828 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.238657 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7705 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.524984 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.239779 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6098 78.97% 78.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 565 7.32% 86.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 401 5.19% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.41% 94.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 200 2.59% 97.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 120 1.55% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6081 78.92% 78.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 565 7.33% 86.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 401 5.20% 91.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 263 3.41% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 200 2.60% 97.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 120 1.56% 99.03% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7705 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available @@ -440,10 +444,10 @@ system.cpu.iq.FU_type_0::MemWrite 395 9.77% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 4045 # Type of FU issued -system.cpu.iq.rate 0.168443 # Inst issue rate +system.cpu.iq.rate 0.168879 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010878 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15897 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 15880 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 7311 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3652 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads @@ -484,26 +488,26 @@ system.cpu.iew.exec_nop 336 # nu system.cpu.iew.exec_refs 1130 # number of memory reference insts executed system.cpu.iew.exec_branches 644 # Number of branches executed system.cpu.iew.exec_stores 388 # Number of stores executed -system.cpu.iew.exec_rate 0.160531 # Inst execution rate +system.cpu.iew.exec_rate 0.160947 # Inst execution rate system.cpu.iew.wb_sent 3738 # cumulative count of insts sent to commit system.cpu.iew.wb_count 3658 # cumulative count of insts written-back system.cpu.iew.wb_producers 1710 # num instructions producing a value system.cpu.iew.wb_consumers 2211 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152328 # insts written-back per cycle +system.cpu.iew.wb_rate 0.152722 # insts written-back per cycle system.cpu.iew.wb_fanout 0.773406 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 2726 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7228 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.356392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.198445 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 7211 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.357232 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.199732 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6359 87.98% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204 2.82% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 308 4.26% 95.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 114 1.58% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6342 87.95% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204 2.83% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 308 4.27% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 114 1.58% 96.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 72 1.00% 97.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 51 0.71% 98.34% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 32 0.44% 98.78% # Number of insts commited each cycle @@ -512,7 +516,7 @@ system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7228 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7211 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -523,25 +527,60 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 189 7.34% 7.34% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1677 65.10% 72.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.04% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 2576 # Class of committed instruction system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12220 # The number of ROB reads +system.cpu.rob.rob_reads 12203 # The number of ROB reads system.cpu.rob.rob_writes 11111 # The number of ROB writes -system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16292 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16247 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 10.060327 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.060327 # CPI: Total CPI of All Threads -system.cpu.ipc 0.099400 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.099400 # IPC: Total IPC of All Threads +system.cpu.cpi 10.034353 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads +system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 4672 # number of integer regfile reads system.cpu.int_regfile_writes 2825 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1455211760 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1458978748 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -556,19 +595,19 @@ system.cpu.toL2Bus.data_through_bus 17472 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 315500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 316750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 133500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 93.163170 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 93.052511 # Cycle average of tags in use system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 93.163170 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.045490 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.045490 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 93.052511 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.045436 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.045436 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id @@ -587,12 +626,12 @@ system.cpu.icache.demand_misses::cpu.inst 250 # n system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17591499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17591499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17591499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17591499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17591499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17591499 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17506249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17506249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17506249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17506249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17506249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17506249 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses @@ -605,12 +644,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70365.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70365.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70365.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70365.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70365.996000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70024.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70024.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70024.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70024.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -631,36 +670,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 188 system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162249 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13162249 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13162249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13162249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13110499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13110499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13110499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13110499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13110499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13110499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70011.962766 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70011.962766 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70011.962766 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70011.962766 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69736.696809 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69736.696809 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 122.028433 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 121.888429 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.360563 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.667870 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002849 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003720 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 249 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -678,17 +717,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12973500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4680750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17654250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1693750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1693750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12973500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6374500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19348000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12973500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6374500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19348000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12921750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17574250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1688000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1688000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12921750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6340500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19262250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12921750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6340500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19262250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -711,17 +750,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69007.978723 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76733.606557 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70900.602410 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70572.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70572.916667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70871.794872 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69007.978723 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74994.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70871.794872 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68732.712766 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76270.491803 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70579.317269 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70333.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70333.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70557.692308 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70557.692308 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,17 +780,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10603500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3934250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14537750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1399750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1399750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10603500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5334000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15937500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10603500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5334000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15937500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14452750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1393500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1393500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5298500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5298500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15846250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -763,30 +802,30 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56401.595745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64495.901639 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58384.538153 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58322.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58322.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56401.595745 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62752.941176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58379.120879 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56105.053191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64016.393443 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58043.172691 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58062.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58062.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56105.053191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62335.294118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58044.871795 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.630537 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 45.583444 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 759 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.929412 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.630537 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011140 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011140 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.583444 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011129 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011129 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1995 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1995 # Number of data accesses @@ -806,14 +845,14 @@ system.cpu.dcache.demand_misses::cpu.data 196 # n system.cpu.dcache.demand_misses::total 196 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 196 # number of overall misses system.cpu.dcache.overall_misses::total 196 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7964000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7964000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5323250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5323250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13287250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13287250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13287250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13287250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7876750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7876750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5302250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5302250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13179000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13179000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13179000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13179000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -830,14 +869,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.205236 system.cpu.dcache.demand_miss_rate::total 0.205236 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.205236 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.205236 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69252.173913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69252.173913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65719.135802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65719.135802 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67792.091837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67792.091837 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67792.091837 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68493.478261 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68493.478261 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65459.876543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65459.876543 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67239.795918 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67239.795918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67239.795918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67239.795918 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -862,14 +901,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6461000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6461000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6427000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6427000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6427000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6427000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -878,14 +917,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089005 system.cpu.dcache.demand_mshr_miss_rate::total 0.089005 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.089005 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77733.606557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77733.606557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71635.416667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71635.416667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76011.764706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77270.491803 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77270.491803 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 2cd66ec8a..6080ce665 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59390 # Simulator instruction rate (inst/s) -host_op_rate 59366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29878318 # Simulator tick rate (ticks/s) -host_mem_usage 267100 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 741583 # Simulator instruction rate (inst/s) +host_op_rate 738395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 370291096 # Simulator tick rate (ticks/s) +host_mem_usage 253628 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 2596 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 944c5b9f4..d01144a54 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu sim_ticks 52548 # Number of ticks simulated final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 15623 # Simulator instruction rate (inst/s) -host_op_rate 15622 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 318507 # Simulator tick rate (ticks/s) -host_mem_usage 173288 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 36298 # Simulator instruction rate (inst/s) +host_op_rate 36291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 739863 # Simulator tick rate (ticks/s) +host_mem_usage 159844 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -209,6 +209,41 @@ system.cpu.num_busy_cycles 52548 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.426467 system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 431 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 215db9928..99c36fa52 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000045 # Nu sim_ticks 44968 # Number of ticks simulated final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18935 # Simulator instruction rate (inst/s) -host_op_rate 18932 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 330302 # Simulator tick rate (ticks/s) -host_mem_usage 175652 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 32543 # Simulator instruction rate (inst/s) +host_op_rate 32537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 567670 # Simulator tick rate (ticks/s) +host_mem_usage 162088 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,6 +200,41 @@ system.cpu.num_busy_cycles 44968 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.661804 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 423 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 87 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index eecde778c..c5b73657d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000043 # Nu sim_ticks 43073 # Number of ticks simulated final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22164 # Simulator instruction rate (inst/s) -host_op_rate 22160 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 370326 # Simulator tick rate (ticks/s) -host_mem_usage 173416 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 51660 # Simulator instruction rate (inst/s) +host_op_rate 51645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 862979 # Simulator tick rate (ticks/s) +host_mem_usage 159984 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -186,6 +186,41 @@ system.cpu.num_busy_cycles 43073 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.412904 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 293fb7685..3c031887e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000035 # Nu sim_ticks 35432 # Number of ticks simulated final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22204 # Simulator instruction rate (inst/s) -host_op_rate 22201 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 305145 # Simulator tick rate (ticks/s) -host_mem_usage 174496 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 51262 # Simulator instruction rate (inst/s) +host_op_rate 51245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 704386 # Simulator tick rate (ticks/s) +host_mem_usage 159904 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -184,6 +184,41 @@ system.cpu.num_busy_cycles 35432 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.200610 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 8be4f5dad..c9a4a26c5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu sim_ticks 52498 # Number of ticks simulated final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 10658 # Simulator instruction rate (inst/s) -host_op_rate 10657 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 217095 # Simulator tick rate (ticks/s) -host_mem_usage 172908 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 55191 # Simulator instruction rate (inst/s) +host_op_rate 55175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1123673 # Simulator tick rate (ticks/s) +host_mem_usage 158428 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -159,6 +159,41 @@ system.cpu.num_busy_cycles 52498 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.958322 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 4ab5ef724..3ccccfd43 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56666 # Simulator instruction rate (inst/s) -host_op_rate 56644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 363064230 # Simulator tick rate (ticks/s) -host_mem_usage 275808 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 366311 # Simulator instruction rate (inst/s) +host_op_rate 365532 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2339184598 # Simulator tick rate (ticks/s) +host_mem_usage 262348 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -101,6 +101,41 @@ system.cpu.num_busy_cycles 33048 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 18325fbc5..06219c218 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17056000 # Number of ticks simulated -final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16955000 # Number of ticks simulated +final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29277 # Simulator instruction rate (inst/s) -host_op_rate 36530 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108745688 # Simulator tick rate (ticks/s) -host_mem_usage 308972 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 43189 # Simulator instruction rate (inst/s) +host_op_rate 53887 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 159459409 # Simulator tick rate (ticks/s) +host_mem_usage 309444 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 392 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 392 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16998500 # Total gap between requests +system.physmem.totGap 16897500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation -system.physmem.totQLat 4223500 # Total ticks spent queuing -system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation +system.physmem.totQLat 3795000 # Total ticks spent queuing +system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5431250 # Total ticks spent accessing banks -system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.49 # Data bus utilization in percentage -system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.56 # Data bus utilization in percentage +system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 326 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43363.52 # Average gap between requests +system.physmem.avgGap 43105.87 # Average gap between requests system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1467166979 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15324750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1475906812 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution @@ -235,9 +239,9 @@ system.membus.tot_pkt_size::total 25024 # Cu system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.4 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2481 # Number of BP lookups system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted @@ -420,39 +424,39 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34113 # number of cpu cycles simulated +system.cpu.numCycles 33911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2426 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing @@ -461,9 +465,9 @@ system.cpu.decode.BranchMispred 159 # Nu system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2227 # Number of cycles rename is running system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename @@ -490,23 +494,23 @@ system.cpu.iq.iqSquashedInstsIssued 113 # Nu system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available @@ -576,10 +580,10 @@ system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.261513 # Inst issue rate +system.cpu.iq.rate 0.263071 # Inst issue rate system.cpu.iq.fu_busy_cnt 224 # FU busy when requested system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -612,43 +616,43 @@ system.cpu.iew.memOrderViolationEvents 21 # Nu system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3299 # number of memory reference insts executed +system.cpu.iew.exec_refs 3300 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.249846 # Inst execution rate +system.cpu.iew.exec_rate 0.251364 # Inst execution rate system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8068 # cumulative count of insts written-back system.cpu.iew.wb_producers 3883 # num instructions producing a value -system.cpu.iew.wb_consumers 7788 # num instructions consuming a value +system.cpu.iew.wb_consumers 7789 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -659,25 +663,60 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5729 # Class of committed instruction system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23225 # The number of ROB reads +system.cpu.rob.rob_reads 23248 # The number of ROB reads system.cpu.rob.rob_writes 23415 # The number of ROB writes -system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads -system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39214 # number of integer regfile reads system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 3239 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution @@ -692,22 +731,22 @@ system.cpu.toL2Bus.data_through_bus 27904 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses system.cpu.icache.tags.data_accesses 4184 # Number of data accesses @@ -723,12 +762,12 @@ system.cpu.icache.demand_misses::cpu.inst 363 # n system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.icache.overall_misses::total 363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses @@ -741,12 +780,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -767,39 +806,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 290 system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses @@ -823,17 +862,17 @@ system.cpu.l2cache.demand_misses::total 397 # nu system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 397 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) @@ -856,17 +895,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908467 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -892,17 +931,17 @@ system.cpu.l2cache.demand_mshr_misses::total 392 system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses @@ -914,39 +953,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits @@ -963,22 +1002,22 @@ system.cpu.dcache.demand_misses::cpu.data 496 # n system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses system.cpu.dcache.overall_misses::total 496 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses @@ -989,22 +1028,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -1031,14 +1070,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -1047,14 +1086,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index b2921c80f..41f6b039e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17056000 # Number of ticks simulated -final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16955000 # Number of ticks simulated +final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53685 # Simulator instruction rate (inst/s) -host_op_rate 66982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 199380443 # Simulator tick rate (ticks/s) -host_mem_usage 308976 # Number of bytes of host memory used +host_inst_rate 52426 # Simulator instruction rate (inst/s) +host_op_rate 65410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 193552438 # Simulator tick rate (ticks/s) +host_mem_usage 308400 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 392 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 392 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16998500 # Total gap between requests +system.physmem.totGap 16897500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation -system.physmem.totQLat 4223500 # Total ticks spent queuing -system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation +system.physmem.totQLat 3795000 # Total ticks spent queuing +system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5431250 # Total ticks spent accessing banks -system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.49 # Data bus utilization in percentage -system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.56 # Data bus utilization in percentage +system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 326 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43363.52 # Average gap between requests +system.physmem.avgGap 43105.87 # Average gap between requests system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1467166979 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15324750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1475906812 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution @@ -235,9 +239,9 @@ system.membus.tot_pkt_size::total 25024 # Cu system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.4 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2481 # Number of BP lookups system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted @@ -333,39 +337,39 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 34113 # number of cpu cycles simulated +system.cpu.numCycles 33911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2426 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing @@ -374,9 +378,9 @@ system.cpu.decode.BranchMispred 159 # Nu system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2227 # Number of cycles rename is running system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename @@ -403,23 +407,23 @@ system.cpu.iq.iqSquashedInstsIssued 113 # Nu system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available @@ -489,10 +493,10 @@ system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.261513 # Inst issue rate +system.cpu.iq.rate 0.263071 # Inst issue rate system.cpu.iq.fu_busy_cnt 224 # FU busy when requested system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -525,43 +529,43 @@ system.cpu.iew.memOrderViolationEvents 21 # Nu system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3299 # number of memory reference insts executed +system.cpu.iew.exec_refs 3300 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.249846 # Inst execution rate +system.cpu.iew.exec_rate 0.251364 # Inst execution rate system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8068 # cumulative count of insts written-back system.cpu.iew.wb_producers 3883 # num instructions producing a value -system.cpu.iew.wb_consumers 7788 # num instructions consuming a value +system.cpu.iew.wb_consumers 7789 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -572,25 +576,60 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5729 # Class of committed instruction system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23225 # The number of ROB reads +system.cpu.rob.rob_reads 23248 # The number of ROB reads system.cpu.rob.rob_writes 23415 # The number of ROB writes -system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads -system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39214 # number of integer regfile reads system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 3239 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution @@ -605,22 +644,22 @@ system.cpu.toL2Bus.data_through_bus 27904 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses system.cpu.icache.tags.data_accesses 4184 # Number of data accesses @@ -636,12 +675,12 @@ system.cpu.icache.demand_misses::cpu.inst 363 # n system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.icache.overall_misses::total 363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses @@ -654,12 +693,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -680,39 +719,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 290 system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses @@ -736,17 +775,17 @@ system.cpu.l2cache.demand_misses::total 397 # nu system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 397 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) @@ -769,17 +808,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908467 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -805,17 +844,17 @@ system.cpu.l2cache.demand_mshr_misses::total 392 system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses @@ -827,39 +866,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits @@ -876,22 +915,22 @@ system.cpu.dcache.demand_misses::cpu.data 496 # n system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses system.cpu.dcache.overall_misses::total 496 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses @@ -902,22 +941,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -944,14 +983,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -960,14 +999,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index e746c690f..fe7b25846 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97101 # Simulator instruction rate (inst/s) -host_op_rate 121123 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60664840 # Simulator tick rate (ticks/s) -host_mem_usage 311632 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 790734 # Simulator instruction rate (inst/s) +host_op_rate 984195 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 492029482 # Simulator tick rate (ticks/s) +host_mem_usage 297624 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -234,5 +234,40 @@ system.cpu.num_busy_cycles 5742 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction +system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5742 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 584aefada..2a0a91e3f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82560 # Simulator instruction rate (inst/s) -host_op_rate 102991 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51587489 # Simulator tick rate (ticks/s) -host_mem_usage 311624 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 770690 # Simulator instruction rate (inst/s) +host_op_rate 959471 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 479615706 # Simulator tick rate (ticks/s) +host_mem_usage 296608 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 5742 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction +system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5742 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 3e831f55e..ba11ac8e8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25969000 # Number of ticks simulated final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82063 # Simulator instruction rate (inst/s) -host_op_rate 101927 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 466514904 # Simulator tick rate (ticks/s) -host_mem_usage 320464 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 376681 # Simulator instruction rate (inst/s) +host_op_rate 467447 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2137718143 # Simulator tick rate (ticks/s) +host_mem_usage 306356 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -153,6 +153,41 @@ system.cpu.num_busy_cycles 51938 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction +system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction +system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5742 # Class of executed instruction system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 5e15549ca..12868f8fc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24975000 # Number of ticks simulated -final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24907000 # Number of ticks simulated +final_tick 24907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86020 # Simulator instruction rate (inst/s) -host_op_rate 86001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 369354314 # Simulator tick rate (ticks/s) -host_mem_usage 263428 # Number of bytes of host memory used +host_inst_rate 84163 # Simulator instruction rate (inst/s) +host_op_rate 84145 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 360406899 # Simulator tick rate (ticks/s) +host_mem_usage 264444 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 812332332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 353633634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1165965966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 812332332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 812332332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 812332332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 353633634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1165965966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 814550126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 354599109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1169149235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 814550126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 814550126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 814550126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 354599109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1169149235 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24894000 # Total gap between requests +system.physmem.totGap 24826000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,34 +186,32 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 267.093333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.339521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.296765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18 24.00% 24.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 29 38.67% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 12.00% 74.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 10.67% 85.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.33% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.33% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.33% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 6.67% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation -system.physmem.totQLat 3086250 # Total ticks spent queuing -system.physmem.totMemAccLat 13542500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 268.075472 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.680617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.800860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25 23.58% 23.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40 37.74% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14 13.21% 74.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 9.43% 83.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 6.60% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 2.83% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 4.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation +system.physmem.totQLat 4873000 # Total ticks spent queuing +system.physmem.totMemAccLat 13404250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8181250 # Total ticks spent accessing banks -system.physmem.avgQLat 6782.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 17980.77 # Average bank access latency per DRAM burst +system.physmem.avgQLat 10709.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29763.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29459.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1169.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1169.15 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.11 # Data bus utilization in percentage -system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.13 # Data bus utilization in percentage +system.physmem.busUtilRead 9.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -221,10 +219,14 @@ system.physmem.readRowHits 344 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54712.09 # Average gap between requests +system.physmem.avgGap 54562.64 # Average gap between requests system.physmem.pageHitRate 75.60 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1165965966 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 22841500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1169149235 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -237,8 +239,8 @@ system.membus.data_through_bus 29120 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4258000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4259500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1156 # Number of BP lookups system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted @@ -268,7 +270,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 49951 # number of cpu cycles simulated +system.cpu.numCycles 49815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). @@ -290,12 +292,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9487 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 463 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44568 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44432 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.776561 # Percentage of cycles cpu is active +system.cpu.activity 10.805982 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -307,36 +309,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 8.591503 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.568111 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.591503 # CPI: Total CPI of All Threads -system.cpu.ipc 0.116394 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.568111 # CPI: Total CPI of All Threads +system.cpu.ipc 0.116712 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.116394 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 46303 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.116712 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46167 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.303157 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 7.323095 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47002 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 47184 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 5.646894 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 47048 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2767 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.539429 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 5.554552 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48577 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47063 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.485195 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46927 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2888 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.781666 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 5.797451 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.508435 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.585033 # Cycle average of tags in use system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.508435 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073490 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073490 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.585033 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073528 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073528 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 306 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id @@ -355,12 +357,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25364500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25364500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25364500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25364500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25364500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25364500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25291750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25291750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25291750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25291750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25291750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25291750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -373,12 +375,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72470 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72470 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72470 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72470 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72470 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72470 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72262.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72262.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72262.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72262.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,26 +401,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23031000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23031000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23031000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23031000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23031000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23031000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22956750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22956750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22956750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22956750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22956750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22956750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72197.492163 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72197.492163 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72197.492163 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72197.492163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72197.492163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72197.492163 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71964.733542 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71964.733542 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1174288353 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -433,21 +435,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 538000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 538750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 225500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 226250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.255183 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 208.347330 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.186433 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.068750 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004644 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.267110 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.080220 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006358 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id @@ -471,17 +473,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22685500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6903000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29588500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3846500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3846500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22685500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10749500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33435000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22685500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10749500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33435000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22611250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6877000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29488250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3810250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3810250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22611250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10687250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33298500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22611250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10687250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33298500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -504,17 +506,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71563.091483 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79344.827586 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73238.861386 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75421.568627 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75421.568627 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71563.091483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77894.927536 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73483.516484 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71563.091483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77894.927536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73483.516484 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71328.864353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79045.977011 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72990.717822 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74710.784314 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74710.784314 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71328.864353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77443.840580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73183.516484 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71328.864353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77443.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73183.516484 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,17 +536,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18705000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5824500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24529500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18705000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9029000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27734000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18705000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9029000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27734000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18629250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5798500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24427750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18629250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8965250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27594500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18629250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8965250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27594500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -556,27 +558,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59006.309148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66948.275862 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60716.584158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59006.309148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65427.536232 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60953.846154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59006.309148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65427.536232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60953.846154 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58767.350158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66649.425287 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60464.727723 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62093.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62093.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58767.350158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64965.579710 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60647.252747 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58767.350158 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64965.579710 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60647.252747 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.278621 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.296415 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.278621 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022041 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.296415 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022045 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022045 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id @@ -599,14 +601,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses system.cpu.dcache.overall_misses::total 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7687000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7687000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21761250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21761250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29448250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29448250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29448250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29448250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7634750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7634750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21637250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21637250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29272000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29272000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29272000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29272000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -623,14 +625,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79247.422680 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79247.422680 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61646.600567 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61646.600567 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65440.555556 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65440.555556 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65440.555556 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65440.555556 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78708.762887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78708.762887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61295.325779 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61295.325779 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65048.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65048.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65048.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65048.888889 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -655,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6996500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6996500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3900500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3900500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10897000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10897000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10897000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10897000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6970500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6970500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3864250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3864250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10834750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10834750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10834750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10834750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -671,14 +673,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80419.540230 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80419.540230 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76480.392157 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76480.392157 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78963.768116 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78963.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78963.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78963.768116 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80120.689655 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80120.689655 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75769.607843 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75769.607843 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78512.681159 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78512.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78512.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78512.681159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index cbbbf2296..6e934b1b9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21918500 # Number of ticks simulated -final_tick 21918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21843500 # Number of ticks simulated +final_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56826 # Simulator instruction rate (inst/s) -host_op_rate 56817 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 241494238 # Simulator tick rate (ticks/s) -host_mem_usage 266500 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 63396 # Simulator instruction rate (inst/s) +host_op_rate 63384 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 268482897 # Simulator tick rate (ticks/s) +host_mem_usage 267540 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory system.physmem.num_reads::total 477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 978169127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 414626913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1392796040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 978169127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 978169127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 978169127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 414626913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1392796040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 477 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21839000 # Total gap between requests +system.physmem.totGap 21764000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,34 +186,33 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.540369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 250.647056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26 29.89% 29.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32 36.78% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 14.94% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.90% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.30% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.15% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.30% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 5.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation -system.physmem.totQLat 2715000 # Total ticks spent queuing -system.physmem.totMemAccLat 13776250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation +system.physmem.totQLat 4715500 # Total ticks spent queuing +system.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8676250 # Total ticks spent accessing banks -system.physmem.avgQLat 5691.82 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 18189.20 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28881.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1392.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1392.80 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.88 # Data bus utilization in percentage -system.physmem.busUtilRead 10.88 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.92 # Data bus utilization in percentage +system.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -221,10 +220,14 @@ system.physmem.readRowHits 357 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45784.07 # Average gap between requests +system.physmem.avgGap 45626.83 # Average gap between requests system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1392796040 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15319000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1397578227 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 426 # Transaction distribution system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -235,10 +238,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4473250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted @@ -268,7 +271,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43838 # number of cpu cycles simulated +system.cpu.numCycles 43688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss @@ -277,18 +280,18 @@ system.cpu.fetch.Branches 2174 # Nu system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1408 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11292 77.85% 77.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1317 9.08% 86.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 104 0.72% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 131 0.90% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total) @@ -297,11 +300,11 @@ system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049592 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.300721 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1660 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3025 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing @@ -311,8 +314,8 @@ system.cpu.decode.DecodedInsts 12292 # Nu system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst +system.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2898 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename @@ -339,14 +342,14 @@ system.cpu.iq.iqSquashedInstsIssued 39 # Nu system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.571734 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.240341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10922 75.30% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1422 9.80% 85.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 891 6.14% 91.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 3.81% 95.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle @@ -355,7 +358,7 @@ system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available @@ -425,10 +428,10 @@ system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8293 # Type of FU issued -system.cpu.iq.rate 0.189174 # Inst issue rate +system.cpu.iq.rate 0.189823 # Inst issue rate system.cpu.iq.fu_busy_cnt 160 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31286 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads @@ -469,23 +472,23 @@ system.cpu.iew.exec_nop 1512 # nu system.cpu.iew.exec_refs 3186 # number of memory reference insts executed system.cpu.iew.exec_branches 1344 # Number of branches executed system.cpu.iew.exec_stores 1079 # Number of stores executed -system.cpu.iew.exec_rate 0.180483 # Inst execution rate +system.cpu.iew.exec_rate 0.181102 # Inst execution rate system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit system.cpu.iew.wb_count 7455 # cumulative count of insts written-back system.cpu.iew.wb_producers 2921 # num instructions producing a value system.cpu.iew.wb_consumers 4197 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.170058 # insts written-back per cycle +system.cpu.iew.wb_rate 0.170642 # insts written-back per cycle system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13637 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.426267 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.206560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11235 82.39% 82.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle @@ -497,7 +500,7 @@ system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -508,25 +511,60 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5813 # Class of committed instruction system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24245 # The number of ROB reads +system.cpu.rob.rob_reads 24239 # The number of ROB reads system.cpu.rob.rob_writes 22333 # The number of ROB writes -system.cpu.timesIdled 286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 8.502327 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.502327 # CPI: Total CPI of All Threads -system.cpu.ipc 0.117615 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.117615 # IPC: Total IPC of All Threads +system.cpu.cpi 8.473235 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118019 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 10743 # number of integer regfile reads system.cpu.int_regfile_writes 5234 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1401555763 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -541,19 +579,19 @@ system.cpu.toL2Bus.data_through_bus 30720 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 161.390328 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.390328 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078804 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078804 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id @@ -572,12 +610,12 @@ system.cpu.icache.demand_misses::cpu.inst 451 # n system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses system.cpu.icache.overall_misses::total 451 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31256750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31256750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31256750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31256750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31256750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31256750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses @@ -590,12 +628,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69305.432373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69305.432373 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -616,36 +654,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 338 system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24262750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24262750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24262750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24262750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24262750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24262750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.496759 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.678282 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.818477 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id @@ -669,17 +707,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23894750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7065750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30960500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3800750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3800750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23894750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34761250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23894750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34761250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) @@ -702,17 +740,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71327.611940 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77645.604396 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72677.230047 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74524.509804 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74524.509804 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72874.737945 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72874.737945 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -732,17 +770,17 @@ system.cpu.l2cache.demand_mshr_misses::total 477 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19660250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5948250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25608500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3170750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3170750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19660250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9119000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28779250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19660250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9119000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28779250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19551000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5938500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25489500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19551000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9082750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28633750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19551000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9082750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28633750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses @@ -754,27 +792,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.623425 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.623425 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022369 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.603992 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022364 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022364 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id @@ -797,14 +835,14 @@ system.cpu.dcache.demand_misses::cpu.data 510 # n system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10261250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22413999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22413999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32675249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32675249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32675249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32675249 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10242750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22302249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22302249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32544999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32544999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32544999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32544999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -821,19 +859,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69332.770270 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69332.770270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61917.124309 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61917.124309 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64069.115686 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64069.115686 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63813.723529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63813.723529 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -853,14 +891,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7160250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7160250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3852749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3852749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11012999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11012999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11012999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11012999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7151000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7151000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -869,14 +907,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index b2f335f88..c5418ef55 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2907000 # Number of ticks simulated final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99853 # Simulator instruction rate (inst/s) -host_op_rate 99820 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49894332 # Simulator tick rate (ticks/s) -host_mem_usage 269208 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 1298058 # Simulator instruction rate (inst/s) +host_op_rate 1293725 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 644853594 # Simulator tick rate (ticks/s) +host_mem_usage 255756 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -81,5 +81,40 @@ system.cpu.num_busy_cycles 5815 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 915 # Number of branches fetched +system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction +system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction +system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction +system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5815 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 24111f1bf..88e0b5c68 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000125 # Nu sim_ticks 125334 # Number of ticks simulated final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32356 # Simulator instruction rate (inst/s) -host_op_rate 32352 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 697352 # Simulator tick rate (ticks/s) -host_mem_usage 176168 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 56489 # Simulator instruction rate (inst/s) +host_op_rate 56481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1217426 # Simulator tick rate (ticks/s) +host_mem_usage 162604 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -146,6 +146,41 @@ system.cpu.num_busy_cycles 125334 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 915 # Number of branches fetched +system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction +system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction +system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction +system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5815 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.954490 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1493 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1489 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index d941cff49..ee2cc6627 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119247 # Simulator instruction rate (inst/s) -host_op_rate 119199 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 648290000 # Simulator tick rate (ticks/s) -host_mem_usage 277916 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 474922 # Simulator instruction rate (inst/s) +host_op_rate 474341 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2577866515 # Simulator tick rate (ticks/s) +host_mem_usage 263440 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -87,6 +87,41 @@ system.cpu.num_busy_cycles 63266 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 915 # Number of branches fetched +system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction +system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction +system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction +system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5815 # Class of executed instruction system.cpu.icache.tags.replacements 13 # number of replacements system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index d62c7aac6..810e47329 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19079500 # Number of ticks simulated -final_tick 19079500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19030500 # Number of ticks simulated +final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82615 # Simulator instruction rate (inst/s) -host_op_rate 82599 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272039638 # Simulator tick rate (ticks/s) +host_inst_rate 79159 # Simulator instruction rate (inst/s) +host_op_rate 79144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 259986612 # Simulator tick rate (ticks/s) host_mem_usage 262500 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1157263031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 338792945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1496055976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1157263031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1157263031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1157263031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 338792945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1496055976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1160242768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 339665274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1499908042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1160242768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1160242768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1160242768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 339665274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1499908042 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 446 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18951000 # Total gap between requests +system.physmem.totGap 18902000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -186,45 +186,47 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.586207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.841802 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 367.136049 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 17 29.31% 29.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14 24.14% 53.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 10.34% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 5.17% 68.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.90% 75.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.45% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.72% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 18.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58 # Bytes accessed per row activation -system.physmem.totQLat 2851500 # Total ticks spent queuing -system.physmem.totMemAccLat 11984000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 198.974683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 351.274465 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28 36.36% 36.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 22.08% 58.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation +system.physmem.totQLat 3599250 # Total ticks spent queuing +system.physmem.totMemAccLat 11961750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6902500 # Total ticks spent accessing banks -system.physmem.avgQLat 6393.50 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15476.46 # Average bank access latency per DRAM burst +system.physmem.avgQLat 8070.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26869.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1496.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26820.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1496.06 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.69 # Data bus utilization in percentage -system.physmem.busUtilRead 11.69 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.72 # Data bus utilization in percentage +system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42491.03 # Average gap between requests +system.physmem.avgGap 42381.17 # Average gap between requests system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1496055976 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1499908042 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -235,10 +237,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 567500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 565500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4177500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2235 # Number of BP lookups system.cpu.branchPred.condPredicted 1802 # Number of conditional branches predicted @@ -268,55 +270,55 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 38160 # number of cpu cycles simulated +system.cpu.numCycles 38062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13154 # Number of instructions fetch has processed system.cpu.fetch.Branches 2235 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2260 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 1309 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1810 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.115975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.532873 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 11872 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.107985 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.525542 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9527 80.83% 80.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 176 1.49% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.49% 83.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.20% 85.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.93% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.12% 88.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.18% 90.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.93% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1040 8.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9612 80.96% 80.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 176 1.48% 82.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.48% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.20% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.91% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 132 1.11% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.16% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.058569 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.344706 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7519 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1384 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2094 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 11872 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.058720 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.345594 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7525 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1463 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2089 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 86 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 340 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 11724 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7704 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 677 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 7710 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 717 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 445 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1984 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 268 # Number of cycles rename is unblocking +system.cpu.rename.RunCycles 1980 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 311 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 11305 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 230 # Number of times rename has blocked due to LSQ full +system.cpu.rename.LSQFullEvents 264 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 18187 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 18161 # Number of integer rename lookups @@ -325,7 +327,7 @@ system.cpu.rename.CommittedMaps 4998 # Nu system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 582 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 615 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. @@ -337,23 +339,23 @@ system.cpu.iq.iqSquashedInstsIssued 241 # Nu system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11787 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.755154 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.486388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11872 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.749747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.477871 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8427 71.49% 71.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 6.71% 87.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 500 4.24% 91.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 455 3.86% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8485 71.47% 71.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1128 9.50% 80.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 793 6.68% 87.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 504 4.25% 91.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.84% 95.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 296 2.49% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 132 1.11% 99.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11787 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11872 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available @@ -423,10 +425,10 @@ system.cpu.iq.FU_type_0::MemWrite 1627 18.28% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8901 # Type of FU issued -system.cpu.iq.rate 0.233255 # Inst issue rate +system.cpu.iq.rate 0.233855 # Inst issue rate system.cpu.iq.fu_busy_cnt 173 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019436 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29941 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 30026 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14573 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8128 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads @@ -467,35 +469,35 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3201 # number of memory reference insts executed system.cpu.iew.exec_branches 1350 # Number of branches executed system.cpu.iew.exec_stores 1523 # Number of stores executed -system.cpu.iew.exec_rate 0.222746 # Inst execution rate +system.cpu.iew.exec_rate 0.223320 # Inst execution rate system.cpu.iew.wb_sent 8270 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8155 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4217 # num instructions producing a value -system.cpu.iew.wb_consumers 6678 # num instructions consuming a value +system.cpu.iew.wb_producers 4187 # num instructions producing a value +system.cpu.iew.wb_consumers 6623 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.213705 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631476 # average fanout of values written-back +system.cpu.iew.wb_rate 0.214256 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.632191 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11078 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.522838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.323591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11163 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.518857 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312790 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8698 78.52% 78.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1008 9.10% 87.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 609 5.50% 93.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 270 2.44% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8756 78.44% 78.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1031 9.24% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 625 5.60% 93.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.36% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 174 1.56% 97.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 104 0.93% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.58% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.39% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11078 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11163 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -506,24 +508,59 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5792 # Class of committed instruction system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21343 # The number of ROB reads +system.cpu.rob.rob_reads 21428 # The number of ROB reads system.cpu.rob.rob_writes 21442 # The number of ROB writes -system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26190 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 6.588398 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.588398 # CPI: Total CPI of All Threads -system.cpu.ipc 0.151782 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.151782 # IPC: Total IPC of All Threads +system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads +system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 13470 # number of integer regfile reads system.cpu.int_regfile_writes 7047 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1519536675 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -538,19 +575,19 @@ system.cpu.toL2Bus.data_through_bus 28992 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 585250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.852168 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 168.931685 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1369 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.900285 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.852168 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082447 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082447 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 168.931685 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082486 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id @@ -569,12 +606,12 @@ system.cpu.icache.demand_misses::cpu.inst 441 # n system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses system.cpu.icache.overall_misses::total 441 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30135000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30135000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30135000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30135000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30135000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30135000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30033500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30033500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30033500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30033500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30033500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30033500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1810 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1810 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1810 # number of demand (read+write) accesses @@ -587,12 +624,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.243646 system.cpu.icache.demand_miss_rate::total 0.243646 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.243646 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.243646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68333.333333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68333.333333 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68333.333333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68333.333333 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68103.174603 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68103.174603 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68103.174603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68103.174603 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -613,36 +650,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351 system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24444750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24444750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24444750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24444750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24444750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24444750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24362250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24362250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24362250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24362250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24362250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24362250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193923 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69643.162393 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69643.162393 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69408.119658 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69408.119658 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.197303 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.280245 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.717049 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.480255 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.794904 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.485341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005121 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006079 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006082 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id @@ -669,17 +706,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24033250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28107750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3621750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3621750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24033250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7696250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31729500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24033250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7696250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31729500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4072250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28023000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3614250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3614250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7686500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31637250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7686500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31637250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -702,17 +739,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69661.594203 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70445.488722 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77058.510638 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77058.510638 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71142.376682 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71142.376682 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69422.463768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75412.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70233.082707 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76898.936170 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76898.936170 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70935.538117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70935.538117 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -732,17 +769,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19691750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23102250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3044750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3044750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19691750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6455250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26147000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19691750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6455250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26147000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19603250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3407750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3033250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3033250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19603250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6441000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26044250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19603250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6441000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26044250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -754,25 +791,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57077.536232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.375940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56821.014493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63106.481481 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57671.679198 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64537.234043 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64537.234043 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.689105 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 63.690367 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.689105 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 63.690367 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.015549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.015549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id @@ -797,14 +834,14 @@ system.cpu.dcache.demand_misses::cpu.data 435 # n system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7364750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7364750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20363246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20363246 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27727996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27727996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27727996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27727996 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7366750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7366750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20319996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20319996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27686746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27686746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27686746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27686746 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -821,19 +858,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70814.903846 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70814.903846 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61520.380665 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61520.380665 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63742.519540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63742.519540 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70834.134615 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70834.134615 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61389.716012 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61389.716012 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63647.691954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63647.691954 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -853,14 +890,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3671748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3671748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7811748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7811748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7811748 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7811748 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4137750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4137750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3664248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3664248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7801998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7801998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7801998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7801998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -869,14 +906,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78122.297872 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78122.297872 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75231.818182 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75231.818182 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77962.723404 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77962.723404 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 96c448d8d..bcfd2d5d0 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139089 # Simulator instruction rate (inst/s) -host_op_rate 138996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69453756 # Simulator tick rate (ticks/s) -host_mem_usage 265200 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 1148266 # Simulator instruction rate (inst/s) +host_op_rate 1144862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 570752858 # Simulator tick rate (ticks/s) +host_mem_usage 250716 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -81,5 +81,40 @@ system.cpu.num_busy_cycles 5793 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1037 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3784 65.32% 65.32% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 65.32% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 65.32% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 65.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.35% # Class of executed instruction +system.cpu.op_class::MemRead 961 16.59% 81.94% # Class of executed instruction +system.cpu.op_class::MemWrite 1046 18.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5793 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index ca26bca81..90109d140 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20970500 # Number of ticks simulated -final_tick 20970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20918500 # Number of ticks simulated +final_tick 20918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71497 # Simulator instruction rate (inst/s) -host_op_rate 71482 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 281347268 # Simulator tick rate (ticks/s) -host_mem_usage 269780 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 69876 # Simulator instruction rate (inst/s) +host_op_rate 69862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 274294219 # Simulator tick rate (ticks/s) +host_mem_usage 270808 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 882000906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 408955437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1290956343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 882000906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 882000906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 882000906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 408955437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1290956343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 884193417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 409972034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1294165452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 884193417 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 884193417 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 884193417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 409972034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1294165452 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20901000 # Total gap between requests +system.physmem.totGap 20849000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,33 +186,31 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 337.333333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.579222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 300.401245 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 27.08% 27.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9 18.75% 45.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 12.50% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 14.58% 72.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 12.50% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 4.17% 89.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 10.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48 # Bytes accessed per row activation -system.physmem.totQLat 3113750 # Total ticks spent queuing -system.physmem.totMemAccLat 11732500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 74 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.459459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 226.188766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 265.234411 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 17 22.97% 22.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 21.62% 44.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 14.86% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 13 17.57% 77.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 10.81% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 5.41% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 6.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74 # Bytes accessed per row activation +system.physmem.totQLat 3773250 # Total ticks spent queuing +system.physmem.totMemAccLat 11704500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6503750 # Total ticks spent accessing banks -system.physmem.avgQLat 7361.11 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15375.30 # Average bank access latency per DRAM burst +system.physmem.avgQLat 8920.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27736.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1290.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27670.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1294.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1290.96 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1294.17 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.09 # Data bus utilization in percentage -system.physmem.busUtilRead 10.09 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.11 # Data bus utilization in percentage +system.physmem.busUtilRead 10.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,10 +218,14 @@ system.physmem.readRowHits 339 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49411.35 # Average gap between requests +system.physmem.avgGap 49288.42 # Average gap between requests system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1290956343 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 13500 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15312750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1294165452 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution @@ -236,8 +238,8 @@ system.membus.data_through_bus 27072 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3929500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted @@ -249,7 +251,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41942 # number of cpu cycles simulated +system.cpu.numCycles 41838 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -271,12 +273,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9659 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 424 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35694 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 422 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35590 # Number of cycles cpu's stages were not processed system.cpu.runCycles 6248 # Number of cycles cpu stages are processed. -system.cpu.activity 14.896762 # Percentage of cycles cpu is active +system.cpu.activity 14.933792 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -288,36 +290,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.873475 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.853952 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.873475 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127009 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.853952 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127324 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127009 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37302 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127324 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37198 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.062896 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38748 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.090396 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38644 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.615278 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38908 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.634208 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38804 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.233799 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40966 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.251781 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40862 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 976 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.327023 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38785 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.332807 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38681 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.527061 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.545772 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.644710 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.676310 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.644710 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069651 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069651 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.676310 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069666 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069666 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id @@ -336,12 +338,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25482750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25482750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25482750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25482750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25482750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25482750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25425250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25425250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25425250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25425250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25425250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -354,12 +356,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69625 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69625 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69625 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69625 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69625 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69625 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69467.896175 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69467.896175 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69467.896175 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69467.896175 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69467.896175 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69467.896175 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,26 +382,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20711750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20711750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20711750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20711750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20711750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20711750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20653250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20653250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20653250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20653250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20653250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20653250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71174.398625 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71174.398625 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71174.398625 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71174.398625 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71174.398625 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71174.398625 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70973.367698 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70973.367698 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70973.367698 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70973.367698 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70973.367698 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70973.367698 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1300112062 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1303343930 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -414,24 +416,24 @@ system.cpu.toL2Bus.data_through_bus 27264 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 486250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 216250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 217000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 169.087834 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 169.122448 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.075458 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.012376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004336 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.106217 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.016231 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004337 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005160 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005161 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010437 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3831 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3831 # Number of data accesses @@ -455,17 +457,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20393250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4031000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24424250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6031750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6031750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20393250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10062750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30456000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20393250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10062750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30456000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20334750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4016000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24350750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5999500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5999500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20334750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10015500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30350250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20334750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10015500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30350250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -488,17 +490,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70564.878893 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76056.603774 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71415.935673 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74466.049383 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74466.049383 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70564.878893 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75095.149254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70564.878893 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75095.149254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70362.456747 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75773.584906 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71201.023392 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74067.901235 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74067.901235 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70362.456747 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74742.537313 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70362.456747 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74742.537313 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71750 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,17 +520,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16781250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3376000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20157250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5037250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5037250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16781250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8413250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25194500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16781250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8413250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25194500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16720750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3361000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20081750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5004000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5004000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16720750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8365000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25085750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16720750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8365000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25085750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -540,27 +542,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58066.608997 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63698.113208 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58939.327485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62188.271605 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62188.271605 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58066.608997 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62785.447761 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59561.465721 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58066.608997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62785.447761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59561.465721 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57857.266436 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63415.094340 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58718.567251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61777.777778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61777.777778 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57857.266436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62425.373134 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59304.373522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57857.266436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62425.373134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59304.373522 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.369033 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 85.354091 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.369033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 85.354091 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020838 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020838 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id @@ -583,14 +585,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4594750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4594750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29091500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29091500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33686250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33686250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33686250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33686250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4579750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4579750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28882250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28882250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33462000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33462000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33462000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33462000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -607,14 +609,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75323.770492 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75323.770492 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70439.467312 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70439.467312 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71068.037975 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71068.037975 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71068.037975 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71068.037975 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75077.868852 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75077.868852 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69932.808717 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69932.808717 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70594.936709 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70594.936709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70594.936709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70594.936709 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked @@ -639,14 +641,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4097500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4097500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6115250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6115250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10212750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10212750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10212750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10212750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6083000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6083000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10165500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10165500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10165500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10165500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -655,14 +657,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75879.629630 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75879.629630 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75496.913580 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75496.913580 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75650 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75650 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75650 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75650 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75601.851852 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75601.851852 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75098.765432 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75098.765432 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75300 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75300 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75300 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75300 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index fd2ae491a..0e41891dc 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97647 # Simulator instruction rate (inst/s) -host_op_rate 97614 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49358124 # Simulator tick rate (ticks/s) -host_mem_usage 275540 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 1015247 # Simulator instruction rate (inst/s) +host_op_rate 1012545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 510902541 # Simulator tick rate (ticks/s) +host_mem_usage 261064 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -63,5 +63,40 @@ system.cpu.num_busy_cycles 5390 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction +system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5370 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 97d6558cc..0f04f9760 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu sim_ticks 107952 # Number of ticks simulated final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 1705 # Simulator instruction rate (inst/s) -host_op_rate 1705 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34543 # Simulator tick rate (ticks/s) -host_mem_usage 182496 # Number of bytes of host memory used -host_seconds 3.13 # Real time elapsed on the host +host_inst_rate 57135 # Simulator instruction rate (inst/s) +host_op_rate 57126 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1157488 # Simulator tick rate (ticks/s) +host_mem_usage 168948 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -128,6 +128,41 @@ system.cpu.num_busy_cycles 107952 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction +system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5370 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.968393 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 9e27f540c..f251b736b 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49661 # Simulator instruction rate (inst/s) -host_op_rate 49653 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 259077754 # Simulator tick rate (ticks/s) -host_mem_usage 284248 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 487107 # Simulator instruction rate (inst/s) +host_op_rate 486440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2535570960 # Simulator tick rate (ticks/s) +host_mem_usage 269788 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -69,6 +69,41 @@ system.cpu.num_busy_cycles 55600 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction +system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5370 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 33851c6e5..32cefdc54 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20069500 # Number of ticks simulated -final_tick 20069500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20011500 # Number of ticks simulated +final_tick 20011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42536 # Simulator instruction rate (inst/s) -host_op_rate 77054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158640887 # Simulator tick rate (ticks/s) -host_mem_usage 283320 # Number of bytes of host memory used +host_inst_rate 41048 # Simulator instruction rate (inst/s) +host_op_rate 74359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152650007 # Simulator tick rate (ticks/s) +host_mem_usage 284392 # Number of bytes of host memory used host_seconds 0.13 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17472 # Nu system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 414 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 870574753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 449637510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1320212262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 870574753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 870574753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 870574753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 449637510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1320212262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 873097969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 450940709 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1324038678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 873097969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 873097969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 873097969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 450940709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1324038678 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 415 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20021000 # Total gap between requests +system.physmem.totGap 19963000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,33 +186,31 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.676056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.837127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 281.987222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26 36.62% 36.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 26 36.62% 73.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 11.27% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 2.82% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.82% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.82% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 7.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation -system.physmem.totQLat 2360500 # Total ticks spent queuing -system.physmem.totMemAccLat 12135500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.697208 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 270.249471 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 33 34.02% 34.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 34 35.05% 69.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 13.40% 82.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 6.19% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.09% 94.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation +system.physmem.totQLat 4234000 # Total ticks spent queuing +system.physmem.totMemAccLat 12015250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers -system.physmem.totBankLat 7700000 # Total ticks spent accessing banks -system.physmem.avgQLat 5687.95 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 18554.22 # Average bank access latency per DRAM burst +system.physmem.avgQLat 10202.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29242.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1323.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28952.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1327.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1323.40 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1327.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.34 # Data bus utilization in percentage -system.physmem.busUtilRead 10.34 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.37 # Data bus utilization in percentage +system.physmem.busUtilRead 10.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,10 +218,14 @@ system.physmem.readRowHits 307 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 73.98 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48243.37 # Average gap between requests +system.physmem.avgGap 48103.61 # Average gap between requests system.physmem.pageHitRate 73.98 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1320212262 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15333750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1324038678 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 338 # Transaction distribution system.membus.trans_dist::ReadResp 337 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution @@ -236,109 +238,109 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 26496 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 501000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3871750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 3873250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 3084 # Number of BP lookups -system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups -system.cpu.branchPred.BTBHits 726 # Number of BTB hits +system.cpu.branchPred.lookups 3083 # Number of BP lookups +system.cpu.branchPred.condPredicted 3083 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2281 # Number of BTB lookups +system.cpu.branchPred.BTBHits 725 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.784305 # BTB Hit Percentage system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 40140 # number of cpu cycles simulated +system.cpu.numCycles 40024 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10289 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5352 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 10292 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14141 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3083 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3942 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2472 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5349 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21899 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.150509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.666400 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.150913 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.666787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18060 82.47% 82.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 216 0.99% 83.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18059 82.46% 82.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 217 0.99% 83.45% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 142 0.65% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.02% 85.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 181 0.83% 85.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 200 0.91% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.02% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 180 0.82% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 201 0.92% 86.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 275 1.26% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 159 0.73% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2442 11.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 159 0.73% 88.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2443 11.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21899 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.076831 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.352118 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11081 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5247 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 21900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077029 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.353313 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11088 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5242 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3583 # Number of cycles decode is running system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11446 # Number of cycles rename is idle +system.cpu.decode.SquashCycles 1856 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24179 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1856 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11454 # Number of cycles rename is idle system.cpu.rename.BlockCycles 3886 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3331 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 592 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3330 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 782 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22657 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made +system.cpu.rename.IQFullEvents 37 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 664 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25254 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55037 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14191 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 2053 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 20246 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17025 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 298 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9739 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13977 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21899 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.652832 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 21900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777397 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.653011 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16413 74.95% 74.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1539 7.03% 81.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1092 4.99% 86.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 724 3.31% 90.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 698 3.19% 93.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 576 2.63% 96.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 581 2.65% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16414 74.95% 74.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1544 7.05% 82.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1087 4.96% 86.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 722 3.30% 90.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 701 3.20% 93.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 573 2.62% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 583 2.66% 98.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21899 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21900 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available @@ -374,7 +376,7 @@ system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13665 80.26% 80.28% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued @@ -407,17 +409,17 @@ system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Ty system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17027 # Type of FU issued -system.cpu.iq.rate 0.424190 # Inst issue rate +system.cpu.iq.FU_type_0::total 17025 # Type of FU issued +system.cpu.iq.rate 0.425370 # Inst issue rate system.cpu.iq.fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56416 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010631 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56421 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30018 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17199 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -430,10 +432,10 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3086 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3085 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 20272 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions @@ -442,33 +444,33 @@ system.cpu.iew.iewIQFullEvents 4 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed +system.cpu.iew.predictedNotTakenIncorrect 571 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 687 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16122 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3127 # number of memory reference insts executed +system.cpu.iew.exec_refs 3126 # number of memory reference insts executed system.cpu.iew.exec_branches 1623 # Number of branches executed system.cpu.iew.exec_stores 1273 # Number of stores executed -system.cpu.iew.exec_rate 0.401694 # Inst execution rate -system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15646 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.402808 # Inst execution rate +system.cpu.iew.wb_sent 15864 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15645 # cumulative count of insts written-back system.cpu.iew.wb_producers 10128 # num instructions producing a value -system.cpu.iew.wb_consumers 15579 # num instructions consuming a value +system.cpu.iew.wb_consumers 15590 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.389786 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back +system.cpu.iew.wb_rate 0.390890 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.649647 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10536 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20042 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.486329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.342699 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 592 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20044 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.486280 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.342641 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16474 82.20% 82.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16476 82.20% 82.20% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1360 6.79% 88.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 589 2.94% 91.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 713 3.56% 95.48% # Number of insts commited each cycle @@ -480,7 +482,7 @@ system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20044 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -491,27 +493,62 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9653 # Number of committed integer instructions. system.cpu.commit.function_calls 106 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 9747 # Class of committed instruction system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40103 # The number of ROB reads -system.cpu.rob.rob_writes 42426 # The number of ROB writes -system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18241 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40115 # The number of ROB reads +system.cpu.rob.rob_writes 42444 # The number of ROB writes +system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18124 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 7.460967 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.460967 # CPI: Total CPI of All Threads -system.cpu.ipc 0.134031 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.134031 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 20727 # number of integer regfile reads -system.cpu.int_regfile_writes 12358 # number of integer regfile writes +system.cpu.cpi 7.439405 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.439405 # CPI: Total CPI of All Threads +system.cpu.ipc 0.134419 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.134419 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 20731 # number of integer regfile reads +system.cpu.int_regfile_writes 12356 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8004 # number of cc regfile reads -system.cpu.cc_regfile_writes 4850 # number of cc regfile writes -system.cpu.misc_regfile_reads 7135 # number of misc regfile reads +system.cpu.cc_regfile_reads 8007 # number of cc regfile reads +system.cpu.cc_regfile_writes 4854 # number of cc regfile writes +system.cpu.misc_regfile_reads 7133 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1326590099 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1330435000 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution @@ -526,61 +563,61 @@ system.cpu.toL2Bus.data_through_bus 26624 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 458250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 459500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 236250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.897576 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.942440 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.875912 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.897576 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063915 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063915 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 130.942440 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063937 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063937 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 274 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4234 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4234 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits -system.cpu.icache.overall_hits::total 1609 # number of overall hits +system.cpu.icache.tags.tag_accesses 4236 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4236 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits +system.cpu.icache.overall_hits::total 1610 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses system.cpu.icache.overall_misses::total 371 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25180750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25180750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25180750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25180750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25180750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25180750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1980 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1980 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1980 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187374 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.187374 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.187374 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67872.641509 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67872.641509 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67872.641509 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67872.641509 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67872.641509 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25106250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25106250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25106250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25106250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25106250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25106250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187279 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.187279 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187279 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.187279 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187279 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.187279 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67671.832884 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67671.832884 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67671.832884 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67671.832884 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -601,39 +638,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 274 system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19745750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19745750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19745750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19745750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19745750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19745750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138384 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138384 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138384 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72064.781022 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72064.781022 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72064.781022 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72064.781022 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19660000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19660000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71751.824818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71751.824818 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.708534 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.759335 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 337 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005935 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.966386 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.742148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003997 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.011600 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32.747734 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004996 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010284 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3750 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3750 # Number of data accesses @@ -657,17 +694,17 @@ system.cpu.l2cache.demand_misses::total 415 # nu system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 415 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19460250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5265000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24725250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5444500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5444500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19460250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10709500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30169750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19460250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10709500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30169750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19374500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5212250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24586750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5445500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5445500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19374500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10657750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30032250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19374500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10657750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30032250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) @@ -690,17 +727,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995204 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71282.967033 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73151.627219 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70707.792208 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70707.792208 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72698.192771 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71282.967033 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75419.014085 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72698.192771 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70968.864469 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80188.461538 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72741.863905 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70720.779221 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70720.779221 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72366.867470 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72366.867470 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,17 +757,17 @@ system.cpu.l2cache.demand_mshr_misses::total 415 system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16034750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4466500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20501250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4485000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4485000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16034750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8951500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24986250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16034750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8951500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24986250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15946000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4413250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20359250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4486000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4486000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15946000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8899250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24845250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15946000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8899250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24845250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses @@ -742,81 +779,81 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58735.347985 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68715.384615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60654.585799 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58246.753247 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58246.753247 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58735.347985 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63038.732394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60207.831325 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58410.256410 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67896.153846 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60234.467456 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58259.740260 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58259.740260 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.267922 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2337 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 83.261165 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2335 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.457746 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.443662 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.267922 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020329 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020329 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 83.261165 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020327 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020327 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5234 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5234 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5232 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5232 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2337 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2337 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2337 # number of overall hits -system.cpu.dcache.overall_hits::total 2337 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2335 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2335 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2335 # number of overall hits +system.cpu.dcache.overall_hits::total 2335 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses -system.cpu.dcache.overall_misses::total 209 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9669000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9669000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5702500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5702500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15371500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15371500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15371500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15371500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses +system.cpu.dcache.overall_misses::total 210 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9645750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9645750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5703500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5703500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15349250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15349250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15349250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15349250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2546 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2546 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2546 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2546 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081937 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081937 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2545 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2545 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2545 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2545 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082609 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.082609 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73250 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74058.441558 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74058.441558 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73547.846890 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73547.846890 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73547.846890 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.082515 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082515 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082515 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082515 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72524.436090 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72524.436090 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74071.428571 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74071.428571 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73091.666667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73091.666667 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -825,12 +862,12 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses @@ -839,30 +876,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5340000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5340000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5521500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5521500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10861500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10861500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10861500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10861500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5522500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5522500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10809750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10809750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10809750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10809750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040994 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040994 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80909.090909 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80909.090909 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71707.792208 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71707.792208 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75954.545455 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75954.545455 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.056189 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.056189 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80109.848485 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80109.848485 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71720.779221 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71720.779221 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 95eaee017..0a6735ef0 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57597 # Simulator instruction rate (inst/s) -host_op_rate 104318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60076981 # Simulator tick rate (ticks/s) -host_mem_usage 286548 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 478524 # Simulator instruction rate (inst/s) +host_op_rate 865796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 498092788 # Simulator tick rate (ticks/s) +host_mem_usage 271572 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -66,5 +66,40 @@ system.cpu.num_busy_cycles 11231 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index f68024429..be3906efe 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 27489 # Simulator instruction rate (inst/s) -host_op_rate 49793 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 621883 # Simulator tick rate (ticks/s) -host_mem_usage 193512 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 47256 # Simulator instruction rate (inst/s) +host_op_rate 85597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1069027 # Simulator tick rate (ticks/s) +host_mem_usage 179456 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -131,6 +131,41 @@ system.cpu.num_busy_cycles 121759 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.652970 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 35c0c845e..bc4d8d180 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28358000 # Number of ticks simulated final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50744 # Simulator instruction rate (inst/s) -host_op_rate 91910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 267330545 # Simulator tick rate (ticks/s) -host_mem_usage 295388 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 260669 # Simulator instruction rate (inst/s) +host_op_rate 471875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1371807276 # Simulator tick rate (ticks/s) +host_mem_usage 281320 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -74,6 +74,41 @@ system.cpu.num_busy_cycles 56716 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. |