diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/quick/se/00.hello | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/quick/se/00.hello')
21 files changed, 3297 insertions, 3227 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 6e7555e80..4f260b234 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -599,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -628,9 +630,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -641,27 +643,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 5b34c9429..59f6accef 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 17:24:08 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 10:37:19 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21065000 because target called exit() +Exiting @ tick 21025000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 489f9221e..1f269f774 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21025000 # Number of ticks simulated final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72274 # Simulator instruction rate (inst/s) -host_op_rate 72262 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 238397605 # Simulator tick rate (ticks/s) -host_mem_usage 265716 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 63804 # Simulator instruction rate (inst/s) +host_op_rate 63793 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 210460029 # Simulator tick rate (ticks/s) +host_mem_usage 221600 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -188,10 +188,10 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 224.218426 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.360278 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 24.05% 50.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 222.888418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.838248 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22 27.85% 27.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 22.78% 50.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # By system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation -system.physmem.totQLat 4394750 # Total ticks spent queuing -system.physmem.totMemAccLat 13544750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4169250 # Total ticks spent queuing +system.physmem.totMemAccLat 13319250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9005.64 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8543.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27755.64 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27293.55 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s @@ -228,50 +228,50 @@ system.physmem.memoryStateTime::PRE_PDN 0 # Ti system.physmem.memoryStateTime::ACT 15304250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.membus.throughput 1482425684 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 415 # Transaction distribution -system.membus.trans_dist::ReadResp 414 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.trans_dist::ReadReq 416 # Transaction distribution +system.membus.trans_dist::ReadResp 415 # Transaction distribution +system.membus.trans_dist::ReadExReq 72 # Transaction distribution +system.membus.trans_dist::ReadExResp 72 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 618500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4556750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4554750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2894 # Number of BP lookups -system.cpu.branchPred.condPredicted 1702 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2922 # Number of BP lookups +system.cpu.branchPred.condPredicted 1714 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 512 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2209 # Number of BTB lookups -system.cpu.branchPred.BTBHits 756 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2236 # Number of BTB lookups +system.cpu.branchPred.BTBHits 763 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.223631 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.123435 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 417 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2077 # DTB read hits +system.cpu.dtb.read_hits 2080 # DTB read hits system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2124 # DTB read accesses -system.cpu.dtb.write_hits 1062 # DTB write hits +system.cpu.dtb.read_accesses 2127 # DTB read accesses +system.cpu.dtb.write_hits 1064 # DTB write hits system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1093 # DTB write accesses -system.cpu.dtb.data_hits 3139 # DTB hits +system.cpu.dtb.write_accesses 1095 # DTB write accesses +system.cpu.dtb.data_hits 3144 # DTB hits system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3217 # DTB accesses -system.cpu.itb.fetch_hits 2387 # ITB hits +system.cpu.dtb.data_accesses 3222 # DTB accesses +system.cpu.itb.fetch_hits 2403 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2426 # ITB accesses +system.cpu.itb.fetch_accesses 2442 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -288,234 +288,235 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 42051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8515 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16590 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2968 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1911 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1438 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8528 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16754 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2922 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2995 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1927 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1100 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15000 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.106000 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.503194 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2403 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 389 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14718 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.138334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.533627 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12032 80.21% 80.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.12% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.56% 83.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 214 1.43% 85.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 255 1.70% 87.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 241 1.61% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.76% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 183 1.22% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 8.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11723 79.65% 79.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 324 2.20% 81.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.59% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 214 1.45% 84.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.73% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 243 1.65% 88.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.79% 90.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 187 1.27% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1274 8.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15000 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068821 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.394521 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9332 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1599 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2769 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1226 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 243 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14718 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.069487 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.398421 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9297 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1311 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2827 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1242 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 247 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15335 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15491 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1226 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 708 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2627 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 344 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14630 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 301 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10973 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18255 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18246 # Number of integer rename lookups +system.cpu.rename.SquashCycles 1242 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9496 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 220 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2672 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 534 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14802 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 481 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11114 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18470 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18461 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6403 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 874 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2768 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6544 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 484 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1358 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12973 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 13092 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10779 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6200 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3613 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 10822 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 61 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6316 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3704 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15000 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.718600 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361398 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14718 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.735290 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.419888 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10485 69.90% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1646 10.97% 80.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1153 7.69% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 753 5.02% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 501 3.34% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 269 1.79% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10506 71.38% 71.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1362 9.25% 80.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 966 6.56% 87.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 797 5.42% 92.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 583 3.96% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 288 1.96% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 161 1.09% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.28% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14718 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 18 15.38% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 61 52.14% 67.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 32.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7243 67.20% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2398 22.25% 89.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1133 10.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7283 67.30% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2401 22.19% 89.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1133 10.47% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10779 # Type of FU issued -system.cpu.iq.rate 0.256332 # Inst issue rate -system.cpu.iq.fu_busy_cnt 112 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010391 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36705 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19206 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9602 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10822 # Type of FU issued +system.cpu.iq.rate 0.257354 # Inst issue rate +system.cpu.iq.fu_busy_cnt 117 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010811 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36519 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19441 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9646 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10878 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10926 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 74 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1585 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1607 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 493 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 132 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 138 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1226 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 247 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13091 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2768 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1242 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 105 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13210 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1358 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 504 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10071 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 383 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 506 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10117 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2138 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 705 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3230 # number of memory reference insts executed -system.cpu.iew.exec_branches 1589 # Number of branches executed -system.cpu.iew.exec_stores 1095 # Number of stores executed -system.cpu.iew.exec_rate 0.239495 # Inst execution rate -system.cpu.iew.wb_sent 9755 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9612 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5069 # num instructions producing a value -system.cpu.iew.wb_consumers 6811 # num instructions consuming a value +system.cpu.iew.exec_refs 3235 # number of memory reference insts executed +system.cpu.iew.exec_branches 1594 # Number of branches executed +system.cpu.iew.exec_stores 1097 # Number of stores executed +system.cpu.iew.exec_rate 0.240589 # Inst execution rate +system.cpu.iew.wb_sent 9800 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9656 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5168 # num instructions producing a value +system.cpu.iew.wb_consumers 7004 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.228580 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.744237 # average fanout of values written-back +system.cpu.iew.wb_rate 0.229626 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737864 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6700 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6822 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13774 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.463845 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273398 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.474102 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.366169 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10981 79.72% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1489 10.81% 90.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 532 3.86% 94.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 235 1.71% 96.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 155 1.13% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 100 0.73% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 106 0.77% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.24% 98.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 143 1.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10977 81.46% 81.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1202 8.92% 90.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 500 3.71% 94.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 222 1.65% 95.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 141 1.05% 96.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 79 0.59% 97.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 99 0.73% 98.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 80 0.59% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 176 1.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13476 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -561,29 +562,29 @@ system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction -system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 176 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26369 # The number of ROB reads -system.cpu.rob.rob_writes 27413 # The number of ROB writes -system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27051 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26160 # The number of ROB reads +system.cpu.rob.rob_writes 27673 # The number of ROB writes +system.cpu.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27333 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12784 # number of integer regfile reads -system.cpu.int_regfile_writes 7268 # number of integer regfile writes +system.cpu.int_regfile_reads 12844 # number of integer regfile reads +system.cpu.int_regfile_writes 7306 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) @@ -596,59 +597,59 @@ system.cpu.toL2Bus.reqLayer0.occupancy 244500 # La system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 278250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 276750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.423717 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 159.493349 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1913 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.092357 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.423717 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077844 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077844 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 159.493349 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077878 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077878 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5088 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5088 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits -system.cpu.icache.overall_hits::total 1898 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses -system.cpu.icache.overall_misses::total 489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31330250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31330250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31330250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31330250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31330250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31330250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64070.040900 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64070.040900 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64070.040900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64070.040900 # average overall miss latency +system.cpu.icache.tags.tag_accesses 5120 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5120 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1913 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1913 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1913 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1913 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1913 # number of overall hits +system.cpu.icache.overall_hits::total 1913 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 490 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 490 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 490 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 490 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 490 # number of overall misses +system.cpu.icache.overall_misses::total 490 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31404750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31404750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31404750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31404750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31404750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31404750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2403 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2403 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2403 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2403 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2403 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2403 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.203912 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.203912 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.203912 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.203912 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.203912 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.203912 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64091.326531 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64091.326531 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64091.326531 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64091.326531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64091.326531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64091.326531 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -657,52 +658,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 174 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 174 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 174 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 174 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 174 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 174 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 175 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22016000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22016000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22016000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22016000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22016000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22016000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69892.063492 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69892.063492 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22044500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22044500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22044500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22044500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22044500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22044500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131086 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.131086 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.131086 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69982.539683 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69982.539683 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69982.539683 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69982.539683 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69982.539683 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69982.539683 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 219.258059 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.991091 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 415 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.507047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59.751013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004868 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006691 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.576725 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 60.414366 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004870 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001844 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006714 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4399 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4399 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits @@ -712,32 +713,32 @@ system.cpu.l2cache.demand_hits::total 1 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses @@ -746,7 +747,7 @@ system.cpu.l2cache.overall_accesses::cpu.data 174 system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses @@ -755,17 +756,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69076.433121 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76415.841584 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70862.650602 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78325.342466 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78325.342466 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71978.995902 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71978.995902 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69167.197452 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76465.686275 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70956.730769 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74843.750000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74843.750000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69167.197452 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75794.540230 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71530.225410 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69167.197452 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75794.540230 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71530.225410 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -775,30 +776,30 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4505750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4505750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17765000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11052250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28817250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17765000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11052250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28817250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses @@ -807,41 +808,41 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56488.853503 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64128.712871 # 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Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026180 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 107.281632 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026192 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026192 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5692 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5692 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1723 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34616722 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1896 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1896 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090285 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.090285 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2761 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2761 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2761 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2761 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090190 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.090190 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.192099 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.192099 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.192099 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.192099 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67020.467836 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67020.467836 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70891.303621 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70891.303621 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69642.411321 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69642.411321 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1529 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.191959 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.191959 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191959 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.191959 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67116.959064 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67116.959064 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64456.050139 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64456.050139 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65314.569811 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65314.569811 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65314.569811 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65314.569811 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1676 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.970588 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.900000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -906,30 +907,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7907500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7907500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5712750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5712750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13620250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13620250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13620250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13620250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053854 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053854 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7909000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7909000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5463750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5463750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13372750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13372750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13372750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13372750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053797 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053797 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77524.509804 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77524.509804 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79343.750000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063021 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77539.215686 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77539.215686 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75885.416667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75885.416667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76854.885057 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76854.885057 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76854.885057 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76854.885057 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 15208c06e..5d14be284 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -599,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/alpha/tru64/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -628,9 +630,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -641,27 +643,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index da1484dec..757b668d6 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 17:24:20 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 10:38:16 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 11990500 because target called exit() +Exiting @ tick 11975500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 8c004be4e..827c29bcd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11975500 # Number of ticks simulated final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56599 # Simulator instruction rate (inst/s) -host_op_rate 56579 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 283759448 # Simulator tick rate (ticks/s) -host_mem_usage 265424 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 28986 # Simulator instruction rate (inst/s) +host_op_rate 28981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 145369893 # Simulator tick rate (ticks/s) +host_mem_usage 220536 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,40 +238,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 344500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2556250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2554750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 1176 # Number of BP lookups -system.cpu.branchPred.condPredicted 619 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1179 # Number of BP lookups +system.cpu.branchPred.condPredicted 620 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups -system.cpu.branchPred.BTBHits 253 # Number of BTB hits +system.cpu.branchPred.BTBLookups 806 # Number of BTB lookups +system.cpu.branchPred.BTBHits 254 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.467662 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.513648 # BTB Hit Percentage system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 710 # DTB read hits +system.cpu.dtb.read_hits 712 # DTB read hits system.cpu.dtb.read_misses 31 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 741 # DTB read accesses +system.cpu.dtb.read_accesses 743 # DTB read accesses system.cpu.dtb.write_hits 368 # DTB write hits system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 388 # DTB write accesses -system.cpu.dtb.data_hits 1078 # DTB hits +system.cpu.dtb.data_hits 1080 # DTB hits system.cpu.dtb.data_misses 51 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1129 # DTB accesses -system.cpu.itb.fetch_hits 1065 # ITB hits +system.cpu.dtb.data_accesses 1131 # DTB accesses +system.cpu.itb.fetch_hits 1070 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1095 # ITB accesses +system.cpu.itb.fetch_accesses 1100 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -288,93 +288,92 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 23952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4342 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 531 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7041 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1179 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 466 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1215 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 516 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched +system.cpu.fetch.CacheLines 1070 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7705 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.909929 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.316850 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.913704 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.320621 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6496 84.31% 84.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.69% 85.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 115 1.49% 86.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.23% 87.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 176 2.28% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 76 0.99% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.83% 91.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.84% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 565 7.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6491 84.23% 84.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.69% 84.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 117 1.52% 86.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 96 1.25% 87.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 2.28% 89.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 76 0.99% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.83% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 66 0.86% 92.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 567 7.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7705 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049098 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.292710 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5480 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 569 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1153 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049223 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.293963 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5479 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 562 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1164 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 497 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 166 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 6225 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5578 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 497 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5576 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 257 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1063 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5900 # Number of instructions processed by rename +system.cpu.rename.RunCycles 1068 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 28 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5913 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4279 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6674 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6667 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 20 # Number of times rename has blocked due to IQ full +system.cpu.rename.RenamedOperands 4287 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6690 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6683 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2511 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2519 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 956 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 469 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 93 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4966 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4974 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4045 # Number of instructions issued +system.cpu.iq.iqInstsIssued 4048 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2341 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1389 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2349 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1396 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7705 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.524984 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.239779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7706 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.525305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.241065 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6081 78.92% 78.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6082 78.93% 78.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 565 7.33% 86.26% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 401 5.20% 91.46% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 263 3.41% 94.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 200 2.60% 97.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 120 1.56% 99.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 198 2.57% 97.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 121 1.57% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48 0.62% 99.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7705 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7706 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available @@ -410,7 +409,7 @@ system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2864 70.80% 70.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2866 70.80% 70.80% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.83% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.83% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.83% # Type of FU issued @@ -439,40 +438,40 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.83% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 785 19.41% 90.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 395 9.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 786 19.42% 90.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 395 9.76% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4045 # Type of FU issued -system.cpu.iq.rate 0.168879 # Inst issue rate +system.cpu.iq.FU_type_0::total 4048 # Type of FU issued +system.cpu.iq.rate 0.169005 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010878 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15880 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7311 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3652 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010870 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15887 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7327 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4082 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4085 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 541 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 175 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 176 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5308 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 497 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 231 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5316 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 956 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 469 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -480,31 +479,31 @@ system.cpu.iew.memOrderViolationEvents 4 # Nu system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 742 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 190 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3860 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 744 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 188 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 336 # number of nop insts executed -system.cpu.iew.exec_refs 1130 # number of memory reference insts executed +system.cpu.iew.exec_refs 1132 # number of memory reference insts executed system.cpu.iew.exec_branches 644 # Number of branches executed system.cpu.iew.exec_stores 388 # Number of stores executed -system.cpu.iew.exec_rate 0.160947 # Inst execution rate -system.cpu.iew.wb_sent 3738 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3658 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1710 # num instructions producing a value -system.cpu.iew.wb_consumers 2211 # num instructions consuming a value +system.cpu.iew.exec_rate 0.161156 # Inst execution rate +system.cpu.iew.wb_sent 3742 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3661 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1713 # num instructions producing a value +system.cpu.iew.wb_consumers 2215 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152722 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.773406 # average fanout of values written-back +system.cpu.iew.wb_rate 0.152847 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.773363 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2726 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2734 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7211 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.357232 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.199732 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 7209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.357331 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.199884 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6342 87.95% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6340 87.95% 87.95% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 204 2.83% 90.78% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 308 4.27% 95.05% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 114 1.58% 96.63% # Number of insts commited each cycle @@ -516,7 +515,7 @@ system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7211 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7209 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -564,18 +563,18 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # system.cpu.commit.op_class_0::total 2576 # Class of committed instruction system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12203 # The number of ROB reads -system.cpu.rob.rob_writes 11111 # The number of ROB writes +system.cpu.rob.rob_reads 12209 # The number of ROB reads +system.cpu.rob.rob_writes 11130 # The number of ROB writes system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16247 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 16246 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.cpi 10.034353 # CPI: Cycles Per Instruction system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4672 # number of integer regfile reads -system.cpu.int_regfile_writes 2825 # number of integer regfile writes +system.cpu.int_regfile_reads 4676 # number of integer regfile reads +system.cpu.int_regfile_writes 2829 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes @@ -599,56 +598,56 @@ system.cpu.toL2Bus.respLayer0.utilization 2.6 # L system.cpu.toL2Bus.respLayer1.occupancy 133500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 93.052511 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 93.052678 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 820 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.361702 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 93.052511 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 93.052678 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.045436 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.045436 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091797 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2318 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2318 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 815 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 815 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 815 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 815 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 815 # number of overall hits -system.cpu.icache.overall_hits::total 815 # number of overall hits +system.cpu.icache.tags.tag_accesses 2328 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2328 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 820 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 820 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 820 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 820 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 820 # number of overall hits +system.cpu.icache.overall_hits::total 820 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17506249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17506249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17506249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17506249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17506249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17506249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1065 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1065 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1065 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234742 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.234742 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70024.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70024.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70024.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70024.996000 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17505249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17505249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17505249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17505249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17505249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17505249 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1070 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1070 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1070 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1070 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1070 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1070 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233645 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.233645 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.233645 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.233645 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.233645 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.233645 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70020.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70020.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70020.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70020.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70020.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70020.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -669,33 +668,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 188 system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13110499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13110499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13110499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13110499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13110499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13110499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69736.696809 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69736.696809 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13109499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13109499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13109499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13109499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13109499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13109499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175701 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175701 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175701 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.175701 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175701 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.175701 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69731.377660 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69731.377660 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69731.377660 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69731.377660 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69731.377660 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69731.377660 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 121.888429 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 121.888470 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250749 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250833 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637638 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.003720 # Average percentage of cache occupancy @@ -716,17 +715,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12921750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17574250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12920750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17572750 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1688000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1688000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12921750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6340500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19262250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12921750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6340500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19262250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12920750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6340000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19260750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12920750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6340000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19260750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -749,17 +748,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68732.712766 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76270.491803 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70579.317269 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68727.393617 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76262.295082 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70573.293173 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70333.333333 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70333.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70557.692308 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70557.692308 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68727.393617 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74588.235294 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70552.197802 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68727.393617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74588.235294 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70552.197802 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -815,9 +814,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58044.871795 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 45.583444 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 759 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 761 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.929412 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.952941 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 45.583444 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.011129 # Average percentage of cache occupancy @@ -826,16 +825,16 @@ system.cpu.dcache.tags.occ_task_id_blocks::1024 85 system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1995 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 546 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 546 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1999 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1999 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 548 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 548 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 759 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 759 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 759 # number of overall hits -system.cpu.dcache.overall_hits::total 759 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 761 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 761 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 761 # number of overall hits +system.cpu.dcache.overall_hits::total 761 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses @@ -852,22 +851,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 13179000 system.cpu.dcache.demand_miss_latency::total 13179000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 13179000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 13179000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 661 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 661 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 955 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 955 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 955 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 955 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173979 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.173979 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 957 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 957 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 957 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 957 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173454 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.173454 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.205236 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.205236 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.205236 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.205236 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.204807 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.204807 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.204807 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.204807 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68493.478261 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 68493.478261 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65459.876543 # average WriteReq miss latency @@ -900,30 +899,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6427000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6427000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6427000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6427000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092284 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092284 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6426500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6426500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.089005 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.089005 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77270.491803 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77270.491803 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.088819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088819 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.088819 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77262.295082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77262.295082 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75605.882353 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75605.882353 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75605.882353 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75605.882353 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 367b15c5e..ec211ffe2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -174,6 +175,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=false system=system tracer=system.cpu.checker.tracer @@ -847,7 +849,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/arm/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -876,9 +878,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -889,27 +891,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 9a11b77d6..09918a5fe 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:05:52 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 11:25:19 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second - 0: system.cpu.checker.isa: ISA system set to: 0 0x5d826c0 - 0: system.cpu.isa: ISA system set to: 0 0x5d826c0 + 0: system.cpu.checker.isa: ISA system set to: 0 0x54ee6d0 + 0: system.cpu.isa: ISA system set to: 0 0x54ee6d0 info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 16981000 because target called exit() +Exiting @ tick 16786000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 52eced7fc..d39b9c7ba 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16955000 # Number of ticks simulated -final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16786000 # Number of ticks simulated +final_tick 16786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43189 # Simulator instruction rate (inst/s) -host_op_rate 53887 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 159459409 # Simulator tick rate (ticks/s) -host_mem_usage 309444 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 36444 # Simulator instruction rate (inst/s) +host_op_rate 45472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 133219523 # Simulator tick rate (ticks/s) +host_mem_usage 259336 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 392 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1029429286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 465149529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1494578816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1029429286 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1029429286 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1029429286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 465149529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1494578816 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 392 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue @@ -46,11 +46,11 @@ system.physmem.perBankRdBursts::1 46 # Pe system.physmem.perBankRdBursts::2 20 # Per bank write bursts system.physmem.perBankRdBursts::3 42 # Per bank write bursts system.physmem.perBankRdBursts::4 17 # Per bank write bursts -system.physmem.perBankRdBursts::5 34 # Per bank write bursts +system.physmem.perBankRdBursts::5 33 # Per bank write bursts system.physmem.perBankRdBursts::6 35 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::9 8 # Per bank write bursts system.physmem.perBankRdBursts::10 28 # Per bank write bursts system.physmem.perBankRdBursts::11 42 # Per bank write bursts system.physmem.perBankRdBursts::12 9 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16897500 # Total gap between requests +system.physmem.totGap 16721500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,70 +187,70 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 396.387097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 264.062800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.835382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 27.42% 45.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.90% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.29% 69.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.23% 72.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 8.06% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.61% 87.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 3795000 # Total ticks spent queuing -system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3300000 # Total ticks spent queuing +system.physmem.totMemAccLat 10650000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8418.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27168.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1494.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1494.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.56 # Data bus utilization in percentage -system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.68 # Data bus utilization in percentage +system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 326 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43105.87 # Average gap between requests +system.physmem.avgGap 42656.89 # Average gap between requests system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15324750 # Time in different power states +system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1475906812 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.throughput 1494578816 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 350 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution -system.membus.trans_dist::ReadExReq 41 # Transaction distribution -system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25024 # Total data (bytes) +system.membus.trans_dist::ReadExReq 42 # Transaction distribution +system.membus.trans_dist::ReadExResp 42 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 784 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 784 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25088 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25088 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 479500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3655500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2481 # Number of BP lookups -system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2517 # Number of BP lookups +system.cpu.branchPred.condPredicted 1805 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups -system.cpu.branchPred.BTBHits 697 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2002 # Number of BTB lookups +system.cpu.branchPred.BTBHits 714 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 35.664336 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 294 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -424,235 +424,237 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 33911 # number of cpu cycles simulated +system.cpu.numCycles 33573 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6921 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12073 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1008 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2659 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1630 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2378 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.162808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.572483 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10430 79.69% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.73% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.55% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 238 1.82% 84.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 231 1.76% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.06% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 93 0.71% 89.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.11% 90.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1254 9.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2426 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2227 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 13089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.074971 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.359604 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6910 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2688 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2492 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 31 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 385 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13358 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 539 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7139 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 151 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2277 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2296 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 258 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12614 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 195 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 12625 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57590 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 52228 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 47 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6952 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 666 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 329 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2826 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1583 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11316 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8961 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 149 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5288 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14803 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.684621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.402607 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9594 73.30% 73.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1210 9.24% 82.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 823 6.29% 88.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 494 3.77% 92.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 479 3.66% 96.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 298 2.28% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 131 1.00% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 49 0.37% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13089 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.71% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 138 62.44% 65.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 34.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5369 59.92% 59.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2357 26.30% 86.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1223 13.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.263071 # Inst issue rate -system.cpu.iq.fu_busy_cnt 224 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8961 # Type of FU issued +system.cpu.iq.rate 0.266911 # Inst issue rate +system.cpu.iq.fu_busy_cnt 221 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31345 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16624 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8077 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9162 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1626 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 645 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11366 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 115 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2826 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1583 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 266 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 376 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8568 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 393 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3300 # number of memory reference insts executed -system.cpu.iew.exec_branches 1437 # Number of branches executed -system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.251364 # Inst execution rate -system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3883 # num instructions producing a value -system.cpu.iew.wb_consumers 7789 # num instructions consuming a value +system.cpu.iew.exec_nop 1 # number of nop insts executed +system.cpu.iew.exec_refs 3332 # number of memory reference insts executed +system.cpu.iew.exec_branches 1443 # Number of branches executed +system.cpu.iew.exec_stores 1172 # Number of stores executed +system.cpu.iew.exec_rate 0.255205 # Inst execution rate +system.cpu.iew.wb_sent 8256 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8093 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3919 # num instructions producing a value +system.cpu.iew.wb_consumers 8062 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back +system.cpu.iew.wb_rate 0.241057 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.486108 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5642 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 326 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12121 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.472651 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.325156 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9924 81.87% 81.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 978 8.07% 89.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.32% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 224 1.85% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 175 1.44% 96.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 212 1.75% 98.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.41% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.27% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 123 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12121 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -698,213 +700,213 @@ system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5729 # Class of committed instruction -system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 123 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23248 # The number of ROB reads -system.cpu.rob.rob_writes 23415 # The number of ROB writes -system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23212 # The number of ROB reads +system.cpu.rob.rob_writes 23723 # The number of ROB writes +system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20484 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads -system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39214 # number of integer regfile reads -system.cpu.int_regfile_writes 7985 # number of integer regfile writes +system.cpu.cpi 7.312786 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.312786 # CPI: Total CPI of All Threads +system.cpu.ipc 0.136747 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.136747 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39407 # number of integer regfile reads +system.cpu.int_regfile_writes 7992 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 3239 # number of misc regfile reads +system.cpu.misc_regfile_reads 3253 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.throughput 1662337662 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 577 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 870 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27712 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 480500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 148.488883 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1601 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.520690 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4184 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits -system.cpu.icache.overall_hits::total 1584 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses -system.cpu.icache.overall_misses::total 363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 148.488883 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072504 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072504 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.141113 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4226 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4226 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits +system.cpu.icache.overall_hits::total 1601 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses +system.cpu.icache.overall_misses::total 367 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23960000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23960000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23960000 # 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number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15291000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5345250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20636250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2596250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2596250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7941500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23232500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15291000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7941500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23232500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903226 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903226 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56633.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66815.625000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58960.714286 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61815.476190 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61815.476190 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.019573 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.438356 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.019573 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021245 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021245 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 5964 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5964 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1782 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1782 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits -system.cpu.dcache.overall_hits::total 2373 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2378 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2378 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2378 # number of overall hits +system.cpu.dcache.overall_hits::total 2378 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses -system.cpu.dcache.overall_misses::total 496 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 507 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 507 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 507 # number of overall misses +system.cpu.dcache.overall_misses::total 507 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20684250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20684250 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 32297743 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32297743 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32297743 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32297743 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1972 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2885 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2885 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2885 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2885 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096349 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096349 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.175737 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175737 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175737 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175737 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61123.647368 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61123.647368 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65250 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65250 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63703.635108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63703.635108 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 118 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6871755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6871755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3151750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3151750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10023505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10023505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.050953 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.050953 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65445.285714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65445.285714 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75041.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75041.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index ecd158ad5..812706715 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,7 +699,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/arm/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index c3c8ec2e1..25b78577f 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:05:41 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 11:25:21 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x578c380 + 0: system.cpu.isa: ISA system set to: 0 0x4e56660 info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 16981000 because target called exit() +Exiting @ tick 16786000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index f55ae4f77..4a87577c2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16955000 # Number of ticks simulated -final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16786000 # Number of ticks simulated +final_tick 16786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52426 # Simulator instruction rate (inst/s) -host_op_rate 65410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 193552438 # Simulator tick rate (ticks/s) -host_mem_usage 308400 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 42967 # Simulator instruction rate (inst/s) +host_op_rate 53611 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 157060125 # Simulator tick rate (ticks/s) +host_mem_usage 258920 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 392 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1029429286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 465149529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1494578816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1029429286 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1029429286 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1029429286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 465149529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1494578816 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 392 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue @@ -46,11 +46,11 @@ system.physmem.perBankRdBursts::1 46 # Pe system.physmem.perBankRdBursts::2 20 # Per bank write bursts system.physmem.perBankRdBursts::3 42 # Per bank write bursts system.physmem.perBankRdBursts::4 17 # Per bank write bursts -system.physmem.perBankRdBursts::5 34 # Per bank write bursts +system.physmem.perBankRdBursts::5 33 # Per bank write bursts system.physmem.perBankRdBursts::6 35 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::9 8 # Per bank write bursts system.physmem.perBankRdBursts::10 28 # Per bank write bursts system.physmem.perBankRdBursts::11 42 # Per bank write bursts system.physmem.perBankRdBursts::12 9 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16897500 # Total gap between requests +system.physmem.totGap 16721500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,70 +187,70 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 396.387097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 264.062800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.835382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 27.42% 45.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.90% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.29% 69.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.23% 72.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 8.06% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.61% 87.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 3795000 # Total ticks spent queuing -system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3300000 # Total ticks spent queuing +system.physmem.totMemAccLat 10650000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8418.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27168.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1494.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1494.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.56 # Data bus utilization in percentage -system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.68 # Data bus utilization in percentage +system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 326 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43105.87 # Average gap between requests +system.physmem.avgGap 42656.89 # Average gap between requests system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15324750 # Time in different power states +system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1475906812 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.throughput 1494578816 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 350 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution -system.membus.trans_dist::ReadExReq 41 # Transaction distribution -system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25024 # Total data (bytes) +system.membus.trans_dist::ReadExReq 42 # Transaction distribution +system.membus.trans_dist::ReadExResp 42 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 784 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 784 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25088 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25088 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 479500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3655500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2481 # Number of BP lookups -system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2517 # Number of BP lookups +system.cpu.branchPred.condPredicted 1805 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups -system.cpu.branchPred.BTBHits 697 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2002 # Number of BTB lookups +system.cpu.branchPred.BTBHits 714 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 35.664336 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 294 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -337,235 +337,237 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 33911 # number of cpu cycles simulated +system.cpu.numCycles 33573 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6921 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12073 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1008 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2659 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1630 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2378 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.162808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.572483 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10430 79.69% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.73% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.55% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 238 1.82% 84.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 231 1.76% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.06% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 93 0.71% 89.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.11% 90.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1254 9.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2426 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2227 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 13089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.074971 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.359604 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6910 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2688 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2492 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 31 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 385 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13358 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 539 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7139 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 151 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2277 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2296 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 258 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12614 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 195 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 12625 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57590 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 52228 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 47 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6952 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 666 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 329 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2826 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1583 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11316 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8961 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 149 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5288 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14803 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.684621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.402607 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9594 73.30% 73.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1210 9.24% 82.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 823 6.29% 88.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 494 3.77% 92.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 479 3.66% 96.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 298 2.28% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 131 1.00% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 49 0.37% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13089 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.71% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 138 62.44% 65.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 34.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5369 59.92% 59.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2357 26.30% 86.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1223 13.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.263071 # Inst issue rate -system.cpu.iq.fu_busy_cnt 224 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8961 # Type of FU issued +system.cpu.iq.rate 0.266911 # Inst issue rate +system.cpu.iq.fu_busy_cnt 221 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31345 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16624 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8077 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9162 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1626 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 645 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11366 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 115 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2826 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1583 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 266 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 376 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8568 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 393 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3300 # number of memory reference insts executed -system.cpu.iew.exec_branches 1437 # Number of branches executed -system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.251364 # Inst execution rate -system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3883 # num instructions producing a value -system.cpu.iew.wb_consumers 7789 # num instructions consuming a value +system.cpu.iew.exec_nop 1 # number of nop insts executed +system.cpu.iew.exec_refs 3332 # number of memory reference insts executed +system.cpu.iew.exec_branches 1443 # Number of branches executed +system.cpu.iew.exec_stores 1172 # Number of stores executed +system.cpu.iew.exec_rate 0.255205 # Inst execution rate +system.cpu.iew.wb_sent 8256 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8093 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3919 # num instructions producing a value +system.cpu.iew.wb_consumers 8062 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back +system.cpu.iew.wb_rate 0.241057 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.486108 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5642 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 326 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12121 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.472651 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.325156 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9924 81.87% 81.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 978 8.07% 89.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.32% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 224 1.85% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 175 1.44% 96.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 212 1.75% 98.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.41% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.27% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 123 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12121 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -611,213 +613,213 @@ system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5729 # Class of committed instruction -system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 123 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23248 # The number of ROB reads -system.cpu.rob.rob_writes 23415 # The number of ROB writes -system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23212 # The number of ROB reads +system.cpu.rob.rob_writes 23723 # The number of ROB writes +system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20484 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads -system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39214 # number of integer regfile reads -system.cpu.int_regfile_writes 7985 # number of integer regfile writes +system.cpu.cpi 7.312786 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.312786 # CPI: Total CPI of All Threads +system.cpu.ipc 0.136747 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.136747 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39407 # number of integer regfile reads +system.cpu.int_regfile_writes 7992 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 3239 # number of misc regfile reads +system.cpu.misc_regfile_reads 3253 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.throughput 1662337662 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 577 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 870 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27712 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 480500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 148.488883 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1601 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.520690 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4184 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits -system.cpu.icache.overall_hits::total 1584 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses -system.cpu.icache.overall_misses::total 363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # 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average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 148.488883 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072504 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072504 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.141113 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4226 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4226 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1601 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76740.157480 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71609.571788 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69196.296296 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76740.157480 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71609.571788 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,179 +835,179 @@ system.cpu.l2cache.demand_mshr_hits::total 5 # system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15291000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5345250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20636250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2596250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2596250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7941500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23232500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15291000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7941500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23232500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903226 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903226 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56633.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66815.625000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58960.714286 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61815.476190 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61815.476190 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.019573 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.438356 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.019573 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021245 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021245 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 5964 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5964 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1782 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1782 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits -system.cpu.dcache.overall_hits::total 2373 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2378 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2378 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2378 # number of overall hits +system.cpu.dcache.overall_hits::total 2378 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses -system.cpu.dcache.overall_misses::total 496 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 507 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 507 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 507 # number of overall misses +system.cpu.dcache.overall_misses::total 507 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20684250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20684250 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 32297743 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32297743 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32297743 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32297743 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1972 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2885 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2885 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2885 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2885 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096349 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096349 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.175737 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175737 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175737 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175737 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61123.647368 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61123.647368 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65250 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65250 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63703.635108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63703.635108 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 118 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6871755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6871755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3151750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3151750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10023505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10023505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.050953 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.050953 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65445.285714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65445.285714 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75041.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75041.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index df84ba05d..d92641c25 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -601,7 +603,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/mips/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -630,9 +632,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -643,27 +645,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 3925c4814..f2d8bae1a 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout +Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:53:01 -gem5 started Jan 22 2014 17:28:02 -gem5 executing on u200540-lin -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing +gem5 compiled Jun 21 2014 10:59:13 +gem5 started Jun 21 2014 10:59:41 +gem5 executing on phenom +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 21898500 because target called exit() +Exiting @ tick 21842500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index dc9e77234..46dc5a264 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21843500 # Number of ticks simulated -final_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21842500 # Number of ticks simulated +final_tick 21842500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63396 # Simulator instruction rate (inst/s) -host_op_rate 63384 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 268482897 # Simulator tick rate (ticks/s) -host_mem_usage 267540 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 54203 # Simulator instruction rate (inst/s) +host_op_rate 54195 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 229554116 # Simulator tick rate (ticks/s) +host_mem_usage 222444 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 30528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory +system.physmem.bytes_read::total 30464 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 477 # Number of read requests accepted +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 981572622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 413139522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1394712144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 981572622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 981572622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 981572622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 413139522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1394712144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 476 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 30464 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 30464 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::11 20 # Pe system.physmem.perBankRdBursts::12 51 # Per bank write bursts system.physmem.perBankRdBursts::13 29 # Per bank write bursts system.physmem.perBankRdBursts::14 77 # Per bank write bursts -system.physmem.perBankRdBursts::15 8 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21764000 # Total gap between requests +system.physmem.totGap 21770000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 477 # Read request sizes (log2) +system.physmem.readPktSize::6 476 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,7 +91,7 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see @@ -186,72 +186,72 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation -system.physmem.totQLat 4715500 # Total ticks spent queuing -system.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 255.407407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.497802 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 250.634672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 31 28.70% 28.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39 36.11% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 14.81% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 7.41% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 3.70% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 0.93% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 2.78% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.93% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 4.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 108 # Bytes accessed per row activation +system.physmem.totQLat 4718000 # Total ticks spent queuing +system.physmem.totMemAccLat 13643000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2380000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9911.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28661.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1394.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1394.71 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.92 # Data bus utilization in percentage -system.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.90 # Data bus utilization in percentage +system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 357 # Number of row buffer hits during reads +system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.21 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45626.83 # Average gap between requests -system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined +system.physmem.avgGap 45735.29 # Average gap between requests +system.physmem.pageHitRate 75.21 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15319000 # Time in different power states +system.physmem.memoryStateTime::ACT 15316000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1397578227 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 426 # Transaction distribution -system.membus.trans_dist::ReadResp 426 # Transaction distribution +system.membus.throughput 1394712144 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 425 # Transaction distribution +system.membus.trans_dist::ReadResp 425 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30528 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 952 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 952 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 30464 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30464 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 4464750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2174 # Number of BP lookups -system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2178 # Number of BP lookups +system.cpu.branchPred.condPredicted 1497 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups -system.cpu.branchPred.BTBHits 492 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups +system.cpu.branchPred.BTBHits 491 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 29.596142 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 258 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -271,236 +271,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43688 # number of cpu cycles simulated +system.cpu.numCycles 43686 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8839 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13190 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2178 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 749 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3214 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1378 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1314 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14424 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.914448 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.226738 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.09% 93.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11210 77.72% 77.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1316 9.12% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 106 0.73% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 131 0.91% 88.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 113 0.78% 91.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 150 1.04% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 160 1.11% 93.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 933 6.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3025 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14424 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049856 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.301927 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8852 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1624 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3059 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 872 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12284 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 872 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9006 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 365 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2898 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups +system.cpu.rename.RunCycles 2923 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 285 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11879 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 266 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14112 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13884 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 151 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9223 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8300 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3436 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2075 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14424 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.575430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.252383 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10895 75.53% 75.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1375 9.53% 85.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 844 5.85% 90.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 571 3.96% 94.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 375 2.60% 97.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 225 1.56% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 91 0.63% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14424 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 3.09% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 102 62.96% 66.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 55 33.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4936 59.47% 59.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2249 27.10% 86.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1106 13.33% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8293 # Type of FU issued -system.cpu.iq.rate 0.189823 # Inst issue rate -system.cpu.iq.fu_busy_cnt 160 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8300 # Type of FU issued +system.cpu.iq.rate 0.189992 # Inst issue rate +system.cpu.iq.fu_busy_cnt 162 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019518 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31229 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12679 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8460 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1305 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 270 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 872 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 287 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10750 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 365 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7921 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 379 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1512 # number of nop insts executed -system.cpu.iew.exec_refs 3186 # number of memory reference insts executed -system.cpu.iew.exec_branches 1344 # Number of branches executed -system.cpu.iew.exec_stores 1079 # Number of stores executed -system.cpu.iew.exec_rate 0.181102 # Inst execution rate -system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7455 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2921 # num instructions producing a value -system.cpu.iew.wb_consumers 4197 # num instructions consuming a value +system.cpu.iew.exec_nop 1515 # number of nop insts executed +system.cpu.iew.exec_refs 3187 # number of memory reference insts executed +system.cpu.iew.exec_branches 1350 # Number of branches executed +system.cpu.iew.exec_stores 1077 # Number of stores executed +system.cpu.iew.exec_rate 0.181317 # Inst execution rate +system.cpu.iew.wb_sent 7554 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7469 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2985 # num instructions producing a value +system.cpu.iew.wb_consumers 4341 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.170642 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back +system.cpu.iew.wb_rate 0.170970 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.687630 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4930 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.428940 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.213640 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 149 1.09% 97.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11200 82.64% 82.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 943 6.96% 89.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 594 4.38% 93.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 344 2.54% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 162 1.20% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 97 0.72% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 69 0.51% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.30% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13552 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -546,93 +546,93 @@ system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5813 # Class of committed instruction -system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24239 # The number of ROB reads -system.cpu.rob.rob_writes 22333 # The number of ROB writes -system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24180 # The number of ROB reads +system.cpu.rob.rob_writes 22370 # The number of ROB writes +system.cpu.timesIdled 295 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29262 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.473235 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118019 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10743 # number of integer regfile reads -system.cpu.int_regfile_writes 5234 # number of integer regfile writes +system.cpu.cpi 8.472847 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.472847 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118024 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.118024 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10764 # number of integer regfile reads +system.cpu.int_regfile_writes 5241 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution +system.cpu.toL2Bus.throughput 1403502346 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 428 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 958 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30656 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 571750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.396825 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1520 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.497041 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.396825 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4268 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4268 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits -system.cpu.icache.overall_hits::total 1514 # number of overall hits +system.cpu.icache.tags.tag_accesses 4280 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4280 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1520 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1520 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1520 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1520 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1520 # number of overall hits +system.cpu.icache.overall_hits::total 1520 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses system.cpu.icache.overall_misses::total 451 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31166000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31166000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31166000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31166000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31166000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31166000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228818 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.228818 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.228818 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.228818 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.228818 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.228818 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69104.212860 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69104.212860 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69104.212860 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69104.212860 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69104.212860 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69104.212860 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -653,42 +653,42 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 338 system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24162750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24162750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24162750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24162750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24162750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24162750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.171487 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.171487 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.171487 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71487.426036 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71487.426036 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71487.426036 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71487.426036 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71487.426036 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71487.426036 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.498533 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 425 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.007059 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.688333 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810199 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 425 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4317 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012970 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4308 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4308 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -696,60 +696,60 @@ system.cpu.l2cache.demand_hits::total 3 # nu system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 426 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 425 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses +system.cpu.l2cache.overall_misses::total 476 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23794750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6985750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30780500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23794750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10762000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34556750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23794750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10762000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34556750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 479 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 480 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 479 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.993007 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.992991 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.993737 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71029.104478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77619.444444 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72424.705882 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71029.104478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76326.241135 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72598.214286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71029.104478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76326.241135 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72598.214286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -759,113 +759,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 425 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58385.820896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64007.092199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60050.945378 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.608220 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # 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Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5965 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5965 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 563 # 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number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2912 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2912 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2912 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2912 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075491 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075491 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175559 # 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number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7079250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7079250 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10907499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10907499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10907499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10907499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045294 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045294 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048420 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048420 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048420 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048420 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78658.333333 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78658.333333 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77358.148936 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77358.148936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77358.148936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77358.148936 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 31323532b..6b18ed844 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -116,6 +117,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -599,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/power/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -628,9 +630,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -641,27 +643,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index bf0b02582..72d83d0d3 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simout +Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:58:44 -gem5 started Jan 22 2014 17:29:11 -gem5 executing on u200540-lin -command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing +gem5 compiled Jun 21 2014 11:03:15 +gem5 started Jun 21 2014 11:03:43 +gem5 executing on phenom +command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 18905500 because target called exit() +Exiting @ tick 19030500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 47a5a4172..ca8bce664 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 19030500 # Number of ticks simulated final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79159 # Simulator instruction rate (inst/s) -host_op_rate 79144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 259986612 # Simulator tick rate (ticks/s) -host_mem_usage 262500 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 17395 # Simulator instruction rate (inst/s) +host_op_rate 17394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57147442 # Simulator tick rate (ticks/s) +host_mem_usage 218304 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -188,10 +188,10 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 198.974683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 351.274465 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28 36.36% 36.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 22.08% 58.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.719469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 351.121005 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27 35.06% 35.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 23.38% 58.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation @@ -199,12 +199,12 @@ system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # By system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation -system.physmem.totQLat 3599250 # Total ticks spent queuing -system.physmem.totMemAccLat 11961750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3354000 # Total ticks spent queuing +system.physmem.totMemAccLat 11716500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8070.07 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7520.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26820.07 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26270.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s @@ -213,7 +213,7 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 11.72 # Data bus utilization in percentage system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes @@ -237,19 +237,19 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 565500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 22.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2235 # Number of BP lookups -system.cpu.branchPred.condPredicted 1802 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2252 # Number of BP lookups +system.cpu.branchPred.condPredicted 1816 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1850 # Number of BTB lookups -system.cpu.branchPred.BTBHits 602 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1865 # Number of BTB lookups +system.cpu.branchPred.BTBHits 610 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.540541 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.707775 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -273,231 +273,232 @@ system.cpu.workload.num_syscalls 9 # Nu system.cpu.numCycles 38062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13154 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2235 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2260 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1309 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1810 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.107985 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.525542 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7462 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13226 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2252 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 809 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2276 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1296 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 871 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1823 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.152492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.564431 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9612 80.96% 80.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 176 1.48% 82.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.48% 83.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.20% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.91% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.11% 88.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.16% 90.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.93% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1040 8.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9200 80.17% 80.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 1.55% 81.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 178 1.55% 83.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 145 1.26% 84.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 228 1.99% 86.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.16% 87.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 261 2.27% 89.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.96% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1043 9.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.058720 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.345594 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7525 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1463 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2089 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 86 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 340 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 11476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059167 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.347486 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7479 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1089 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2174 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 714 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11724 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7710 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 717 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 445 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1980 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 311 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11305 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 11804 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 714 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7660 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2016 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 428 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11368 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 264 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18187 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18161 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 165 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 241 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9753 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18286 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18260 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4755 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 615 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. +system.cpu.rename.skidInsts 259 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2025 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1841 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10356 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8901 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8929 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4296 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3542 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11872 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.749747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.477871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.778059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.545863 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8485 71.47% 71.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1128 9.50% 80.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 793 6.68% 87.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 504 4.25% 91.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 456 3.84% 95.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 296 2.49% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 132 1.11% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8265 72.02% 72.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1011 8.81% 80.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 683 5.95% 86.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 469 4.09% 90.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 473 4.12% 94.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 313 2.73% 97.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 182 1.59% 99.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.38% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11872 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11476 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 73 42.20% 46.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 92 53.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 6.21% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 75 42.37% 48.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 91 51.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5476 61.52% 61.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1796 20.18% 81.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1627 18.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5495 61.54% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1798 20.14% 81.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1634 18.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8901 # Type of FU issued -system.cpu.iq.rate 0.233855 # Inst issue rate -system.cpu.iq.fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019436 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30026 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14573 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8128 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8929 # Type of FU issued +system.cpu.iq.rate 0.234591 # Inst issue rate +system.cpu.iq.fu_busy_cnt 177 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019823 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29690 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14680 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9072 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1062 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1064 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 795 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 457 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10360 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 714 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 160 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10413 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2025 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1841 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8500 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8526 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1682 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3201 # number of memory reference insts executed -system.cpu.iew.exec_branches 1350 # Number of branches executed -system.cpu.iew.exec_stores 1523 # Number of stores executed -system.cpu.iew.exec_rate 0.223320 # Inst execution rate -system.cpu.iew.wb_sent 8270 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8155 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4187 # num instructions producing a value -system.cpu.iew.wb_consumers 6623 # num instructions consuming a value +system.cpu.iew.exec_refs 3211 # number of memory reference insts executed +system.cpu.iew.exec_branches 1353 # Number of branches executed +system.cpu.iew.exec_stores 1529 # Number of stores executed +system.cpu.iew.exec_rate 0.224003 # Inst execution rate +system.cpu.iew.wb_sent 8294 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8178 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4388 # num instructions producing a value +system.cpu.iew.wb_consumers 6958 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.214256 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.632191 # average fanout of values written-back +system.cpu.iew.wb_rate 0.214860 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.630641 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4620 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11163 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.518857 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.312790 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.538190 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.389247 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8756 78.44% 78.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1031 9.24% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 625 5.60% 93.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 263 2.36% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.56% 97.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 104 0.93% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 65 0.58% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.39% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101 0.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8538 79.33% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 887 8.24% 87.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 552 5.13% 92.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 240 2.23% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 177 1.64% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 96 0.89% 97.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 118 1.10% 98.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 47 0.44% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 107 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11163 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10762 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -543,20 +544,20 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21428 # The number of ROB reads -system.cpu.rob.rob_writes 21442 # The number of ROB writes -system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26190 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21067 # The number of ROB reads +system.cpu.rob.rob_writes 21539 # The number of ROB writes +system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26586 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13470 # number of integer regfile reads -system.cpu.int_regfile_writes 7047 # number of integer regfile writes +system.cpu.int_regfile_reads 13502 # number of integer regfile reads +system.cpu.int_regfile_writes 7065 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s) @@ -574,61 +575,61 @@ system.cpu.toL2Bus.data_through_bus 28992 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 588250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 162000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.931685 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1369 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 169.076059 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1380 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.900285 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.931624 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.931685 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082486 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.076059 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082557 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082557 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 3971 # Number of tag accesses -system.cpu.icache.tags.data_accesses 3971 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1369 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1369 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1369 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1369 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1369 # number of overall hits -system.cpu.icache.overall_hits::total 1369 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses -system.cpu.icache.overall_misses::total 441 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30033500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30033500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30033500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30033500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30033500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30033500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1810 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1810 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1810 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1810 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1810 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1810 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243646 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.243646 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.243646 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.243646 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.243646 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.243646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68103.174603 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68103.174603 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68103.174603 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68103.174603 # average overall miss latency +system.cpu.icache.tags.tag_accesses 3997 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3997 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1380 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1380 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1380 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1380 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1380 # number of overall hits +system.cpu.icache.overall_hits::total 1380 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 443 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 443 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 443 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 443 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 443 # number of overall misses +system.cpu.icache.overall_misses::total 443 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 29586250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 29586250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 29586250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 29586250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 29586250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 29586250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1823 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1823 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1823 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.243006 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.243006 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.243006 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.243006 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.243006 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66786.117381 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66786.117381 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66786.117381 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66786.117381 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -637,51 +638,51 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24362250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24362250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24362250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24362250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24362250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24362250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193923 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69408.119658 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69408.119658 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24098750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24098750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24098750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24098750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24098750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24098750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192540 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.192540 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.192540 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68657.407407 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68657.407407 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.280245 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.437860 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.794904 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.485341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.936913 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.500947 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005125 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006082 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006086 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 215 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4070 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4070 # Number of data accesses @@ -705,17 +706,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4072250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28023000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3614250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3614250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7686500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31637250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7686500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31637250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23687250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4073750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27761000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3627250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3627250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23687250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7701000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31388250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23687250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7701000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31388250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -738,17 +739,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69422.463768 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75412.037037 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70233.082707 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76898.936170 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76898.936170 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70935.538117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70935.538117 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68658.695652 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75439.814815 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69576.441103 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77175.531915 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77175.531915 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68658.695652 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76247.524752 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70377.242152 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68658.695652 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76247.524752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70377.242152 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -768,17 +769,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19603250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3407750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3033250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3033250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19603250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6441000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26044250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19603250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6441000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26044250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19339750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3409250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22749000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3052750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3052750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19339750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6462000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25801750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19339750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6462000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25801750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -790,41 +791,41 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56821.014493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63106.481481 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57671.679198 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64537.234043 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64537.234043 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56057.246377 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63134.259259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57015.037594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64952.127660 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64952.127660 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56057.246377 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63980.198020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57851.457399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56057.246377 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63980.198020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57851.457399 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.690367 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.722947 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2180 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.372549 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.690367 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015549 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015549 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.722947 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015557 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015557 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5348 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5348 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5332 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5332 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1465 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1465 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits -system.cpu.dcache.overall_hits::total 2188 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2180 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2180 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2180 # number of overall hits +system.cpu.dcache.overall_hits::total 2180 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses @@ -833,38 +834,38 @@ system.cpu.dcache.demand_misses::cpu.data 435 # n system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7366750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7366750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20319996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20319996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27686746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27686746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27686746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27686746 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7380250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7380250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21128996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21128996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28509246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28509246 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28509246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28509246 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066284 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.066284 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70834.134615 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70834.134615 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61389.716012 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61389.716012 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63647.691954 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63647.691954 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.166348 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.166348 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166348 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166348 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70963.942308 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70963.942308 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63833.824773 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63833.824773 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65538.496552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65538.496552 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -889,30 +890,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4137750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4137750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3664248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3664248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7801998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7801998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7801998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7801998 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4139250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4139250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3677248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3677248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7816498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7816498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7816498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035054 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035054 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75231.818182 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75231.818182 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77962.723404 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77962.723404 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.039006 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.039006 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75259.090909 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75259.090909 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78239.319149 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78239.319149 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index b8e6ab850..016cd0c8d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -632,7 +634,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/x86/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -661,9 +663,9 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -674,27 +676,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 7bb858e94..289680317 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 17:29:56 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 11:13:51 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 19970500 because target called exit() +Exiting @ tick 19813000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 9459f1021..be2005774 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,55 +1,55 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20011500 # Number of ticks simulated -final_tick 20011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19813000 # Number of ticks simulated +final_tick 19813000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41048 # Simulator instruction rate (inst/s) -host_op_rate 74359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152650007 # Simulator tick rate (ticks/s) -host_mem_usage 284392 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 35950 # Simulator instruction rate (inst/s) +host_op_rate 65125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132368943 # Simulator tick rate (ticks/s) +host_mem_usage 240140 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 26496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 414 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 873097969 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 450940709 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1324038678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 873097969 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 873097969 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 873097969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 450940709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1324038678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 415 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory +system.physmem.bytes_read::total 26624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 416 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 885075456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 458688740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1343764195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 885075456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 885075456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 885075456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 458688740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1343764195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 33 # Per bank write bursts +system.physmem.perBankRdBursts::0 34 # Per bank write bursts system.physmem.perBankRdBursts::1 1 # Per bank write bursts -system.physmem.perBankRdBursts::2 5 # Per bank write bursts +system.physmem.perBankRdBursts::2 6 # Per bank write bursts system.physmem.perBankRdBursts::3 8 # Per bank write bursts system.physmem.perBankRdBursts::4 50 # Per bank write bursts system.physmem.perBankRdBursts::5 44 # Per bank write bursts -system.physmem.perBankRdBursts::6 20 # Per bank write bursts +system.physmem.perBankRdBursts::6 21 # Per bank write bursts system.physmem.perBankRdBursts::7 36 # Per bank write bursts -system.physmem.perBankRdBursts::8 23 # Per bank write bursts +system.physmem.perBankRdBursts::8 22 # Per bank write bursts system.physmem.perBankRdBursts::9 73 # Per bank write bursts system.physmem.perBankRdBursts::10 63 # Per bank write bursts system.physmem.perBankRdBursts::11 17 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19963000 # Total gap between requests +system.physmem.totGap 19764000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 415 # Read request sizes (log2) +system.physmem.readPktSize::6 417 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,197 +187,196 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 161.697208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 270.249471 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 250.721649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.075563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 270.532528 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 33 34.02% 34.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 34 35.05% 69.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 13.40% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 36 37.11% 71.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 9.28% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 5.15% 85.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 6 6.19% 91.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 3 3.09% 94.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation -system.physmem.totQLat 4234000 # Total ticks spent queuing -system.physmem.totMemAccLat 12015250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10202.41 # Average queueing delay per DRAM burst +system.physmem.totQLat 3851250 # Total ticks spent queuing +system.physmem.totMemAccLat 11670000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9235.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28952.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1327.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27985.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1346.99 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1327.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1346.99 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.37 # Data bus utilization in percentage -system.physmem.busUtilRead 10.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.52 # Data bus utilization in percentage +system.physmem.busUtilRead 10.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 307 # Number of row buffer hits during reads +system.physmem.readRowHits 310 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.98 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48103.61 # Average gap between requests -system.physmem.pageHitRate 73.98 # Row buffer hit rate, read and write combined +system.physmem.avgGap 47395.68 # Average gap between requests +system.physmem.pageHitRate 74.34 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15333750 # Time in different power states +system.physmem.memoryStateTime::ACT 15315750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1324038678 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 338 # Transaction distribution -system.membus.trans_dist::ReadResp 337 # Transaction distribution +system.membus.throughput 1343764195 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 340 # Transaction distribution +system.membus.trans_dist::ReadResp 339 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution system.membus.trans_dist::ReadExResp 77 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26496 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26624 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 501000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3873250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.4 # Layer utilization (%) +system.membus.reqLayer0.occupancy 508000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3892500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 3083 # Number of BP lookups -system.cpu.branchPred.condPredicted 3083 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2281 # Number of BTB lookups -system.cpu.branchPred.BTBHits 725 # Number of BTB hits +system.cpu.branchPred.lookups 3151 # Number of BP lookups +system.cpu.branchPred.condPredicted 3151 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 538 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2362 # Number of BTB lookups +system.cpu.branchPred.BTBHits 784 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.784305 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 33.192210 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 213 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 80 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 40024 # number of cpu cycles simulated +system.cpu.numCycles 39627 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10292 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14141 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3083 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3942 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2472 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5349 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21900 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.150913 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.666787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10249 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14342 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3151 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 997 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4009 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2516 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5030 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 499 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21739 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.176503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.686230 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18059 82.46% 82.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 217 0.99% 83.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 142 0.65% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.02% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 180 0.82% 85.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 201 0.92% 86.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 275 1.26% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 159 0.73% 88.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2443 11.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17828 82.01% 82.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 213 0.98% 82.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 156 0.72% 83.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.04% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 194 0.89% 85.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 208 0.96% 86.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 291 1.34% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 168 0.77% 88.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2454 11.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21900 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077029 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.353313 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11088 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5242 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3583 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1856 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24179 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1856 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11454 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3886 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 592 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3330 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 782 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22657 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 664 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25254 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55037 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21739 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.079516 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.361925 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11168 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4895 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3648 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1891 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24503 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1891 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11399 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 477 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 595 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3548 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3829 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 23145 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 51 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 3750 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 25950 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56380 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 31990 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14191 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2053 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20246 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17025 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 298 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9739 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13977 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21900 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777397 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.653011 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 14887 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1258 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 20529 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17116 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 311 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10025 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14683 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21739 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.787341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.689074 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16414 74.95% 74.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1544 7.05% 82.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1087 4.96% 86.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 722 3.30% 90.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 701 3.20% 93.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 573 2.62% 96.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 583 2.66% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16539 76.08% 76.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1246 5.73% 81.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 983 4.52% 86.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 694 3.19% 89.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 782 3.60% 93.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 618 2.84% 95.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 580 2.67% 98.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 252 1.16% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 45 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21739 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 136 76.40% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.61% 91.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 16 8.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13665 80.26% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13738 80.26% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.03% 80.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued @@ -405,84 +404,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1970 11.51% 91.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1393 8.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17025 # Type of FU issued -system.cpu.iq.rate 0.425370 # Inst issue rate -system.cpu.iq.fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010631 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56421 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30018 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17116 # Type of FU issued +system.cpu.iq.rate 0.431928 # Inst issue rate +system.cpu.iq.fu_busy_cnt 178 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010400 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56452 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30591 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15728 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17199 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17287 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 197 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1240 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 684 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3085 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20272 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1891 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 262 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20557 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 31 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 571 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 687 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16122 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 697 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16214 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1838 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 902 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3126 # number of memory reference insts executed -system.cpu.iew.exec_branches 1623 # Number of branches executed -system.cpu.iew.exec_stores 1273 # Number of stores executed -system.cpu.iew.exec_rate 0.402808 # Inst execution rate -system.cpu.iew.wb_sent 15864 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15645 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10128 # num instructions producing a value -system.cpu.iew.wb_consumers 15590 # num instructions consuming a value +system.cpu.iew.exec_refs 3129 # number of memory reference insts executed +system.cpu.iew.exec_branches 1636 # Number of branches executed +system.cpu.iew.exec_stores 1291 # Number of stores executed +system.cpu.iew.exec_rate 0.409165 # Inst execution rate +system.cpu.iew.wb_sent 15955 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15732 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10485 # num instructions producing a value +system.cpu.iew.wb_consumers 16294 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.390890 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.649647 # average fanout of values written-back +system.cpu.iew.wb_rate 0.397002 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.643488 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10536 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10809 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 592 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20044 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.486280 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.342641 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 19848 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.491082 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.377621 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16476 82.20% 82.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1360 6.79% 88.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 589 2.94% 91.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 713 3.56% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 364 1.82% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16557 83.42% 83.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1016 5.12% 88.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 561 2.83% 91.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 767 3.86% 95.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 387 1.95% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 137 0.69% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 118 0.59% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 73 0.37% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 232 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20044 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 19848 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -528,100 +527,100 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40115 # The number of ROB reads -system.cpu.rob.rob_writes 42444 # The number of ROB writes -system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18124 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40172 # The number of ROB reads +system.cpu.rob.rob_writes 43025 # The number of ROB writes +system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17888 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.439405 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.439405 # CPI: Total CPI of All Threads -system.cpu.ipc 0.134419 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.134419 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 20731 # number of integer regfile reads -system.cpu.int_regfile_writes 12356 # number of integer regfile writes +system.cpu.cpi 7.365613 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.365613 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135766 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135766 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 20766 # number of integer regfile reads +system.cpu.int_regfile_writes 12432 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8007 # number of cc regfile reads -system.cpu.cc_regfile_writes 4854 # number of cc regfile writes -system.cpu.misc_regfile_reads 7133 # number of misc regfile reads +system.cpu.cc_regfile_reads 8051 # number of cc regfile reads +system.cpu.cc_regfile_writes 4869 # number of cc regfile writes +system.cpu.misc_regfile_reads 7177 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1330435000 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution +system.cpu.toL2Bus.throughput 1346994398 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26688 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 459500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 461000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 236250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.942440 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.875912 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 131.410773 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.967273 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.942440 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063937 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063937 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 274 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4236 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4236 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits -system.cpu.icache.overall_hits::total 1610 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses -system.cpu.icache.overall_misses::total 371 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25106250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25106250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25106250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25106250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25106250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25106250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187279 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.187279 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.187279 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.187279 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.187279 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.187279 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67671.832884 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67671.832884 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67671.832884 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67671.832884 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 131.410773 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064165 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064165 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.134277 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4301 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4301 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1641 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1641 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1641 # number of overall hits +system.cpu.icache.overall_hits::total 1641 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 372 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 372 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 372 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 372 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 372 # number of overall misses +system.cpu.icache.overall_misses::total 372 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25012250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25012250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25012250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25012250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25012250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25012250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184799 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184799 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184799 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184799 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184799 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184799 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67237.231183 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67237.231183 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67237.231183 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67237.231183 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67237.231183 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67237.231183 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -631,112 +630,109 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 97 system.cpu.icache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 97 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 97 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19660000 # 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mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58410.256410 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67896.153846 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60234.467456 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58259.740260 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58259.740260 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57799.270073 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64215.909091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59044.852941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58360.389610 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58360.389610 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57799.270073 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61062.937063 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58918.465228 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57799.270073 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61062.937063 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58918.465228 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.261165 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2335 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 83.263820 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2308 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.443662 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.253521 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.261165 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020327 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020327 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 83.263820 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020328 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020328 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5232 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5232 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5178 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5178 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1450 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1450 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2335 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2335 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2335 # number of overall hits -system.cpu.dcache.overall_hits::total 2335 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2308 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2308 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2308 # number of overall hits +system.cpu.dcache.overall_hits::total 2308 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses @@ -821,38 +817,38 @@ system.cpu.dcache.demand_misses::cpu.data 210 # n system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses system.cpu.dcache.overall_misses::total 210 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9645750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9645750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5703500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5703500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15349250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15349250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15349250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15349250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1610 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9474500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9474500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5711750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5711750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15186250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15186250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15186250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15186250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1583 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1583 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2545 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2545 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2545 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2545 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082609 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082609 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2518 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2518 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2518 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2518 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084018 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.084018 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082515 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082515 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082515 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082515 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72524.436090 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72524.436090 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74071.428571 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74071.428571 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73091.666667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73091.666667 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.083400 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.083400 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.083400 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.083400 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71236.842105 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71236.842105 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74178.571429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74178.571429 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72315.476190 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72315.476190 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72315.476190 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72315.476190 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -875,30 +871,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5522500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5522500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10809750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10809750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10809750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10809750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040994 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5115250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5115250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5531250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5531250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10646500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10646500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10646500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10646500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041693 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041693 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056189 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056189 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80109.848485 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80109.848485 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71720.779221 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71720.779221 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056791 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.056791 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056791 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.056791 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77503.787879 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77503.787879 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71834.415584 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71834.415584 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74451.048951 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74451.048951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74451.048951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74451.048951 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |