diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
| commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
| tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/quick/se/00.hello | |
| parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
| download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz | |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/quick/se/00.hello')
23 files changed, 1619 insertions, 1600 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index acb604328..800d8e238 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:07:24 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 14:39:12 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 15802500 because target called exit() +Exiting @ tick 16032500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 8b0cd4f27..1a9d50ed7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16039500 # Number of ticks simulated -final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16032500 # Number of ticks simulated +final_tick 16032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1336 # Simulator instruction rate (inst/s) -host_op_rate 1336 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3362323 # Simulator tick rate (ticks/s) -host_mem_usage 225744 # Number of bytes of host memory used -host_seconds 4.77 # Real time elapsed on the host +host_inst_rate 34765 # Simulator instruction rate (inst/s) +host_op_rate 34761 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87452252 # Simulator tick rate (ticks/s) +host_mem_usage 269696 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19968 # Nu system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1245470139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 694589116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1940059255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1245470139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1245470139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1245470139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 694589116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1940059255 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 486 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15803000 # Total gap between requests +system.physmem.totGap 15819000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -149,27 +149,27 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2921750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests +system.physmem.totQLat 2907500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13642500 # Sum of mem lat for all requests system.physmem.totBusLat 2430000 # Total cycles spent in databus access system.physmem.totBankLat 8305000 # Total cycles spent in bank access -system.physmem.avgQLat 6011.83 # Average queueing delay per request +system.physmem.avgQLat 5982.51 # Average queueing delay per request system.physmem.avgBankLat 17088.48 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28100.31 # Average memory access latency -system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28070.99 # Average memory access latency +system.physmem.avgRdBW 1940.06 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1940.06 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.15 # Data bus utilization in percentage +system.physmem.busUtil 15.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 396 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32516.46 # Average gap between requests +system.physmem.avgGap 32549.38 # Average gap between requests system.cpu.branchPred.lookups 2896 # Number of BP lookups system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect @@ -212,10 +212,10 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 32080 # number of cpu cycles simulated +system.cpu.numCycles 32066 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 8354 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken @@ -226,49 +226,49 @@ system.cpu.fetch.MiscStallCycles 24 # Nu system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.139086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.536110 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 14511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.138929 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.535970 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11558 79.66% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11560 79.66% 79.66% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 185 1.28% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 185 1.27% 91.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 14511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090314 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.515406 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9311 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2753 # Number of cycles decode is running +system.cpu.decode.RunCycles 2752 # Number of cycles decode is running system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15363 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15357 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9517 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 9520 # Number of cycles rename is idle system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2631 # Number of cycles rename is running +system.cpu.rename.RunCycles 2630 # Number of cycles rename is running system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14679 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 14673 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11023 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18314 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18297 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 11018 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18307 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18290 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6453 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6448 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer @@ -283,15 +283,15 @@ system.cpu.iq.iqSquashedInstsIssued 50 # Nu system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14509 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.744779 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.389331 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14511 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.744676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.388965 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10032 69.14% 69.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1598 11.01% 80.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 759 5.23% 93.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 472 3.25% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10031 69.13% 69.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1602 11.04% 80.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 759 5.23% 93.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 471 3.25% 96.62% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle @@ -299,7 +299,7 @@ system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14511 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available @@ -369,12 +369,12 @@ system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 10806 # Type of FU issued -system.cpu.iq.rate 0.336845 # Inst issue rate +system.cpu.iq.rate 0.336992 # Inst issue rate system.cpu.iq.fu_busy_cnt 118 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 36270 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9700 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 9699 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses @@ -395,7 +395,7 @@ system.cpu.iew.iewSquashCycles 1212 # Nu system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 147 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions @@ -405,33 +405,33 @@ system.cpu.iew.memOrderViolationEvents 17 # Nu system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10154 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 10153 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 653 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 86 # number of nop insts executed system.cpu.iew.exec_refs 3233 # number of memory reference insts executed system.cpu.iew.exec_branches 1613 # Number of branches executed system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.316521 # Inst execution rate -system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9710 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5134 # num instructions producing a value -system.cpu.iew.wb_consumers 6919 # num instructions consuming a value +system.cpu.iew.exec_rate 0.316628 # Inst execution rate +system.cpu.iew.wb_sent 9856 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9709 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5133 # num instructions producing a value +system.cpu.iew.wb_consumers 6918 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back +system.cpu.iew.wb_rate 0.302782 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.741977 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13297 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.480484 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.303494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.480412 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.303409 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10548 79.33% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10550 79.33% 79.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 514 3.87% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 514 3.86% 94.07% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle @@ -441,7 +441,7 @@ system.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13299 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -454,32 +454,32 @@ system.cpu.commit.int_insts 6307 # Nu system.cpu.commit.function_calls 127 # Number of function calls committed. system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25928 # The number of ROB reads +system.cpu.rob.rob_reads 25930 # The number of ROB reads system.cpu.rob.rob_writes 27481 # The number of ROB writes system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17555 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads -system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12888 # number of integer regfile reads -system.cpu.int_regfile_writes 7343 # number of integer regfile writes +system.cpu.cpi 5.032329 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.032329 # CPI: Total CPI of All Threads +system.cpu.ipc 0.198715 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.198715 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12887 # number of integer regfile reads +system.cpu.int_regfile_writes 7342 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use +system.cpu.icache.tagsinuse 159.192462 # Cycle average of tags in use system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 159.192462 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits @@ -492,12 +492,12 @@ system.cpu.icache.demand_misses::cpu.inst 480 # n system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses system.cpu.icache.overall_misses::total 480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22197500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22197500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22197500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22197500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22197500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22197500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22201500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22201500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22201500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22201500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22201500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22201500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses @@ -510,12 +510,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46244.791667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46244.791667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46244.791667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46244.791667 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.125000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46253.125000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.125000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46253.125000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.125000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46253.125000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -536,36 +536,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 313 system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16111000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16111000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16111000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16111000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16111000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16111000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16101000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16101000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51472.843450 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51472.843450 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51440.894569 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51440.894569 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51440.894569 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51440.894569 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51440.894569 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51440.894569 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.754912 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 159.415983 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 60.338929 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004865 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 159.327579 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 60.315874 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006706 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -583,17 +583,17 @@ system.cpu.l2cache.demand_misses::total 486 # nu system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 486 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15786000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15776000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21866500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21856500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15786000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15776000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25554000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15786000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 25544000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15776000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25554000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25544000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) @@ -616,17 +616,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997947 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50596.153846 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50564.102564 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52945.520581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52921.307506 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50564.102564 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52580.246914 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52559.670782 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50564.102564 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52580.246914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52559.670782 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,17 +646,17 @@ system.cpu.l2cache.demand_mshr_misses::total 486 system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916495 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11906745 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16765286 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16755536 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916495 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11906745 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19561067 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916495 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19551317 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11906745 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19561067 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19551317 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses @@ -668,27 +668,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38193.894231 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38162.644231 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40593.912833 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40570.305085 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.644231 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40229.047325 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.644231 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40229.047325 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.750370 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 107.714584 # Cycle average of tags in use system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.750370 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026306 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026306 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 107.714584 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026298 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026298 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits @@ -705,14 +705,14 @@ system.cpu.dcache.demand_misses::cpu.data 528 # n system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses system.cpu.dcache.overall_misses::total 528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9127000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9127000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9128000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 15893487 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 15893487 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25020487 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25020487 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25020487 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25020487 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25021487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25021487 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25021487 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25021487 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1925 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1925 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -729,14 +729,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.189247 system.cpu.dcache.demand_miss_rate::total 0.189247 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.189247 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.189247 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54005.917160 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54005.917160 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54011.834320 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54011.834320 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44271.551532 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 44271.551532 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47387.285985 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47387.285985 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47389.179924 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47389.179924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47389.179924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47389.179924 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 862 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index cb5c70de3..4ea05c228 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:48:19 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 14:39:13 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 9059000 because target called exit() +Exiting @ tick 9350000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index c84a7ed5c..d97241466 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000009 # Nu sim_ticks 9350000 # Number of ticks simulated final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55287 # Simulator instruction rate (inst/s) -host_op_rate 55271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216439769 # Simulator tick rate (ticks/s) -host_mem_usage 224436 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 14656 # Simulator instruction rate (inst/s) +host_op_rate 14654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57391857 # Simulator tick rate (ticks/s) +host_mem_usage 269408 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 1328750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7872500 # Sum of mem lat for all requests +system.physmem.totQLat 1327750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7871500 # Sum of mem lat for all requests system.physmem.totBusLat 1360000 # Total cycles spent in databus access system.physmem.totBankLat 5183750 # Total cycles spent in bank access -system.physmem.avgQLat 4885.11 # Average queueing delay per request +system.physmem.avgQLat 4881.43 # Average queueing delay per request system.physmem.avgBankLat 19057.90 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28943.01 # Average memory access latency +system.physmem.avgMemAccLat 28939.34 # Average memory access latency system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s @@ -215,7 +215,7 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 18701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 4191 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 6947 # Number of instructions fetch has processed system.cpu.fetch.Branches 1154 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 450 # Number of branches that fetch has predicted taken @@ -227,26 +227,26 @@ system.cpu.fetch.PendingTrapStallCycles 1024 # Nu system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1043 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.949044 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.362722 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7322 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.948784 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.362451 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6126 83.69% 83.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6128 83.69% 83.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 54 0.74% 84.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 114 1.56% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 114 1.56% 85.99% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 92 1.26% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 168 2.30% 89.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 73 1.00% 90.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 168 2.29% 89.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 73 1.00% 90.54% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 64 0.87% 91.41% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 64 0.87% 92.28% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 565 7.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 7322 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.061708 # Number of branch fetches per cycle system.cpu.fetch.rate 0.371477 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5332 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 5334 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 332 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1148 # Number of cycles decode is running system.cpu.decode.UnblockCycles 8 # Number of cycles decode is unblocking @@ -256,7 +256,7 @@ system.cpu.decode.BranchMispred 81 # Nu system.cpu.decode.DecodedInsts 6173 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 500 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5432 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 5434 # Number of cycles rename is idle system.cpu.rename.BlockCycles 109 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 186 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1056 # Number of cycles rename is running @@ -284,14 +284,14 @@ system.cpu.iq.iqSquashedInstsIssued 53 # Nu system.cpu.iq.iqSquashedInstsExamined 2458 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 1421 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7320 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.555328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.267026 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7322 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.555176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.266886 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5695 77.80% 77.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 561 7.66% 85.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5697 77.81% 77.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 561 7.66% 85.47% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 397 5.42% 90.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 261 3.57% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 261 3.56% 94.46% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 207 2.83% 97.28% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 126 1.72% 99.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 50 0.68% 99.69% # Number of insts issued each cycle @@ -300,7 +300,7 @@ system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7322 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 2 4.35% 4.35% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available @@ -373,7 +373,7 @@ system.cpu.iq.FU_type_0::total 4065 # Ty system.cpu.iq.rate 0.217368 # Inst issue rate system.cpu.iq.fu_busy_cnt 46 # FU busy when requested system.cpu.iq.fu_busy_rate 0.011316 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15536 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 15538 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 7472 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3658 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads @@ -417,23 +417,23 @@ system.cpu.iew.exec_stores 377 # Nu system.cpu.iew.exec_rate 0.205978 # Inst execution rate system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit system.cpu.iew.wb_count 3664 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1730 # num instructions producing a value -system.cpu.iew.wb_consumers 2229 # num instructions consuming a value +system.cpu.iew.wb_producers 1729 # num instructions producing a value +system.cpu.iew.wb_consumers 2228 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.195925 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.776133 # average fanout of values written-back +system.cpu.iew.wb_fanout 0.776032 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 2758 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6820 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.377713 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.238824 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 6822 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.377602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.238659 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5956 87.33% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5958 87.34% 87.34% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 201 2.95% 90.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 310 4.55% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 116 1.70% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 310 4.54% 94.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 116 1.70% 96.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 63 0.92% 97.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 50 0.73% 98.18% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 32 0.47% 98.65% # Number of insts commited each cycle @@ -442,7 +442,7 @@ system.cpu.commit.committed_per_cycle::8 69 1.01% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6820 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6822 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -455,10 +455,10 @@ system.cpu.commit.int_insts 2367 # Nu system.cpu.commit.function_calls 71 # Number of function calls committed. system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11838 # The number of ROB reads +system.cpu.rob.rob_reads 11840 # The number of ROB reads system.cpu.rob.rob_writes 11181 # The number of ROB writes system.cpu.timesIdled 163 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11381 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11379 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated @@ -492,12 +492,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12422499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12422499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12422499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12422499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12422499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12422499 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12418499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12418499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12418499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12418499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12418499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12418499 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1043 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1043 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1043 # number of demand (read+write) accesses @@ -510,12 +510,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.238734 system.cpu.icache.demand_miss_rate::total 0.238734 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.238734 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.238734 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49889.554217 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49889.554217 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49889.554217 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49889.554217 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49889.554217 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49889.554217 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.489960 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49873.489960 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.489960 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49873.489960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.489960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49873.489960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 160 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -536,24 +536,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187 system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9626999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9626999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9626999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9626999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9626999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9626999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9624999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9624999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9624999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9624999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9624999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9624999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.179291 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.179291 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.179291 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51481.278075 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51481.278075 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51481.278075 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51481.278075 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51470.582888 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51470.582888 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51470.582888 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51470.582888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51470.582888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51470.582888 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 119.099647 # Cycle average of tags in use @@ -577,17 +577,17 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9437000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3587500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13026500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13024500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1408000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1408000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9439000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9437000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 4995500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14434500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9439000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 14432500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9437000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 4995500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14434500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14432500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -610,17 +610,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50475.935829 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50465.240642 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58811.475410 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52526.209677 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52518.145161 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58666.666667 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58666.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50475.935829 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50465.240642 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53068.014706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50475.935829 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53060.661765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50465.240642 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53068.014706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53060.661765 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,17 +640,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118144 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7116144 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838783 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9956927 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9954927 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114012 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114012 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118144 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7116144 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952795 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11070939 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118144 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11068939 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7116144 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952795 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11070939 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11068939 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -662,17 +662,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38064.941176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38054.245989 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.426230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40148.899194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40140.834677 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.166667 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38054.245989 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40694.628676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38054.245989 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40694.628676 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 875543733..99487a7ba 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -588,6 +588,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -620,6 +621,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -630,6 +632,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index df6ac8e30..d6f213d3f 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:43:45 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 26 2013 15:15:53 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13354000 because target called exit() +Exiting @ tick 13706000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ed4523776..8dbb84df8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13709000 # Number of ticks simulated -final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13706000 # Number of ticks simulated +final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31817 # Simulator instruction rate (inst/s) -host_op_rate 39697 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 94976589 # Simulator tick rate (ticks/s) -host_mem_usage 239960 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 599 # Simulator instruction rate (inst/s) +host_op_rate 748 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1788642 # Simulator tick rate (ticks/s) +host_mem_usage 284080 # Number of bytes of host memory used +host_seconds 7.66 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13651500 # Total gap between requests +system.physmem.totGap 13648500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -157,9 +157,9 @@ system.physmem.avgQLat 6364.85 # Av system.physmem.avgBankLat 18461.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 29826.14 # Average memory access latency -system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 14.37 # Data bus utilization in percentage @@ -169,14 +169,14 @@ system.physmem.readRowHits 294 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34648.48 # Average gap between requests -system.cpu.branchPred.lookups 2501 # Number of BP lookups -system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect +system.physmem.avgGap 34640.86 # Average gap between requests +system.cpu.branchPred.lookups 2491 # Number of BP lookups +system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups -system.cpu.branchPred.BTBHits 702 # Number of BTB hits +system.cpu.branchPred.BTBHits 700 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits @@ -267,176 +267,176 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 27419 # number of cpu cycles simulated +system.cpu.numCycles 27413 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2445 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2438 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2245 # Number of cycles rename is running +system.cpu.rename.RunCycles 2238 # Number of cycles rename is running system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8986 # Type of FU issued -system.cpu.iq.rate 0.327729 # Inst issue rate -system.cpu.iq.fu_busy_cnt 228 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8967 # Type of FU issued +system.cpu.iq.rate 0.327108 # Inst issue rate +system.cpu.iq.fu_busy_cnt 230 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed @@ -445,57 +445,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3302 # number of memory reference insts executed -system.cpu.iew.exec_branches 1444 # Number of branches executed +system.cpu.iew.exec_refs 3301 # number of memory reference insts executed +system.cpu.iew.exec_branches 1438 # Number of branches executed system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.312302 # Inst execution rate -system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8106 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3904 # num instructions producing a value -system.cpu.iew.wb_consumers 7842 # num instructions consuming a value +system.cpu.iew.exec_rate 0.311713 # Inst execution rate +system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3894 # num instructions producing a value +system.cpu.iew.wb_consumers 7825 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back +system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -506,74 +506,74 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23072 # The number of ROB reads -system.cpu.rob.rob_writes 23605 # The number of ROB writes -system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23047 # The number of ROB reads +system.cpu.rob.rob_writes 23560 # The number of ROB writes +system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads -system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39366 # number of integer regfile reads -system.cpu.int_regfile_writes 8019 # number of integer regfile writes +system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads +system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39296 # number of integer regfile reads +system.cpu.int_regfile_writes 8001 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2982 # number of misc regfile reads +system.cpu.misc_regfile_reads 2981 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use -system.cpu.icache.total_refs 1596 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use +system.cpu.icache.total_refs 1590 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits -system.cpu.icache.overall_hits::total 1596 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits +system.cpu.icache.overall_hits::total 1590 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -589,36 +589,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.107247 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.394475 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.712772 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004223 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001426 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005649 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits @@ -639,17 +639,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19078000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14110000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 21480500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14110000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21480500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -672,17 +672,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51875 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53290.502793 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51875 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53835.839599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51875 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53835.839599 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -708,17 +708,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735459 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14491743 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735459 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16388514 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735459 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16388514 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -730,39 +730,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39468.599265 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41053.096317 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use -system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.521929 # Cycle average of tags in use +system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.376712 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.521929 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021124 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021124 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits -system.cpu.dcache.overall_hits::total 2370 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits +system.cpu.dcache.overall_hits::total 2369 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses @@ -783,28 +783,28 @@ system.cpu.dcache.demand_miss_latency::cpu.data 23550000 system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency @@ -849,14 +849,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 24bdf3e80..a72da393a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -553,6 +555,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index e90c24cf4..ed98a8f73 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:43:34 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 26 2013 15:15:53 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13354000 because target called exit() +Exiting @ tick 13706000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index ef2f22c88..f41a24ed6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13709000 # Number of ticks simulated -final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13706000 # Number of ticks simulated +final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36221 # Simulator instruction rate (inst/s) -host_op_rate 45190 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108117571 # Simulator tick rate (ticks/s) -host_mem_usage 238932 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 7143 # Simulator instruction rate (inst/s) +host_op_rate 8913 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21323596 # Simulator tick rate (ticks/s) +host_mem_usage 284080 # Number of bytes of host memory used +host_seconds 0.64 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13651500 # Total gap between requests +system.physmem.totGap 13648500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -157,9 +157,9 @@ system.physmem.avgQLat 6364.85 # Av system.physmem.avgBankLat 18461.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 29826.14 # Average memory access latency -system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 14.37 # Data bus utilization in percentage @@ -169,14 +169,14 @@ system.physmem.readRowHits 294 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34648.48 # Average gap between requests -system.cpu.branchPred.lookups 2501 # Number of BP lookups -system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect +system.physmem.avgGap 34640.86 # Average gap between requests +system.cpu.branchPred.lookups 2491 # Number of BP lookups +system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups -system.cpu.branchPred.BTBHits 702 # Number of BTB hits +system.cpu.branchPred.BTBHits 700 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -222,176 +222,176 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 27419 # number of cpu cycles simulated +system.cpu.numCycles 27413 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2445 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2438 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2245 # Number of cycles rename is running +system.cpu.rename.RunCycles 2238 # Number of cycles rename is running system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8986 # Type of FU issued -system.cpu.iq.rate 0.327729 # Inst issue rate -system.cpu.iq.fu_busy_cnt 228 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8967 # Type of FU issued +system.cpu.iq.rate 0.327108 # Inst issue rate +system.cpu.iq.fu_busy_cnt 230 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed @@ -400,57 +400,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3302 # number of memory reference insts executed -system.cpu.iew.exec_branches 1444 # Number of branches executed +system.cpu.iew.exec_refs 3301 # number of memory reference insts executed +system.cpu.iew.exec_branches 1438 # Number of branches executed system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.312302 # Inst execution rate -system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8106 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3904 # num instructions producing a value -system.cpu.iew.wb_consumers 7842 # num instructions consuming a value +system.cpu.iew.exec_rate 0.311713 # Inst execution rate +system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3894 # num instructions producing a value +system.cpu.iew.wb_consumers 7825 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back +system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,74 +461,74 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23072 # The number of ROB reads -system.cpu.rob.rob_writes 23605 # The number of ROB writes -system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23047 # The number of ROB reads +system.cpu.rob.rob_writes 23560 # The number of ROB writes +system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads -system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39366 # number of integer regfile reads -system.cpu.int_regfile_writes 8019 # number of integer regfile writes +system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads +system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39296 # number of integer regfile reads +system.cpu.int_regfile_writes 8001 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2982 # number of misc regfile reads +system.cpu.misc_regfile_reads 2981 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use -system.cpu.icache.total_refs 1596 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use +system.cpu.icache.total_refs 1590 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits -system.cpu.icache.overall_hits::total 1596 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits +system.cpu.icache.overall_hits::total 1590 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -544,36 +544,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.107247 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.394475 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.712772 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004223 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001426 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005649 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits @@ -594,17 +594,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19078000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14110000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 21480500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14110000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21480500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -627,17 +627,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51875 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53290.502793 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51875 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53835.839599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51875 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53835.839599 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -663,17 +663,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735459 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14491743 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735459 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16388514 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735459 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16388514 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -685,39 +685,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39468.599265 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41053.096317 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use -system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.521929 # Cycle average of tags in use +system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.376712 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.521929 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021124 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021124 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits -system.cpu.dcache.overall_hits::total 2370 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits +system.cpu.dcache.overall_hits::total 2369 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses @@ -738,28 +738,28 @@ system.cpu.dcache.demand_miss_latency::cpu.data 23550000 system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency @@ -804,14 +804,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 25f28ceed..146a5ec3a 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:16:48 -gem5 started Jan 23 2013 15:16:55 +gem5 compiled Mar 26 2013 14:56:08 +gem5 started Mar 26 2013 14:56:29 gem5 executing on ribera.cs.wisc.edu command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 18578000 because target called exit() +Exiting @ tick 19339000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index d65cf38dc..54d30dc78 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 19339000 # Number of ticks simulated final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54855 # Simulator instruction rate (inst/s) -host_op_rate 54842 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 182382541 # Simulator tick rate (ticks/s) -host_mem_usage 224336 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 26477 # Simulator instruction rate (inst/s) +host_op_rate 26474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88053451 # Simulator tick rate (ticks/s) +host_mem_usage 270344 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -260,19 +260,19 @@ system.cpu.stage4.runCycles 2902 # Nu system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use -system.cpu.icache.total_refs 428 # Total number of references to valid blocks. +system.cpu.icache.total_refs 429 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.344828 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits -system.cpu.icache.overall_hits::total 428 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 429 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 429 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 429 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 429 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 429 # number of overall hits +system.cpu.icache.overall_hits::total 429 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses @@ -285,18 +285,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 18937500 system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 774 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 774 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 774 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.447028 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.447028 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.447028 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.447028 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.447028 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.447028 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 775 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 775 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 775 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.446452 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.446452 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.446452 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.446452 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.446452 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.446452 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency @@ -329,12 +329,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329000 system.cpu.icache.demand_mshr_miss_latency::total 17329000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 17329000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.412145 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.412145 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.412145 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.411613 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.411613 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.411613 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54322.884013 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54322.884013 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 9962046c6..97699de37 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -481,6 +481,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -513,6 +514,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -520,25 +522,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 3edf11a35..33a7977e7 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:16:48 -gem5 started Jan 23 2013 15:17:06 +gem5 compiled Mar 26 2013 14:56:08 +gem5 started Mar 26 2013 14:56:29 gem5 executing on ribera.cs.wisc.edu command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 16532500 because target called exit() +Exiting @ tick 17026500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 13fbe689c..c79016c7b 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17026500 # Number of ticks simulated final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44899 # Simulator instruction rate (inst/s) -host_op_rate 44889 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 148205995 # Simulator tick rate (ticks/s) -host_mem_usage 226388 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 19281 # Simulator instruction rate (inst/s) +host_op_rate 19280 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63663526 # Simulator tick rate (ticks/s) +host_mem_usage 270344 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2863000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests +system.physmem.totQLat 2843000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14596750 # Sum of mem lat for all requests system.physmem.totBusLat 2390000 # Total cycles spent in databus access system.physmem.totBankLat 9363750 # Total cycles spent in bank access -system.physmem.avgQLat 5989.54 # Average queueing delay per request +system.physmem.avgQLat 5947.70 # Average queueing delay per request system.physmem.avgBankLat 19589.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30578.97 # Average memory access latency +system.physmem.avgMemAccLat 30537.13 # Average memory access latency system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s @@ -170,13 +170,13 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 35495.82 # Average gap between requests -system.cpu.branchPred.lookups 2222 # Number of BP lookups -system.cpu.branchPred.condPredicted 1502 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2218 # Number of BP lookups +system.cpu.branchPred.condPredicted 1500 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1693 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1689 # Number of BTB lookups system.cpu.branchPred.BTBHits 508 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.005907 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 30.076969 # BTB Hit Percentage system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -202,47 +202,47 @@ system.cpu.numCycles 34054 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13389 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered +system.cpu.fetch.Insts 13373 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2218 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3272 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1401 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 3270 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1400 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14126 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.947827 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.258648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2012 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.946895 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.257314 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10854 76.84% 76.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1348 9.54% 86.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 105 0.74% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 135 0.96% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.16% 90.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.84% 91.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 156 1.10% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 160 1.13% 93.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 945 6.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10853 76.85% 76.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1348 9.54% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 105 0.74% 87.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 135 0.96% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.16% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 118 0.84% 91.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 156 1.10% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 160 1.13% 93.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 943 6.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14126 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065249 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.393170 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8860 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1239 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3094 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065132 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.392700 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8861 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1237 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3093 # Number of cycles decode is running system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 889 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 888 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12497 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12489 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 889 # Number of cycles rename is squashing +system.cpu.rename.SquashCycles 888 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 804 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 802 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2958 # Number of cycles rename is running system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename @@ -258,34 +258,34 @@ system.cpu.rename.UndoneMaps 3839 # Nu system.cpu.rename.serializingInsts 18 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2483 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1201 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2482 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1199 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9303 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8325 # Number of instructions issued +system.cpu.iq.iqInstsAdded 9295 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8318 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3645 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2172 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14126 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.589339 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.255776 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 3635 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.588968 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.255126 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10546 74.66% 74.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1398 9.90% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 898 6.36% 90.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 564 3.99% 94.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 360 2.55% 97.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 226 1.60% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10544 74.66% 74.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1399 9.91% 84.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 897 6.35% 90.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 565 4.00% 94.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 359 2.54% 97.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 225 1.59% 99.05% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14126 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14123 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available @@ -321,8 +321,8 @@ system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4947 59.42% 59.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4943 59.43% 59.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.49% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued @@ -350,72 +350,72 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2263 27.18% 86.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1106 13.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2262 27.19% 86.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8325 # Type of FU issued -system.cpu.iq.rate 0.244465 # Inst issue rate +system.cpu.iq.FU_type_0::total 8318 # Type of FU issued +system.cpu.iq.rate 0.244259 # Inst issue rate system.cpu.iq.fu_busy_cnt 159 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019099 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30977 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12971 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7469 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30960 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12952 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7465 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8482 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1319 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 276 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 274 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 889 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 888 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10864 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2483 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1201 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 10854 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2482 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1199 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 7932 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 389 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 386 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1547 # number of nop insts executed -system.cpu.iew.exec_refs 3203 # number of memory reference insts executed +system.cpu.iew.exec_nop 1546 # number of nop insts executed +system.cpu.iew.exec_refs 3202 # number of memory reference insts executed system.cpu.iew.exec_branches 1355 # Number of branches executed -system.cpu.iew.exec_stores 1078 # Number of stores executed -system.cpu.iew.exec_rate 0.233042 # Inst execution rate -system.cpu.iew.wb_sent 7560 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7471 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2950 # num instructions producing a value -system.cpu.iew.wb_consumers 4259 # num instructions consuming a value +system.cpu.iew.exec_stores 1077 # Number of stores executed +system.cpu.iew.exec_rate 0.232924 # Inst execution rate +system.cpu.iew.wb_sent 7556 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7467 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2949 # num instructions producing a value +system.cpu.iew.wb_consumers 4258 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.219387 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692651 # average fanout of values written-back +system.cpu.iew.wb_rate 0.219269 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692579 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5043 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5033 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13237 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.439148 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.223024 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.439214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.223104 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10853 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10851 81.99% 81.99% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle @@ -427,7 +427,7 @@ system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13237 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13235 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -440,10 +440,10 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23973 # The number of ROB reads -system.cpu.rob.rob_writes 22610 # The number of ROB writes -system.cpu.timesIdled 288 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23961 # The number of ROB reads +system.cpu.rob.rob_writes 22589 # The number of ROB writes +system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19931 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated @@ -451,56 +451,56 @@ system.cpu.cpi 6.604732 # CP system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10756 # number of integer regfile reads -system.cpu.int_regfile_writes 5239 # number of integer regfile writes +system.cpu.int_regfile_reads 10750 # number of integer regfile reads +system.cpu.int_regfile_writes 5236 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 150 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 162.249914 # Cycle average of tags in use +system.cpu.icache.tagsinuse 162.197466 # Cycle average of tags in use system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 162.249914 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079224 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079224 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 162.197466 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079198 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079198 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits system.cpu.icache.overall_hits::total 1566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses -system.cpu.icache.overall_misses::total 447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22381500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22381500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22381500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22381500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22381500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22381500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.222057 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.222057 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.222057 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.222057 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.222057 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.222057 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50070.469799 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50070.469799 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50070.469799 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50070.469799 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses +system.cpu.icache.overall_misses::total 446 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22343000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22343000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22343000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22343000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22343000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22343000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2012 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2012 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2012 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2012 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221670 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.221670 # 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number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -509,48 +509,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 6 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # 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Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.638337 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.788300 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005024 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006788 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 164.584950 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.776656 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005023 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006786 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -568,17 +568,17 @@ system.cpu.l2cache.demand_misses::total 478 # nu system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 478 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17452500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5919000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23371500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17438500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5913000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23351500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2657000 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8570000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26008500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 430 # number of ReadReq accesses(hits+misses) @@ -601,17 +601,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51941.964286 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65043.956044 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54734.192037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51900.297619 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64978.021978 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54687.353630 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52098.039216 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52098.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51941.964286 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60394.366197 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54452.928870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51941.964286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60394.366197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54452.928870 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51900.297619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60352.112676 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54411.087866 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51900.297619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60352.112676 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54411.087866 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,17 +631,17 @@ system.cpu.l2cache.demand_mshr_misses::total 478 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20109099 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273027 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836072 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20109099 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13259027 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6830321 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20089348 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13259027 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6830321 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20089348 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses @@ -653,27 +653,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.056548 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52791.692308 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.060890 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39461.389881 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52728.494505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42288.805621 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 91.642501 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 91.619831 # Cycle average of tags in use system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 91.642501 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022374 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022374 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 91.619831 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022368 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022368 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1852 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1852 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits @@ -690,14 +690,14 @@ system.cpu.dcache.demand_misses::cpu.data 501 # n system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses system.cpu.dcache.overall_misses::total 501 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9019500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9019500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8995500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8995500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 15098999 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 15098999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24118499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24118499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24118499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24118499 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24094499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24094499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24094499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24094499 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2000 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2000 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -714,14 +714,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.171282 system.cpu.dcache.demand_miss_rate::total 0.171282 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.171282 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.171282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60942.567568 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60942.567568 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60780.405405 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60780.405405 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42773.368272 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 42773.368272 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48140.716567 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48140.716567 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48092.812375 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48092.812375 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -746,14 +746,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6013500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6013500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6007500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6007500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8722499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8722499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8722499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8722499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8716499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8716499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8716499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8716499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -762,14 +762,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66082.417582 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66016.483516 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66016.483516 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 073ffb5b4..1aa882d35 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -480,6 +480,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -512,6 +513,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -519,25 +521,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 09e115be1..b6781a5c9 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:33:02 -gem5 started Jan 23 2013 15:33:08 +gem5 compiled Mar 26 2013 14:59:37 +gem5 started Mar 26 2013 14:59:57 gem5 executing on ribera.cs.wisc.edu command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 14065500 because target called exit() +Exiting @ tick 14724500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 69396a815..30ea78059 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu sim_ticks 14724500 # Number of ticks simulated final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62176 # Simulator instruction rate (inst/s) -host_op_rate 62167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158021685 # Simulator tick rate (ticks/s) -host_mem_usage 222660 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 11850 # Simulator instruction rate (inst/s) +host_op_rate 11850 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30123505 # Simulator tick rate (ticks/s) +host_mem_usage 266600 # Number of bytes of host memory used +host_seconds 0.49 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see @@ -201,7 +201,7 @@ system.cpu.workload.num_syscalls 9 # Nu system.cpu.numCycles 29450 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7445 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7448 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13075 # Number of instructions fetch has processed system.cpu.fetch.Branches 2226 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 797 # Number of branches that fetch has predicted taken @@ -210,26 +210,26 @@ system.cpu.fetch.SquashCycles 1279 # Nu system.cpu.fetch.BlockedCycles 1007 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.132231 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547600 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 11551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.131937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.547334 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9302 80.55% 80.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9305 80.56% 80.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 175 1.52% 82.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 174 1.51% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 174 1.51% 83.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 140 1.21% 84.79% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 227 1.97% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.14% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 132 1.14% 87.90% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 256 2.22% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 108 0.94% 91.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.93% 91.05% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1034 8.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 11551 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.075586 # Number of branch fetches per cycle system.cpu.fetch.rate 0.443973 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7511 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 7514 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1178 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2083 # Number of cycles decode is running system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking @@ -239,7 +239,7 @@ system.cpu.decode.BranchMispred 154 # Nu system.cpu.decode.DecodedInsts 11641 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 697 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7696 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle system.cpu.rename.BlockCycles 476 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1969 # Number of cycles rename is running @@ -267,23 +267,23 @@ system.cpu.iq.iqSquashedInstsIssued 171 # Nu system.cpu.iq.iqSquashedInstsExamined 4167 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3342 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11548 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.771302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.771102 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.501710 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8209 71.09% 71.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1071 9.27% 80.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 6.85% 87.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 496 4.30% 91.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 4.04% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 302 2.62% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8211 71.08% 71.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1072 9.28% 80.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 790 6.84% 87.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 498 4.31% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 4.03% 95.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 301 2.61% 98.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 134 1.16% 99.32% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 44 0.38% 99.70% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 35 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11551 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available @@ -356,9 +356,9 @@ system.cpu.iq.FU_type_0::total 8907 # Ty system.cpu.iq.rate 0.302445 # Inst issue rate system.cpu.iq.fu_busy_cnt 171 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019198 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29642 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 29645 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14405 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8122 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 8123 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses @@ -389,32 +389,32 @@ system.cpu.iew.memOrderViolationEvents 6 # Nu system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 329 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8492 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 8493 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1673 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 415 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3204 # number of memory reference insts executed system.cpu.iew.exec_branches 1349 # Number of branches executed system.cpu.iew.exec_stores 1531 # Number of stores executed -system.cpu.iew.exec_rate 0.288353 # Inst execution rate -system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8149 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.288387 # Inst execution rate +system.cpu.iew.wb_sent 8266 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8150 # cumulative count of insts written-back system.cpu.iew.wb_producers 4198 # num instructions producing a value system.cpu.iew.wb_consumers 6619 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.276706 # insts written-back per cycle +system.cpu.iew.wb_rate 0.276740 # insts written-back per cycle system.cpu.iew.wb_fanout 0.634235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4482 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10851 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.533776 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.333108 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.332953 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8471 78.07% 78.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 999 9.21% 87.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8474 78.07% 78.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 9.20% 87.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 620 5.71% 92.99% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 267 2.46% 95.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 174 1.60% 97.05% # Number of insts commited each cycle @@ -425,7 +425,7 @@ system.cpu.commit.committed_per_cycle::8 101 0.93% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -438,10 +438,10 @@ system.cpu.commit.int_insts 5698 # Nu system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21024 # The number of ROB reads +system.cpu.rob.rob_reads 21027 # The number of ROB reads system.cpu.rob.rob_writes 21246 # The number of ROB writes system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17902 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17899 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated @@ -449,8 +449,8 @@ system.cpu.cpi 5.084599 # CP system.cpu.cpi_total 5.084599 # CPI: Total CPI of All Threads system.cpu.ipc 0.196672 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.196672 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13466 # number of integer regfile reads -system.cpu.int_regfile_writes 7036 # number of integer regfile writes +system.cpu.int_regfile_reads 13468 # number of integer regfile reads +system.cpu.int_regfile_writes 7037 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements @@ -474,12 +474,12 @@ system.cpu.icache.demand_misses::cpu.inst 441 # n system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses system.cpu.icache.overall_misses::total 441 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21881500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21881500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21881500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21881500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21881500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21881500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21880000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21880000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21880000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21880000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21880000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21880000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1802 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1802 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1802 # number of demand (read+write) accesses @@ -492,12 +492,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.244728 system.cpu.icache.demand_miss_rate::total 0.244728 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.244728 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.244728 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49617.913832 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49617.913832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49617.913832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49617.913832 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49614.512472 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49614.512472 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49614.512472 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49614.512472 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -538,13 +538,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 198.145822 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 198.145720 # Cycle average of tags in use system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::cpu.inst 166.786167 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.359655 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.359554 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy @@ -569,16 +569,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 345 # system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17370000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3170500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20540500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3171000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20541000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2908000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2908000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 17370000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6078500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23448500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23449000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 17370000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6078500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23448500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6079000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23449000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -602,16 +602,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50347.826087 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58712.962963 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51479.949875 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58722.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51481.203008 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61872.340426 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61872.340426 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52575.112108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60188.118812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52576.233184 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52575.112108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60188.118812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52576.233184 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -666,12 +666,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.079208 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.324462 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 63.324326 # Cycle average of tags in use system.cpu.dcache.total_refs 2181 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 21.382353 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.324462 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 63.324326 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.015460 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.015460 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits @@ -690,14 +690,14 @@ system.cpu.dcache.demand_misses::cpu.data 438 # n system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses system.cpu.dcache.overall_misses::total 438 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5160500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5160500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5163000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5163000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 14813997 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 14813997 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19974497 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19974497 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19974497 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19974497 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19976997 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19976997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19976997 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19976997 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1573 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1573 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -714,14 +714,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.167239 system.cpu.dcache.demand_miss_rate::total 0.167239 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.167239 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.167239 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51094.059406 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51094.059406 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51118.811881 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51118.811881 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43958.448071 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 43958.448071 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45603.874429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45603.874429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45609.582192 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45609.582192 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 419 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -746,14 +746,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2957499 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2957499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6193499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6193499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6193999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6193999 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034965 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034965 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -762,14 +762,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038946 system.cpu.dcache.demand_mshr_miss_rate::total 0.038946 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038946 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58836.363636 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58836.363636 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58845.454545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58845.454545 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62925.510638 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62925.510638 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index 254e6c7c6..08313d557 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -179,6 +179,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -211,6 +212,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -221,6 +223,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 7978eda39..06a0491cb 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorde gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:01:02 +gem5 compiled Mar 26 2013 15:04:14 +gem5 started Mar 26 2013 15:04:37 gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 16286500 because target called exit() +Hello World!Exiting @ tick 16783500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index d53327dbb..91942b523 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16783500 # Number of ticks simulated final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48421 # Simulator instruction rate (inst/s) -host_op_rate 48416 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152524495 # Simulator tick rate (ticks/s) -host_mem_usage 230316 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 18770 # Simulator instruction rate (inst/s) +host_op_rate 18768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59128079 # Simulator tick rate (ticks/s) +host_mem_usage 276316 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2672750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12996500 # Sum of mem lat for all requests +system.physmem.totQLat 2671750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12995500 # Sum of mem lat for all requests system.physmem.totBusLat 2115000 # Total cycles spent in databus access system.physmem.totBankLat 8208750 # Total cycles spent in bank access -system.physmem.avgQLat 6318.56 # Average queueing delay per request +system.physmem.avgQLat 6316.19 # Average queueing delay per request system.physmem.avgBankLat 19406.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30724.59 # Average memory access latency +system.physmem.avgMemAccLat 30722.22 # Average memory access latency system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s @@ -202,7 +202,7 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed @@ -225,12 +225,12 @@ system.cpu.cpi_total 6.301483 # CP system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 28929 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.819709 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 30371 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.523951 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 28928 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 13.822688 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 30373 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.517993 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts). @@ -241,50 +241,50 @@ system.cpu.stage4.idleCycles 30411 # Nu system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 141.185042 # Cycle average of tags in use -system.cpu.icache.total_refs 895 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 141.184744 # Cycle average of tags in use +system.cpu.icache.total_refs 896 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 141.185042 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 141.184744 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 895 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 895 # number of overall hits -system.cpu.icache.overall_hits::total 895 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits +system.cpu.icache.overall_hits::total 896 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18996500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18996500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18996500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18996500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18996500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18996500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1257 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1257 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1257 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287987 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.287987 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.287987 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52476.519337 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52476.519337 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52476.519337 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52476.519337 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18997500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18997500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18997500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18997500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18997500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18997500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52479.281768 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52479.281768 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52479.281768 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52479.281768 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52479.281768 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52479.281768 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,32 +305,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15423000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15423000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15423000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15423000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15423000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15423000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15424000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15424000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15424000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15424000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15424000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15424000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53003.436426 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53003.436426 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53003.436426 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53003.436426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53003.436426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53003.436426 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 167.397215 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 167.396977 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.661002 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 140.660763 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 26.736213 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy @@ -355,16 +355,16 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15104500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3320000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15105500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3319000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 18424500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4710000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4710000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15104500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8030000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15105500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8029000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 23134500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15104500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8030000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15105500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8029000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 23134500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) @@ -388,16 +388,16 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52264.705882 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62641.509434 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52268.166090 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62622.641509 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 53872.807018 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58148.148148 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58148.148148 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52268.166090 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59917.910448 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 54691.489362 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52268.166090 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59917.910448 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 54691.489362 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -419,16 +419,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527228 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665291 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192519 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2664291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14191519 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719787 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719787 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527228 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385078 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17912306 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6384078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17911306 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527228 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385078 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17912306 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6384078 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17911306 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -441,16 +441,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39886.602076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50288.509434 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41498.593567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50269.641509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41495.669591 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.296296 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.296296 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47642.373134 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42343.513002 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47642.373134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42343.513002 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use @@ -477,14 +477,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3818500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3818500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3817500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3817500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 21812000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 21812000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25630500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25630500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25630500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25630500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25629500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25629500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25629500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25629500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -501,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62598.360656 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62598.360656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62581.967213 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62581.967213 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54072.784810 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54072.784810 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54070.675105 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54070.675105 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked @@ -533,14 +533,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3385500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3385500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8180000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8180000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8180000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8180000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8179000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8179000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8179000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8179000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -549,14 +549,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62712.962963 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.444444 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62694.444444 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 745f3a55b..6136a5e78 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 11 2013 13:21:48 -gem5 started Mar 11 2013 13:21:58 +gem5 compiled Mar 26 2013 15:13:59 +gem5 started Mar 26 2013 15:14:41 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 15471000 because target called exit() +Exiting @ tick 15474000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 50eb0a35f..63a2cacd2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15471000 # Number of ticks simulated -final_tick 15471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15474000 # Number of ticks simulated +final_tick 15474000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25126 # Simulator instruction rate (inst/s) -host_op_rate 45518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72243012 # Simulator tick rate (ticks/s) -host_mem_usage 287412 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 16433 # Simulator instruction rate (inst/s) +host_op_rate 29770 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47259450 # Simulator tick rate (ticks/s) +host_mem_usage 286708 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19392 # Nu system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory system.physmem.num_reads::total 449 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1253441924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 603968716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1857410639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1253441924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1253441924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1253441924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 603968716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1857410639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1253198914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 603851622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1857050536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1253198914 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1253198914 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1253198914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 603851622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1857050536 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 451 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15455000 # Total gap between requests +system.physmem.totGap 15458000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -157,9 +157,9 @@ system.physmem.avgQLat 4211.75 # Av system.physmem.avgBankLat 19969.51 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 29181.26 # Average memory access latency -system.physmem.avgRdBW 1857.41 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1857.05 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1857.41 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1857.05 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 14.51 # Data bus utilization in percentage @@ -169,104 +169,104 @@ system.physmem.readRowHits 333 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34268.29 # Average gap between requests -system.cpu.branchPred.lookups 2992 # Number of BP lookups -system.cpu.branchPred.condPredicted 2992 # Number of conditional branches predicted +system.physmem.avgGap 34274.94 # Average gap between requests +system.cpu.branchPred.lookups 2993 # Number of BP lookups +system.cpu.branchPred.condPredicted 2993 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2482 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 2483 # Number of BTB lookups system.cpu.branchPred.BTBHits 793 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.950040 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.937173 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 30943 # number of cpu cycles simulated +system.cpu.numCycles 30949 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8896 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2992 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 8903 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14396 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2993 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3908 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2410 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3707 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 3910 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2411 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3703 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1872 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 18558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.369490 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.871739 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1874 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 286 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 18564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.369856 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.872055 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 14749 79.48% 79.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 190 1.02% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 14753 79.47% 79.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 190 1.02% 80.49% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 153 0.82% 81.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 193 1.04% 82.36% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 163 0.88% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 168 0.91% 84.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.42% 85.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 160 0.86% 86.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2518 13.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 168 0.90% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.42% 85.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 161 0.87% 86.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2519 13.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 18558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.096694 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.464952 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9433 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 18564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.096707 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.465152 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9437 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 3646 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3518 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 144 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1817 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24275 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1817 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9777 # Number of cycles rename is idle +system.cpu.decode.RunCycles 3520 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 143 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1818 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24283 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1818 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9780 # Number of cycles rename is idle system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 497 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3304 # Number of cycles rename is running +system.cpu.rename.RunCycles 3306 # Number of cycles rename is running system.cpu.rename.UnblockCycles 765 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22769 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 22784 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 649 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24875 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 54688 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54672 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 651 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24893 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 54727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54711 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13812 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13830 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 34 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2061 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 2066 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2202 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1748 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20301 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 20310 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 36 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17266 # Number of instructions issued +system.cpu.iq.iqInstsIssued 17272 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 205 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9813 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13640 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 9822 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13657 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 18558 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.930380 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.788216 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 18564 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.930403 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.788380 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13171 70.97% 70.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1403 7.56% 78.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1055 5.68% 84.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 693 3.73% 87.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 728 3.92% 91.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 621 3.35% 95.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13176 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1404 7.56% 78.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1053 5.67% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 694 3.74% 87.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 727 3.92% 91.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 623 3.36% 95.22% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 594 3.20% 98.42% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 251 1.35% 99.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 18558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 18564 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 132 76.30% 76.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 76.30% # attempts to use FU when none available @@ -302,7 +302,7 @@ system.cpu.iq.fu_full::MemWrite 21 12.14% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13880 80.39% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13885 80.39% 80.41% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.41% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.41% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.41% # Type of FU issued @@ -331,21 +331,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.41% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.41% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.41% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1903 11.02% 91.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1904 11.02% 91.43% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1480 8.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17266 # Type of FU issued -system.cpu.iq.rate 0.557994 # Inst issue rate +system.cpu.iq.FU_type_0::total 17272 # Type of FU issued +system.cpu.iq.rate 0.558079 # Inst issue rate system.cpu.iq.fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010020 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53460 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30157 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15915 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010016 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53478 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30175 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15918 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17432 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17438 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 159 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -358,10 +358,10 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1817 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1818 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20337 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 20346 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2202 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1748 # Number of dispatched store instructions @@ -372,43 +372,43 @@ system.cpu.iew.memOrderViolationEvents 12 # Nu system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 606 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 662 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16344 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 16347 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1780 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 922 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 925 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3142 # number of memory reference insts executed +system.cpu.iew.exec_refs 3143 # number of memory reference insts executed system.cpu.iew.exec_branches 1619 # Number of branches executed -system.cpu.iew.exec_stores 1362 # Number of stores executed -system.cpu.iew.exec_rate 0.528197 # Inst execution rate -system.cpu.iew.wb_sent 16113 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15919 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10115 # num instructions producing a value -system.cpu.iew.wb_consumers 15622 # num instructions consuming a value +system.cpu.iew.exec_stores 1363 # Number of stores executed +system.cpu.iew.exec_rate 0.528192 # Inst execution rate +system.cpu.iew.wb_sent 16117 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15922 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10116 # num instructions producing a value +system.cpu.iew.wb_consumers 15624 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.514462 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.647484 # average fanout of values written-back +system.cpu.iew.wb_rate 0.514459 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.647465 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10589 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 572 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 16741 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.582223 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.458057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 16746 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.582049 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.457997 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13206 78.88% 78.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13211 78.89% 78.89% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1328 7.93% 86.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 594 3.55% 90.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 704 4.21% 94.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 595 3.55% 90.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 703 4.20% 94.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 355 2.12% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 141 0.84% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 118 0.70% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 140 0.84% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 119 0.71% 98.24% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 74 0.44% 98.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 16741 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 16746 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -421,67 +421,67 @@ system.cpu.commit.int_insts 9654 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36856 # The number of ROB reads -system.cpu.rob.rob_writes 42518 # The number of ROB writes +system.cpu.rob.rob_reads 36870 # The number of ROB reads +system.cpu.rob.rob_writes 42537 # The number of ROB writes system.cpu.timesIdled 155 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 5.751487 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.751487 # CPI: Total CPI of All Threads -system.cpu.ipc 0.173868 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.173868 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28772 # number of integer regfile reads -system.cpu.int_regfile_writes 17143 # number of integer regfile writes +system.cpu.cpi 5.752602 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.752602 # CPI: Total CPI of All Threads +system.cpu.ipc 0.173834 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.173834 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28776 # number of integer regfile reads +system.cpu.int_regfile_writes 17146 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7129 # number of misc regfile reads +system.cpu.misc_regfile_reads 7131 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.801510 # Cycle average of tags in use -system.cpu.icache.total_refs 1474 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.810143 # Cycle average of tags in use +system.cpu.icache.total_refs 1475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.848684 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.851974 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 144.801510 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070704 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070704 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1474 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1474 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1474 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1474 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1474 # number of overall hits -system.cpu.icache.overall_hits::total 1474 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses -system.cpu.icache.overall_misses::total 398 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20575500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20575500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20575500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20575500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20575500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20575500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1872 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1872 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1872 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1872 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212607 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.212607 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.212607 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.212607 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.212607 # 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number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1475 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1475 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1475 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1475 # number of overall hits +system.cpu.icache.overall_hits::total 1475 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses +system.cpu.icache.overall_misses::total 399 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20615000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20615000 # 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mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53149.671053 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53149.671053 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53149.671053 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53149.671053 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53149.671053 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53149.671053 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 177.956413 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 177.966730 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.938671 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.017743 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 144.947246 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.019484 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004423 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005431 # Average percentage of cache occupancy @@ -549,17 +549,17 @@ system.cpu.l2cache.demand_misses::total 451 # nu system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses system.cpu.l2cache.overall_misses::total 451 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15842000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15842500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3892500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19734500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19735000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3990500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3990500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15842000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15842500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23725000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15842000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 23725500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15842500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23725000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23725500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 72 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses) @@ -582,17 +582,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997788 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # 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average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52605.321508 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52606.430155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52285.478548 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52605.321508 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52606.430155 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,14 +615,14 @@ system.cpu.l2cache.overall_mshr_misses::total 451 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12091981 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030041 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122022 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058056 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058056 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3057807 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3057807 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12091981 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088097 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18180078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6087848 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18179829 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12091981 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088097 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18180078 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6087848 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18179829 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses @@ -637,24 +637,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40237.578947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40237.578947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40234.302632 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40234.302632 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41134.108108 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.042129 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41134.108108 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.042129 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.486269 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.491215 # Cycle average of tags in use system.cpu.dcache.total_refs 2285 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 15.650685 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.486269 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020382 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020382 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.491215 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020384 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020384 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits |