diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/quick/se/00.hello | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/quick/se/00.hello')
24 files changed, 4827 insertions, 4059 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index a38dae954..35c6d79b2 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19476000 # Number of ticks simulated -final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 24560000 # Number of ticks simulated +final_tick 24560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1322 # Simulator instruction rate (inst/s) -host_op_rate 1322 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4028719 # Simulator tick rate (ticks/s) -host_mem_usage 223696 # Number of bytes of host memory used -host_seconds 4.83 # Real time elapsed on the host +host_inst_rate 1785 # Simulator instruction rate (inst/s) +host_op_rate 1785 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6860090 # Simulator tick rate (ticks/s) +host_mem_usage 225432 # Number of bytes of host memory used +host_seconds 3.58 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 985828712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 552064079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1537892791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 985828712 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 985828712 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 985828712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 552064079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1537892791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 781758958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 437785016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1219543974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 781758958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 781758958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 781758958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 437785016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1219543974 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 29952 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 47 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19461500 # Total gap between requests +system.physmem.totGap 24545500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,9 +85,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -149,27 +149,62 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2627750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13374000 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 67 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 285.611940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 145.316634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 484.514157 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 33 49.25% 49.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 11.94% 61.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 7.46% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 7.46% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 5.97% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 4.48% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.49% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.49% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.49% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.49% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 1.49% 94.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.49% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation +system.physmem.totQLat 1607750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11529000 # Sum of mem lat for all requests system.physmem.totBusLat 2345000 # Total cycles spent in databus access -system.physmem.totBankLat 8401250 # Total cycles spent in bank access -system.physmem.avgQLat 5602.88 # Average queueing delay per request -system.physmem.avgBankLat 17913.11 # Average bank access latency per request +system.physmem.totBankLat 7576250 # Total cycles spent in bank access +system.physmem.avgQLat 3428.04 # Average queueing delay per request +system.physmem.avgBankLat 16154.05 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28515.99 # Average memory access latency -system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24582.09 # Average memory access latency +system.physmem.avgRdBW 1219.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1219.54 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.69 # Average read queue length over time +system.physmem.busUtil 9.53 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.47 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 377 # Number of row buffer hits during reads +system.physmem.readRowHits 402 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41495.74 # Average gap between requests +system.physmem.avgGap 52335.82 # Average gap between requests +system.membus.throughput 1219543974 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 396 # Transaction distribution +system.membus.trans_dist::ReadResp 395 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 937 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 937 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 29952 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 563500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 4381500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.8 # Layer utilization (%) system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -183,18 +218,18 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_hits 1184 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 866 # DTB write hits +system.cpu.dtb.read_accesses 1191 # DTB read accesses +system.cpu.dtb.write_hits 893 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 869 # DTB write accesses -system.cpu.dtb.data_hits 2049 # DTB hits +system.cpu.dtb.write_accesses 896 # DTB write accesses +system.cpu.dtb.data_hits 2077 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2059 # DTB accesses +system.cpu.dtb.data_accesses 2087 # DTB accesses system.cpu.itb.fetch_hits 915 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -212,18 +247,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 38953 # number of cpu cycles simulated +system.cpu.numCycles 49121 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5201 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5174 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9768 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9741 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2949 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 2976 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2152 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken). @@ -234,12 +269,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11658 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 503 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31578 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7375 # Number of cycles cpu stages are processed. -system.cpu.activity 18.933073 # Percentage of cycles cpu is active +system.cpu.timesIdled 510 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41745 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7376 # Number of cycles cpu stages are processed. +system.cpu.activity 15.015981 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -251,36 +286,36 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 6.095931 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.687167 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.095931 # CPI: Total CPI of All Threads -system.cpu.ipc 0.164044 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.687167 # CPI: Total CPI of All Threads +system.cpu.ipc 0.130087 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.164044 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34029 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.130087 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 44197 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.640875 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 35060 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 10.024226 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45228 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.994095 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34792 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.925327 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44960 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 10.682104 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 37647 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1306 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.352758 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 34441 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4512 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 11.583190 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.utilization 8.470919 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47787 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.715743 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 44663 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 9.075548 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 142.957443 # Cycle average of tags in use +system.cpu.icache.tagsinuse 140.779037 # Cycle average of tags in use system.cpu.icache.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 142.957443 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069803 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069803 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 140.779037 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.068740 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.068740 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -293,12 +328,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18504000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18504000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18504000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18504000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18504000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18504000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24103000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24103000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24103000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24103000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24103000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24103000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -311,17 +346,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52123.943662 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52123.943662 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52123.943662 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52123.943662 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67895.774648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67895.774648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67895.774648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67895.774648 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 88 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -337,36 +372,55 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15862500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15862500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15862500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15862500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15862500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15862500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20462500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20462500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20462500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20462500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20462500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20462500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52524.834437 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52524.834437 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67756.622517 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67756.622517 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1222149837 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 939 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 30016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 451500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 199.973821 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 197.103662 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 143.049595 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.924226 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 140.828803 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.274859 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006015 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -384,17 +438,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5344500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20888500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3558500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3558500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15544000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8903000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24447000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15544000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8903000 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31954000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -417,17 +471,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51641.196013 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56257.894737 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52748.737374 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48746.575342 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48746.575342 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52125.799574 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52125.799574 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66923.588040 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72973.684211 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68375 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66815.068493 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66815.068493 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68132.196162 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68132.196162 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,17 +501,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177308 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993558 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666299 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666299 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843607 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18659857 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843607 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18659857 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16417750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5764000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22181750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16417750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9750750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26168500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16417750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9750750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26168500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -469,27 +523,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39256.644518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43971.663158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40387.772727 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36524.643836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36524.643836 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54544.019934 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60673.684211 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56014.520202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.747723 # Cycle average of tags in use system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 104.433203 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025496 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025496 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.747723 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025085 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025085 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -506,14 +560,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5722500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5722500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15380500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15380500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21103000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21103000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21103000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21103000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7336500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7336500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21108000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21108000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28444500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28444500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28444500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28444500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -530,19 +584,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58994.845361 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58994.845361 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43944.285714 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43944.285714 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47210.290828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47210.290828 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 178 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75634.020619 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75634.020619 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60308.571429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60308.571429 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63634.228188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63634.228188 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -562,14 +616,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5446000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3636000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3636000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9082000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9082000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7034000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7034000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4955000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4955000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11989000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11989000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11989000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11989000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -578,14 +632,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57326.315789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57326.315789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49808.219178 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49808.219178 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74042.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74042.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67876.712329 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67876.712329 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 1a9d50ed7..9e4861fce 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16032500 # Number of ticks simulated -final_tick 16032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 20632000 # Number of ticks simulated +final_tick 20632000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34765 # Simulator instruction rate (inst/s) -host_op_rate 34761 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87452252 # Simulator tick rate (ticks/s) -host_mem_usage 269696 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 1782 # Simulator instruction rate (inst/s) +host_op_rate 1782 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5769044 # Simulator tick rate (ticks/s) +host_mem_usage 227476 # Number of bytes of host memory used +host_seconds 3.58 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory -system.physmem.bytes_read::total 31104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 31168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1245470139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 694589116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1940059255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1245470139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1245470139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1245470139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 694589116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1940059255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 486 # Total number of read requests seen +system.physmem.num_reads::total 487 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 970918961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 539744087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1510663048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 970918961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 970918961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 970918961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 539744087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1510663048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 488 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 31104 # Total number of bytes read from memory +system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 31168 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 47 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15819000 # Total gap between requests +system.physmem.totGap 20599000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 486 # Categorize read packet sizes +system.physmem.readPktSize::6 488 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,56 +149,90 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2907500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13642500 # Sum of mem lat for all requests -system.physmem.totBusLat 2430000 # Total cycles spent in databus access -system.physmem.totBankLat 8305000 # Total cycles spent in bank access -system.physmem.avgQLat 5982.51 # Average queueing delay per request -system.physmem.avgBankLat 17088.48 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation +system.physmem.totQLat 2633750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12636250 # Sum of mem lat for all requests +system.physmem.totBusLat 2440000 # Total cycles spent in databus access +system.physmem.totBankLat 7562500 # Total cycles spent in bank access +system.physmem.avgQLat 5397.03 # Average queueing delay per request +system.physmem.avgBankLat 15496.93 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28070.99 # Average memory access latency -system.physmem.avgRdBW 1940.06 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25893.95 # Average memory access latency +system.physmem.avgRdBW 1510.66 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1940.06 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1510.66 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.85 # Average read queue length over time +system.physmem.busUtil 11.80 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.61 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 396 # Number of row buffer hits during reads +system.physmem.readRowHits 419 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32549.38 # Average gap between requests -system.cpu.branchPred.lookups 2896 # Number of BP lookups -system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups -system.cpu.branchPred.BTBHits 746 # Number of BTB hits +system.physmem.avgGap 42211.07 # Average gap between requests +system.membus.throughput 1510663048 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 415 # Transaction distribution +system.membus.trans_dist::ReadResp 414 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 975 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 31168 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 600000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) +system.cpu.branchPred.lookups 2906 # Number of BP lookups +system.cpu.branchPred.condPredicted 1709 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2211 # Number of BTB lookups +system.cpu.branchPred.BTBHits 759 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.909091 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.328358 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2071 # DTB read hits -system.cpu.dtb.read_misses 50 # DTB read misses +system.cpu.dtb.read_hits 2097 # DTB read hits +system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2121 # DTB read accesses -system.cpu.dtb.write_hits 1069 # DTB write hits -system.cpu.dtb.write_misses 30 # DTB write misses +system.cpu.dtb.read_accesses 2144 # DTB read accesses +system.cpu.dtb.write_hits 1063 # DTB write hits +system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1099 # DTB write accesses -system.cpu.dtb.data_hits 3140 # DTB hits -system.cpu.dtb.data_misses 80 # DTB misses +system.cpu.dtb.write_accesses 1094 # DTB write accesses +system.cpu.dtb.data_hits 3160 # DTB hits +system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3220 # DTB accesses -system.cpu.itb.fetch_hits 2349 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 3238 # DTB accesses +system.cpu.itb.fetch_hits 2393 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2387 # ITB accesses +system.cpu.itb.fetch_accesses 2432 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -212,236 +246,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 32066 # number of cpu cycles simulated +system.cpu.numCycles 41265 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8354 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1883 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1142 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.138929 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.535970 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8511 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16675 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2906 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2982 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1908 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1525 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 759 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2393 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 379 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.103793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.501598 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11560 79.66% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 185 1.27% 91.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12125 80.26% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 320 2.12% 82.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 215 1.42% 85.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 256 1.69% 87.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 241 1.60% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 187 1.24% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1265 8.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090314 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.515406 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9311 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2752 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15357 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9520 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2630 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14673 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 15107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.070423 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.404095 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9355 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1672 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2793 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1224 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 15419 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1224 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9566 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 693 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 555 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2621 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 448 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14692 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11018 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18307 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18290 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 388 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 11020 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18321 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18304 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6448 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6450 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2761 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 976 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2777 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1360 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13018 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10806 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14511 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.744676 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.388965 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12985 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10814 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6280 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 15107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.715827 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10031 69.13% 69.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1602 11.04% 80.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 759 5.23% 93.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 471 3.25% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10552 69.85% 69.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1715 11.35% 81.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1107 7.33% 88.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 773 5.12% 93.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 494 3.27% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 269 1.78% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 148 0.98% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 35 0.23% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14511 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15107 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 63 53.39% 66.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 33.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 14 12.61% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 59 53.15% 65.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 34.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7299 67.55% 67.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2362 21.86% 89.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7260 67.14% 67.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2415 22.33% 89.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1134 10.49% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10806 # Type of FU issued -system.cpu.iq.rate 0.336992 # Inst issue rate -system.cpu.iq.fu_busy_cnt 118 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36270 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9699 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10814 # Type of FU issued +system.cpu.iq.rate 0.262062 # Inst issue rate +system.cpu.iq.fu_busy_cnt 111 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010264 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36878 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19300 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9631 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10911 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10912 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1578 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1594 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 495 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 87 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 136 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1212 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 147 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1224 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 218 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13104 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2777 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1360 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10153 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 653 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 509 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10116 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2155 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 698 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 86 # number of nop insts executed -system.cpu.iew.exec_refs 3233 # number of memory reference insts executed -system.cpu.iew.exec_branches 1613 # Number of branches executed -system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.316628 # Inst execution rate -system.cpu.iew.wb_sent 9856 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9709 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5133 # num instructions producing a value -system.cpu.iew.wb_consumers 6918 # num instructions consuming a value +system.cpu.iew.exec_nop 89 # number of nop insts executed +system.cpu.iew.exec_refs 3251 # number of memory reference insts executed +system.cpu.iew.exec_branches 1595 # Number of branches executed +system.cpu.iew.exec_stores 1096 # Number of stores executed +system.cpu.iew.exec_rate 0.245147 # Inst execution rate +system.cpu.iew.wb_sent 9787 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9641 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5053 # num instructions producing a value +system.cpu.iew.wb_consumers 6805 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.302782 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.741977 # average fanout of values written-back +system.cpu.iew.wb_rate 0.233636 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742542 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6713 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.480412 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.303409 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.460203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.266435 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10550 79.33% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 514 3.86% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 101 0.76% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11056 79.64% 79.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1544 11.12% 90.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 511 3.68% 94.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 249 1.79% 96.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 151 1.09% 97.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 81 0.58% 97.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 113 0.81% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.25% 98.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13883 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -452,70 +487,89 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25930 # The number of ROB reads -system.cpu.rob.rob_writes 27481 # The number of ROB writes -system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26491 # The number of ROB reads +system.cpu.rob.rob_writes 27437 # The number of ROB writes +system.cpu.timesIdled 274 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26158 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 5.032329 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.032329 # CPI: Total CPI of All Threads -system.cpu.ipc 0.198715 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.198715 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12887 # number of integer regfile reads -system.cpu.int_regfile_writes 7342 # number of integer regfile writes +system.cpu.cpi 6.475989 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.475989 # CPI: Total CPI of All Threads +system.cpu.ipc 0.154417 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.154417 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12831 # number of integer regfile reads +system.cpu.int_regfile_writes 7294 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.toL2Bus.throughput 1513765025 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 977 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 261000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.192462 # Cycle average of tags in use -system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.617277 # Cycle average of tags in use +system.cpu.icache.total_refs 1903 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.060510 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 159.192462 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1869 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1869 # number of overall hits -system.cpu.icache.overall_hits::total 1869 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses -system.cpu.icache.overall_misses::total 480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22201500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22201500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22201500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22201500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22201500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22201500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2349 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69952.054795 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67057.324841 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75537.356322 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70080.942623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67057.324841 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75537.356322 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70080.942623 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,124 +689,124 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40229.047325 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.644231 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40229.047325 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54695.859873 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67341.584158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57773.493976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57698.630137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57698.630137 # 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number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses -system.cpu.dcache.overall_misses::total 528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9128000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15893487 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15893487 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25021487 # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47389.179924 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 862 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.190631 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.190631 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.190631 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.190631 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68814.705882 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68814.705882 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60511.080780 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60511.080780 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63179.542533 # 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number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3763500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9952500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9952500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052468 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052468 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8145500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8145500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5182500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5182500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13328000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13328000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13328000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13328000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052880 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052880 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062366 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062366 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61277.227723 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61277.227723 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062703 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062703 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80648.514851 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80648.514851 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70993.150685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70993.150685 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 4cd56283e..469297f21 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3208000 # Number of ticks simulated final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84722 # Simulator instruction rate (inst/s) -host_op_rate 84702 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42507676 # Simulator tick rate (ticks/s) -host_mem_usage 261184 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 2502 # Simulator instruction rate (inst/s) +host_op_rate 2502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1255935 # Simulator tick rate (ticks/s) +host_mem_usage 215792 # Number of bytes of host memory used +host_seconds 2.55 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 2087281796 # Wr system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 12806733167 # Throughput (bytes/s) +system.membus.data_through_bus 41084 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index afd21634e..ece7545ec 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu sim_ticks 32544000 # Number of ticks simulated final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97330 # Simulator instruction rate (inst/s) -host_op_rate 97300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 495402774 # Simulator tick rate (ticks/s) -host_mem_usage 269640 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 19861 # Simulator instruction rate (inst/s) +host_op_rate 19860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101141711 # Simulator tick rate (ticks/s) +host_mem_usage 224276 # Number of bytes of host memory used +host_seconds 0.32 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 546705998 # In system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 877089479 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 373 # Transaction distribution +system.membus.trans_dist::ReadResp 373 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 892 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 28544 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.3 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -383,5 +398,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 558 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 28608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d97241466..efc4a5915 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9350000 # Number of ticks simulated -final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11848000 # Number of ticks simulated +final_tick 11848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 14656 # Simulator instruction rate (inst/s) -host_op_rate 14654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57391857 # Simulator tick rate (ticks/s) -host_mem_usage 269408 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 800 # Simulator instruction rate (inst/s) +host_op_rate 800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3968846 # Simulator tick rate (ticks/s) +host_mem_usage 226160 # Number of bytes of host memory used +host_seconds 2.99 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1280000000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 581818182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1861818182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1280000000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1280000000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1280000000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 581818182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1861818182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1010128292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459149223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1469277515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1010128292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1010128292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1010128292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459149223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1469277515 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 17408 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 9280500 # Total gap between requests +system.physmem.totGap 11758500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,56 +149,86 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 1327750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7871500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 33 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 277.333333 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.700631 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 448.761258 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 20 60.61% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 1 3.03% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 2 6.06% 69.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 1 3.03% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 6.06% 78.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 3.03% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 6.06% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 6.06% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation +system.physmem.totQLat 1380750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6920750 # Sum of mem lat for all requests system.physmem.totBusLat 1360000 # Total cycles spent in databus access -system.physmem.totBankLat 5183750 # Total cycles spent in bank access -system.physmem.avgQLat 4881.43 # Average queueing delay per request -system.physmem.avgBankLat 19057.90 # Average bank access latency per request +system.physmem.totBankLat 4180000 # Total cycles spent in bank access +system.physmem.avgQLat 5076.29 # Average queueing delay per request +system.physmem.avgBankLat 15367.65 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28939.34 # Average memory access latency -system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25443.93 # Average memory access latency +system.physmem.avgRdBW 1469.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1469.28 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 14.55 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.84 # Average read queue length over time +system.physmem.busUtil 11.48 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.58 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 207 # Number of row buffer hits during reads +system.physmem.readRowHits 239 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34119.49 # Average gap between requests -system.cpu.branchPred.lookups 1154 # Number of BP lookups -system.cpu.branchPred.condPredicted 581 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect +system.physmem.avgGap 43229.78 # Average gap between requests +system.membus.throughput 1469277515 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 248 # Transaction distribution +system.membus.trans_dist::ReadResp 248 # Transaction distribution +system.membus.trans_dist::ReadExReq 24 # Transaction distribution +system.membus.trans_dist::ReadExResp 24 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 544 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17408 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2542750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu.branchPred.lookups 1157 # Number of BP lookups +system.cpu.branchPred.condPredicted 604 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 257 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 791 # Number of BTB lookups -system.cpu.branchPred.BTBHits 226 # Number of BTB hits +system.cpu.branchPred.BTBHits 240 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 28.571429 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 30.341340 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 708 # DTB read hits +system.cpu.dtb.read_hits 704 # DTB read hits system.cpu.dtb.read_misses 28 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 736 # DTB read accesses -system.cpu.dtb.write_hits 357 # DTB write hits -system.cpu.dtb.write_misses 20 # DTB write misses +system.cpu.dtb.read_accesses 732 # DTB read accesses +system.cpu.dtb.write_hits 354 # DTB write hits +system.cpu.dtb.write_misses 19 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 377 # DTB write accesses -system.cpu.dtb.data_hits 1065 # DTB hits -system.cpu.dtb.data_misses 48 # DTB misses +system.cpu.dtb.write_accesses 373 # DTB write accesses +system.cpu.dtb.data_hits 1058 # DTB hits +system.cpu.dtb.data_misses 47 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1113 # DTB accesses -system.cpu.itb.fetch_hits 1043 # ITB hits +system.cpu.dtb.data_accesses 1105 # DTB accesses +system.cpu.itb.fetch_hits 1045 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1073 # ITB accesses +system.cpu.itb.fetch_accesses 1075 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -212,237 +242,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 18701 # number of cpu cycles simulated +system.cpu.numCycles 23697 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4191 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6947 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1154 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 450 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1194 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 306 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4326 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6897 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1157 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 858 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 471 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1024 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1121 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1043 # Number of cache lines fetched +system.cpu.fetch.CacheLines 1045 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7322 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.948784 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.362451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.895714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.301681 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6128 83.69% 83.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 54 0.74% 84.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 114 1.56% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 92 1.26% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 168 2.29% 89.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 73 1.00% 90.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.87% 91.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.87% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 565 7.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6510 84.55% 84.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52 0.68% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 117 1.52% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91 1.18% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 172 2.23% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 75 0.97% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 61 0.79% 91.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 67 0.87% 92.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 555 7.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7322 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.061708 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.371477 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5334 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 332 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1148 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 500 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.048825 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.291049 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5567 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 499 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1144 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 485 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 163 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6173 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 500 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5434 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 109 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 186 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1056 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 37 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5903 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4293 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6642 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6630 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 6120 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 485 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5671 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1044 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 32 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5812 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4232 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6563 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6551 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2525 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2464 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 133 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 964 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 466 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5010 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 948 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 455 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4912 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4065 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2458 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1421 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4000 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2288 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1369 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7322 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.555176 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.266886 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.519481 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.232756 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5697 77.81% 77.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 561 7.66% 85.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 397 5.42% 90.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 261 3.56% 94.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 207 2.83% 97.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 126 1.72% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 50 0.68% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15 0.20% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6104 79.27% 79.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 546 7.09% 86.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 391 5.08% 91.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 259 3.36% 94.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 207 2.69% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 122 1.58% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48 0.62% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15 0.19% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7322 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7700 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 4.35% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21 45.65% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.55% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19 43.18% 47.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2890 71.09% 71.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 787 19.36% 90.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 387 9.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2840 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 778 19.45% 90.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 381 9.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4065 # Type of FU issued -system.cpu.iq.rate 0.217368 # Inst issue rate -system.cpu.iq.fu_busy_cnt 46 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011316 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15538 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7472 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3658 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4000 # Type of FU issued +system.cpu.iq.rate 0.168798 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011000 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15794 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7204 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3598 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4104 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4037 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 549 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 533 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 172 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 161 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 500 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 100 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5355 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 129 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 964 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 466 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 485 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 153 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5240 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 948 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 455 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 159 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3852 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 737 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 213 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 212 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3798 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 733 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 202 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 339 # number of nop insts executed -system.cpu.iew.exec_refs 1114 # number of memory reference insts executed -system.cpu.iew.exec_branches 649 # Number of branches executed -system.cpu.iew.exec_stores 377 # Number of stores executed -system.cpu.iew.exec_rate 0.205978 # Inst execution rate -system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3664 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1729 # num instructions producing a value -system.cpu.iew.wb_consumers 2228 # num instructions consuming a value +system.cpu.iew.exec_nop 322 # number of nop insts executed +system.cpu.iew.exec_refs 1106 # number of memory reference insts executed +system.cpu.iew.exec_branches 638 # Number of branches executed +system.cpu.iew.exec_stores 373 # Number of stores executed +system.cpu.iew.exec_rate 0.160273 # Inst execution rate +system.cpu.iew.wb_sent 3682 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3604 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1694 # num instructions producing a value +system.cpu.iew.wb_consumers 2179 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.195925 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.776032 # average fanout of values written-back +system.cpu.iew.wb_rate 0.152087 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.777421 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2758 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2655 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6822 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.377602 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.238659 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 7215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.357034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.202430 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5958 87.34% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 201 2.95% 90.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 310 4.54% 94.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 116 1.70% 96.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 63 0.92% 97.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 50 0.73% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.47% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23 0.34% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6348 87.98% 87.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 203 2.81% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 309 4.28% 95.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 113 1.57% 96.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 69 0.96% 97.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 52 0.72% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.46% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22 0.30% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 66 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6822 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7215 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -453,119 +484,138 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 66 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11840 # The number of ROB reads -system.cpu.rob.rob_writes 11181 # The number of ROB writes -system.cpu.timesIdled 163 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11379 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 12133 # The number of ROB reads +system.cpu.rob.rob_writes 10960 # The number of ROB writes +system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15997 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 7.834520 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.834520 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127640 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127640 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4649 # number of integer regfile reads -system.cpu.int_regfile_writes 2842 # number of integer regfile writes +system.cpu.cpi 9.927524 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.927524 # CPI: Total CPI of All Threads +system.cpu.ipc 0.100730 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.100730 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4598 # number of integer regfile reads +system.cpu.int_regfile_writes 2789 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.toL2Bus.throughput 1469277515 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 17408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 17408 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 90.926534 # Cycle average of tags in use -system.cpu.icache.total_refs 794 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 91.300481 # Cycle average of tags in use +system.cpu.icache.total_refs 795 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.245989 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.251337 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 90.926534 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.044398 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.044398 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 794 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 794 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 794 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 794 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 794 # number of overall hits -system.cpu.icache.overall_hits::total 794 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses -system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12418499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12418499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12418499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12418499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12418499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12418499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1043 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1043 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1043 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1043 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.238734 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.238734 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.238734 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.238734 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.238734 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.238734 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.489960 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49873.489960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.489960 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49873.489960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.489960 # 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average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use -system.cpu.dcache.total_refs 763 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 44.834743 # Cycle average of tags in use +system.cpu.dcache.total_refs 761 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.976471 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.952941 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 44.507812 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.010866 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.010866 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 550 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 550 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 44.834743 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.010946 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.010946 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 548 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 548 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 763 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 763 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 763 # number of overall hits -system.cpu.dcache.overall_hits::total 763 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 761 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 761 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 761 # number of overall hits +system.cpu.dcache.overall_hits::total 761 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 109 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 109 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses -system.cpu.dcache.overall_misses::total 193 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5526500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5526500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4429500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4429500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9956000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9956000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9956000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9956000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 662 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 662 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses +system.cpu.dcache.overall_misses::total 190 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7852000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7852000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5307500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5307500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13159500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13159500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13159500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13159500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 657 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 657 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 956 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 956 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 956 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 956 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169184 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169184 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 951 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 951 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 951 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 951 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.165906 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.165906 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.201883 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.201883 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.201883 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.201883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49343.750000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49343.750000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54685.185185 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54685.185185 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51585.492228 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51585.492228 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.199790 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.199790 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.199790 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.199790 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72036.697248 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72036.697248 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65524.691358 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65524.691358 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69260.526316 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69260.526316 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69260.526316 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69260.526316 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 144 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 48 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 108 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 108 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 105 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 105 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 105 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -755,30 +805,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3648500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3648500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1433500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1433500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5082000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5082000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092145 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092145 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4662500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4662500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6402000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6402000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6402000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6402000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092846 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092846 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.088912 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.088912 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59811.475410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59811.475410 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089380 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.089380 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089380 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.089380 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76434.426230 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76434.426230 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72479.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72479.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75317.647059 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75317.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75317.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75317.647059 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 70ee5a4ad..aec79b975 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34130 # Simulator instruction rate (inst/s) -host_op_rate 34121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17175609 # Simulator tick rate (ticks/s) -host_mem_usage 260900 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 388869 # Simulator instruction rate (inst/s) +host_op_rate 388153 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 195100518 # Simulator tick rate (ticks/s) +host_mem_usage 215488 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1586127168 # Wr system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11879768786 # Throughput (bytes/s) +system.membus.data_through_bus 15414 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 005a80d9b..cb629b252 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 14244 # Simulator instruction rate (inst/s) -host_op_rate 14243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91318433 # Simulator tick rate (ticks/s) -host_mem_usage 268332 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 252355 # Simulator instruction rate (inst/s) +host_op_rate 251860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1611932908 # Simulator tick rate (ticks/s) +host_mem_usage 223992 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 631324135 # In system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 948922779 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 218 # Transaction distribution +system.membus.trans_dist::ReadResp 218 # Transaction distribution +system.membus.trans_dist::ReadExReq 27 # Transaction distribution +system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 490 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15680 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 13.3 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -377,5 +392,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 948922779 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 10432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 8dbb84df8..6938f2714 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13706000 # Number of ticks simulated -final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16387000 # Number of ticks simulated +final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 599 # Simulator instruction rate (inst/s) -host_op_rate 748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1788642 # Simulator tick rate (ticks/s) -host_mem_usage 284080 # Number of bytes of host memory used -host_seconds 7.66 # Real time elapsed on the host +host_inst_rate 31359 # Simulator instruction rate (inst/s) +host_op_rate 39125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111893890 # Simulator tick rate (ticks/s) +host_mem_usage 244352 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 394 # Total number of read requests seen +system.physmem.num_reads::total 393 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 393 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 25216 # Total number of bytes read from memory +system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25152 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13648500 # Total gap between requests +system.physmem.totGap 16329500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 394 # Categorize read packet sizes +system.physmem.readPktSize::6 393 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,34 +149,68 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2507750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests -system.physmem.totBusLat 1970000 # Total cycles spent in databus access -system.physmem.totBankLat 7273750 # Total cycles spent in bank access -system.physmem.avgQLat 6364.85 # Average queueing delay per request -system.physmem.avgBankLat 18461.29 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation +system.physmem.totQLat 2029000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests +system.physmem.totBusLat 1965000 # Total cycles spent in databus access +system.physmem.totBankLat 5472500 # Total cycles spent in bank access +system.physmem.avgQLat 5162.85 # Average queueing delay per request +system.physmem.avgBankLat 13924.94 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29826.14 # Average memory access latency -system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24087.79 # Average memory access latency +system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 14.37 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.86 # Average read queue length over time +system.physmem.busUtil 11.99 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.58 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 294 # Number of row buffer hits during reads +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads +system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34640.86 # Average gap between requests -system.cpu.branchPred.lookups 2491 # Number of BP lookups -system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted +system.physmem.avgGap 41550.89 # Average gap between requests +system.membus.throughput 1534875206 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 352 # Transaction distribution +system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.membus.trans_dist::ReadExReq 41 # Transaction distribution +system.membus.trans_dist::ReadExResp 41 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 786 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.4 # Layer utilization (%) +system.cpu.branchPred.lookups 2471 # Number of BP lookups +system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups -system.cpu.branchPred.BTBHits 700 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups +system.cpu.branchPred.BTBHits 695 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits @@ -267,235 +301,235 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 27413 # number of cpu cycles simulated +system.cpu.numCycles 32775 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2438 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2415 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2238 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups +system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2217 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8967 # Type of FU issued -system.cpu.iq.rate 0.327108 # Inst issue rate -system.cpu.iq.fu_busy_cnt 230 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.272189 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3301 # number of memory reference insts executed -system.cpu.iew.exec_branches 1438 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.311713 # Inst execution rate -system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3894 # num instructions producing a value -system.cpu.iew.wb_consumers 7825 # num instructions consuming a value +system.cpu.iew.exec_refs 3294 # number of memory reference insts executed +system.cpu.iew.exec_branches 1436 # Number of branches executed +system.cpu.iew.exec_stores 1160 # Number of stores executed +system.cpu.iew.exec_rate 0.259863 # Inst execution rate +system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3885 # num instructions producing a value +system.cpu.iew.wb_consumers 7780 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back +system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -506,150 +540,169 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23047 # The number of ROB reads -system.cpu.rob.rob_writes 23560 # The number of ROB writes +system.cpu.rob.rob_reads 23312 # The number of ROB reads +system.cpu.rob.rob_writes 23396 # The number of ROB writes system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads -system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39296 # number of integer regfile reads -system.cpu.int_regfile_writes 8001 # number of integer regfile writes +system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads +system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39187 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2981 # number of misc regfile reads +system.cpu.misc_regfile_reads 2976 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use -system.cpu.icache.total_refs 1590 # Total number of references to valid blocks. +system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use +system.cpu.icache.total_refs 1578 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits -system.cpu.icache.overall_hits::total 1590 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses -system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits +system.cpu.icache.overall_hits::total 1578 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18642000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18642000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149846 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149846 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149846 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64061.855670 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64061.855670 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.107247 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.934708 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.910959 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51875 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53290.502793 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.064426 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.804878 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.804878 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68658.291457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68658.291457 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,142 +750,142 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14791750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4905500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19697250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2490250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2490250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14791750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22187500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14791750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395750 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54582.103321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60561.728395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55958.096591 # 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number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 85.937637 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020981 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020981 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1760 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1760 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits -system.cpu.dcache.overall_hits::total 2369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2366 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2366 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2366 # number of overall hits +system.cpu.dcache.overall_hits::total 2366 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses -system.cpu.dcache.overall_misses::total 500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses +system.cpu.dcache.overall_misses::total 497 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10638500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10638500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19663000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19663000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 127500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30301500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30301500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30301500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30301500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -841,30 +894,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index f41a24ed6..42ebdbb61 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13706000 # Number of ticks simulated -final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16387000 # Number of ticks simulated +final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 7143 # Simulator instruction rate (inst/s) -host_op_rate 8913 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21323596 # Simulator tick rate (ticks/s) -host_mem_usage 284080 # Number of bytes of host memory used -host_seconds 0.64 # Real time elapsed on the host +host_inst_rate 36614 # Simulator instruction rate (inst/s) +host_op_rate 45680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 130634561 # Simulator tick rate (ticks/s) +host_mem_usage 244344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 394 # Total number of read requests seen +system.physmem.num_reads::total 393 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 393 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 25216 # Total number of bytes read from memory +system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25152 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13648500 # Total gap between requests +system.physmem.totGap 16329500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 394 # Categorize read packet sizes +system.physmem.readPktSize::6 393 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,34 +149,68 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2507750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests -system.physmem.totBusLat 1970000 # Total cycles spent in databus access -system.physmem.totBankLat 7273750 # Total cycles spent in bank access -system.physmem.avgQLat 6364.85 # Average queueing delay per request -system.physmem.avgBankLat 18461.29 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation +system.physmem.totQLat 2029000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests +system.physmem.totBusLat 1965000 # Total cycles spent in databus access +system.physmem.totBankLat 5472500 # Total cycles spent in bank access +system.physmem.avgQLat 5162.85 # Average queueing delay per request +system.physmem.avgBankLat 13924.94 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29826.14 # Average memory access latency -system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24087.79 # Average memory access latency +system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 14.37 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.86 # Average read queue length over time +system.physmem.busUtil 11.99 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.58 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 294 # Number of row buffer hits during reads +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads +system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34640.86 # Average gap between requests -system.cpu.branchPred.lookups 2491 # Number of BP lookups -system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted +system.physmem.avgGap 41550.89 # Average gap between requests +system.membus.throughput 1534875206 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 352 # Transaction distribution +system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.membus.trans_dist::ReadExReq 41 # Transaction distribution +system.membus.trans_dist::ReadExResp 41 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 786 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.4 # Layer utilization (%) +system.cpu.branchPred.lookups 2471 # Number of BP lookups +system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups -system.cpu.branchPred.BTBHits 700 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups +system.cpu.branchPred.BTBHits 695 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -222,235 +256,235 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 27413 # number of cpu cycles simulated +system.cpu.numCycles 32775 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2438 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2415 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2238 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups +system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2217 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8967 # Type of FU issued -system.cpu.iq.rate 0.327108 # Inst issue rate -system.cpu.iq.fu_busy_cnt 230 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.272189 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3301 # number of memory reference insts executed -system.cpu.iew.exec_branches 1438 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.311713 # Inst execution rate -system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3894 # num instructions producing a value -system.cpu.iew.wb_consumers 7825 # num instructions consuming a value +system.cpu.iew.exec_refs 3294 # number of memory reference insts executed +system.cpu.iew.exec_branches 1436 # Number of branches executed +system.cpu.iew.exec_stores 1160 # Number of stores executed +system.cpu.iew.exec_rate 0.259863 # Inst execution rate +system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3885 # num instructions producing a value +system.cpu.iew.wb_consumers 7780 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back +system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,150 +495,169 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23047 # The number of ROB reads -system.cpu.rob.rob_writes 23560 # The number of ROB writes +system.cpu.rob.rob_reads 23312 # The number of ROB reads +system.cpu.rob.rob_writes 23396 # The number of ROB writes system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads -system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39296 # number of integer regfile reads -system.cpu.int_regfile_writes 8001 # number of integer regfile writes +system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads +system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39187 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2981 # number of misc regfile reads +system.cpu.misc_regfile_reads 2976 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use -system.cpu.icache.total_refs 1590 # Total number of references to valid blocks. +system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use +system.cpu.icache.total_refs 1578 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits -system.cpu.icache.overall_hits::total 1590 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses -system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits +system.cpu.icache.overall_hits::total 1578 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18642000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18642000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149846 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149846 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149846 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64061.855670 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64061.855670 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.107247 # Cycle average of tags in use -system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 183.439490 # Cycle average of tags in use +system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.113636 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.394475 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.712772 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004223 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001426 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005649 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::cpu.inst 137.046036 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.393454 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004182 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001416 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005598 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits +system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 20 # 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number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses +system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19078000 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.064426 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.804878 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.804878 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68658.291457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68658.291457 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -652,142 +705,142 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # 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number of replacements -system.cpu.dcache.tagsinuse 86.521929 # Cycle average of tags in use -system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.937637 # Cycle average of tags in use +system.cpu.dcache.total_refs 2388 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.376712 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.356164 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.521929 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021124 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021124 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1763 # 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number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -796,30 +849,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 9c0909975..05df8bae0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1926 # Simulator instruction rate (inst/s) -host_op_rate 2404 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1204405 # Simulator tick rate (ticks/s) -host_mem_usage 275696 # Number of bytes of host memory used -host_seconds 2.38 # Real time elapsed on the host +host_inst_rate 686137 # Simulator instruction rate (inst/s) +host_op_rate 854515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 427336749 # Simulator tick rate (ticks/s) +host_mem_usage 232512 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1270858735 # Wr system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9251001568 # Throughput (bytes/s) +system.membus.data_through_bus 26555 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 1d0558bdb..ea8a36796 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122854 # Simulator instruction rate (inst/s) -host_op_rate 153228 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76735417 # Simulator tick rate (ticks/s) -host_mem_usage 275692 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 723203 # Simulator instruction rate (inst/s) +host_op_rate 900650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 450384934 # Simulator tick rate (ticks/s) +host_mem_usage 232532 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1270858735 # Wr system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9251001568 # Throughput (bytes/s) +system.membus.data_through_bus 26555 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 2bce78814..744017c0b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25969000 # Number of ticks simulated final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66941 # Simulator instruction rate (inst/s) -host_op_rate 83151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 380602116 # Simulator tick rate (ticks/s) -host_mem_usage 284140 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 220478 # Simulator instruction rate (inst/s) +host_op_rate 273604 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1251201624 # Simulator tick rate (ticks/s) +host_mem_usage 241012 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 554507297 # In system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 862566907 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 307 # Transaction distribution +system.membus.trans_dist::ReadResp 307 # Transaction distribution +system.membus.trans_dist::ReadExReq 43 # Transaction distribution +system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 700 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22400 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.1 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -404,5 +419,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 941430167 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 482 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 764 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 24448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 54d30dc78..4cccc3a14 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19339000 # Number of ticks simulated -final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 24539000 # Number of ticks simulated +final_tick 24539000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26477 # Simulator instruction rate (inst/s) -host_op_rate 26474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88053451 # Simulator tick rate (ticks/s) -host_mem_usage 270344 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 40560 # Simulator instruction rate (inst/s) +host_op_rate 40552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171130571 # Simulator tick rate (ticks/s) +host_mem_usage 226208 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1049071824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 456693728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1505765551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1049071824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1049071824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1049071824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 456693728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1505765551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 826765557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 359916867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1186682424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 826765557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 826765557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 826765557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 359916867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1186682424 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 29120 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 89 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 59 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 75 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19292000 # Total gap between requests +system.physmem.totGap 24472000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -149,34 +149,69 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2650000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13958750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 94 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.234043 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.011055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 299.928179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 34 36.17% 36.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 16 17.02% 53.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 9 9.57% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 9.57% 72.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 4.26% 76.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 9 9.57% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.06% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.13% 89.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 2.13% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.13% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 2.13% 95.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 1.06% 96.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.06% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation +system.physmem.totQLat 2632000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13115750 # Sum of mem lat for all requests system.physmem.totBusLat 2275000 # Total cycles spent in databus access -system.physmem.totBankLat 9033750 # Total cycles spent in bank access -system.physmem.avgQLat 5824.18 # Average queueing delay per request -system.physmem.avgBankLat 19854.40 # Average bank access latency per request +system.physmem.totBankLat 8208750 # Total cycles spent in bank access +system.physmem.avgQLat 5784.62 # Average queueing delay per request +system.physmem.avgBankLat 18041.21 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30678.57 # Average memory access latency -system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28825.82 # Average memory access latency +system.physmem.avgRdBW 1186.68 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1186.68 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.76 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.72 # Average read queue length over time +system.physmem.busUtil 9.27 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.53 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 334 # Number of row buffer hits during reads +system.physmem.readRowHits 361 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42400.00 # Average gap between requests -system.cpu.branchPred.lookups 1154 # Number of BP lookups -system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted +system.physmem.avgGap 53784.62 # Average gap between requests +system.membus.throughput 1186682424 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 404 # Transaction distribution +system.membus.trans_dist::ReadResp 404 # Transaction distribution +system.membus.trans_dist::ReadExReq 51 # Transaction distribution +system.membus.trans_dist::ReadExResp 51 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 910 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 29120 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4265750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.4 # Layer utilization (%) +system.cpu.branchPred.lookups 1157 # Number of BP lookups +system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 877 # Number of BTB lookups -system.cpu.branchPred.BTBHits 336 # Number of BTB hits +system.cpu.branchPred.BTBLookups 880 # Number of BTB lookups +system.cpu.branchPred.BTBHits 339 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.312429 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 38.522727 # BTB Hit Percentage system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -198,34 +233,34 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 38679 # number of cpu cycles simulated +system.cpu.numCycles 49079 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5089 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8485 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1292 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1328 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2229 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 274 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 594 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 321 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 64.918033 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3135 # Number of Instructions Executed. +system.cpu.execution_unit.executions 3133 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9463 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9516 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33303 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5376 # Number of cycles cpu stages are processed. -system.cpu.activity 13.899015 # Percentage of cycles cpu is active +system.cpu.timesIdled 488 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 43696 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. +system.cpu.activity 10.968031 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -237,72 +272,72 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 6.652735 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.441520 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.652735 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150314 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.441520 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118462 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150314 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 35030 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3649 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.434060 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 35863 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2816 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.280436 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 35914 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.118462 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45429 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 7.436989 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46265 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 5.733613 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46314 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.148582 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 37453 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.169679 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 35777 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.utilization 5.633774 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47841 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.522464 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46189 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 5.888466 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use -system.cpu.icache.total_refs 429 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 150.599216 # Cycle average of tags in use +system.cpu.icache.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.344828 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 429 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 429 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 429 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 429 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 429 # number of overall hits -system.cpu.icache.overall_hits::total 429 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses -system.cpu.icache.overall_misses::total 346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18937500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18937500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18937500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 775 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 775 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 775 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.446452 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.446452 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.446452 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.446452 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.446452 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.446452 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54732.658960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54732.658960 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.599216 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073535 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073535 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits +system.cpu.icache.overall_hits::total 428 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25149500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25149500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25149500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25149500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25149500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25149500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 778 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 778 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.449871 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.449871 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71855.714286 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71855.714286 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71855.714286 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71855.714286 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -311,48 +346,67 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 27 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 27 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 31 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 31 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 31 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17329000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17329000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17329000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.411613 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.411613 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.411613 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54322.884013 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54322.884013 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22969000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22969000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22969000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22969000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22969000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22969000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72003.134796 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72003.134796 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1191898610 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 638 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 29248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 206.866533 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 208.333773 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 151.045990 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.820543 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 152.278645 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.055128 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006358 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -370,17 +424,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16983500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5162000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 22145500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2560500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2560500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16983500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7722500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24706000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16983500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7722500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24706000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22623500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6716000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29339500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3640500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3640500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22623500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10356500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32980000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22623500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10356500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32980000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -403,17 +457,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53575.709779 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54815.594059 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50205.882353 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50205.882353 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54298.901099 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54298.901099 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71367.507886 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77195.402299 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72622.524752 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71382.352941 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71382.352941 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71367.507886 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75047.101449 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72483.516484 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71367.507886 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75047.101449 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72483.516484 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,17 +487,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055265 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090554 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17145819 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925038 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925038 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055265 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015592 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19070857 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055265 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015592 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19070857 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18696000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5647250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24343250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18696000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8653250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27349250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18696000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8653250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27349250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -455,51 +509,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41183.801262 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47017.862069 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.146040 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37745.843137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37745.843137 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58977.917981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64910.919540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60255.569307 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use -system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 90.129103 # Cycle average of tags in use +system.cpu.dcache.total_refs 1637 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.862319 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.917113 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021952 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021952 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1644 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1644 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1644 # number of overall hits -system.cpu.dcache.overall_hits::total 1644 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 93 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 351 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 351 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 444 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses -system.cpu.dcache.overall_misses::total 444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5626500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5626500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14767500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14767500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20394000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20394000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20394000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20394000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 90.129103 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022004 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022004 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1065 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1065 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1637 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1637 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1637 # number of overall hits +system.cpu.dcache.overall_hits::total 1637 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 451 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 451 # number of overall misses +system.cpu.dcache.overall_misses::total 451 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7478500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7478500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21383500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21383500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28862000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28862000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28862000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28862000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -508,38 +562,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2088 # system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.379459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.379459 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60500 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60500 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42072.649573 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42072.649573 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45932.432432 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45932.432432 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084265 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.084265 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.215996 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.215996 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.215996 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.215996 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76311.224490 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76311.224490 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60576.487252 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60576.487252 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63995.565410 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63995.565410 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 253 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.461538 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 313 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 313 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -548,14 +602,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5255500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5255500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2614500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2614500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7870000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7870000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3694500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3694500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10504000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10504000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10504000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10504000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -564,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60408.045977 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60408.045977 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51264.705882 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51264.705882 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78270.114943 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78270.114943 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72441.176471 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72441.176471 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index c79016c7b..37ca97b46 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17026500 # Number of ticks simulated -final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 21759500 # Number of ticks simulated +final_tick 21759500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19281 # Simulator instruction rate (inst/s) -host_op_rate 19280 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63663526 # Simulator tick rate (ticks/s) -host_mem_usage 270344 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 43168 # Simulator instruction rate (inst/s) +host_op_rate 43158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 182102261 # Simulator tick rate (ticks/s) +host_mem_usage 228268 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21504 # Nu system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory system.physmem.num_reads::total 478 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1262972425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 533756204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1796728629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1262972425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1262972425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1262972425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 533756204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1796728629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 988258002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 417656656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1405914658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 988258002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 988258002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 988258002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 417656656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1405914658 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 478 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 30592 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 93 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16967000 # Total gap between requests +system.physmem.totGap 21680500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,36 +149,70 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2843000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14596750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.330097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.624939 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.862985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 1.94% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 3.88% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation +system.physmem.totQLat 2435500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13501750 # Sum of mem lat for all requests system.physmem.totBusLat 2390000 # Total cycles spent in databus access -system.physmem.totBankLat 9363750 # Total cycles spent in bank access -system.physmem.avgQLat 5947.70 # Average queueing delay per request -system.physmem.avgBankLat 19589.44 # Average bank access latency per request +system.physmem.totBankLat 8676250 # Total cycles spent in bank access +system.physmem.avgQLat 5095.19 # Average queueing delay per request +system.physmem.avgBankLat 18151.15 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30537.13 # Average memory access latency -system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28246.34 # Average memory access latency +system.physmem.avgRdBW 1405.91 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1405.91 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 14.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.86 # Average read queue length over time +system.physmem.busUtil 10.98 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.62 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 351 # Number of row buffer hits during reads +system.physmem.readRowHits 375 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.45 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 35495.82 # Average gap between requests -system.cpu.branchPred.lookups 2218 # Number of BP lookups -system.cpu.branchPred.condPredicted 1500 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1689 # Number of BTB lookups -system.cpu.branchPred.BTBHits 508 # Number of BTB hits +system.physmem.avgGap 45356.69 # Average gap between requests +system.membus.throughput 1405914658 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 427 # Transaction distribution +system.membus.trans_dist::ReadResp 427 # Transaction distribution +system.membus.trans_dist::ReadExReq 51 # Transaction distribution +system.membus.trans_dist::ReadExResp 51 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 956 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 956 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 30592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30592 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 590000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4475750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.6 # Layer utilization (%) +system.cpu.branchPred.lookups 2196 # Number of BP lookups +system.cpu.branchPred.condPredicted 1494 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1671 # Number of BTB lookups +system.cpu.branchPred.BTBHits 505 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.076969 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 30.221424 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 262 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -198,94 +232,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 34054 # number of cpu cycles simulated +system.cpu.numCycles 43520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13373 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2218 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3270 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1400 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8865 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13232 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 767 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3240 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1388 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1327 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2012 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.946895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.257314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.912867 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.222713 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10853 76.85% 76.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1348 9.54% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 105 0.74% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 135 0.96% 88.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.16% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.84% 91.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 156 1.10% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 160 1.13% 93.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 943 6.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11255 77.65% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1338 9.23% 86.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 132 0.91% 88.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 307 2.12% 90.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 118 0.81% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 149 1.03% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 934 6.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065132 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.392700 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8861 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1237 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3093 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 888 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.050460 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.304044 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8953 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1558 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3054 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 877 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12489 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12351 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 888 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 802 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2958 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.SquashCycles 877 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9138 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 511 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 897 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2924 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 93 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7237 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14212 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14208 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7195 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14132 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14128 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3839 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2482 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1199 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3797 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2463 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8318 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3635 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2167 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14123 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.588968 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.255126 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8313 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3584 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.573508 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.239818 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10544 74.66% 74.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1399 9.91% 84.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 897 6.35% 90.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 565 4.00% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 359 2.54% 97.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 225 1.59% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10895 75.16% 75.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1434 9.89% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 892 6.15% 91.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 557 3.84% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 358 2.47% 97.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.56% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 86 0.59% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available @@ -321,113 +355,113 @@ system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4943 59.43% 59.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2262 27.19% 86.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 13.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4947 59.51% 59.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2253 27.10% 86.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8318 # Type of FU issued -system.cpu.iq.rate 0.244259 # Inst issue rate +system.cpu.iq.FU_type_0::total 8313 # Type of FU issued +system.cpu.iq.rate 0.191016 # Inst issue rate system.cpu.iq.fu_busy_cnt 159 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30960 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12952 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7465 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019127 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31318 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12850 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8470 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1319 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1300 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 274 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 888 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10854 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2482 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1199 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 877 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 334 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10786 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2463 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 102 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7932 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 386 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 461 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2118 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 377 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1546 # number of nop insts executed -system.cpu.iew.exec_refs 3202 # number of memory reference insts executed -system.cpu.iew.exec_branches 1355 # Number of branches executed -system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.232924 # Inst execution rate -system.cpu.iew.wb_sent 7556 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7467 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2949 # num instructions producing a value -system.cpu.iew.wb_consumers 4258 # num instructions consuming a value +system.cpu.iew.exec_nop 1529 # number of nop insts executed +system.cpu.iew.exec_refs 3196 # number of memory reference insts executed +system.cpu.iew.exec_branches 1356 # Number of branches executed +system.cpu.iew.exec_stores 1078 # Number of stores executed +system.cpu.iew.exec_rate 0.182353 # Inst execution rate +system.cpu.iew.wb_sent 7562 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7469 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2922 # num instructions producing a value +system.cpu.iew.wb_consumers 4200 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.219269 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692579 # average fanout of values written-back +system.cpu.iew.wb_rate 0.171622 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.695714 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5033 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4965 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13235 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.439214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.223104 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13618 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.426862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.205287 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10851 81.99% 81.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.12% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 96 0.73% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 63 0.48% 98.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.31% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11210 82.32% 82.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1002 7.36% 89.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 633 4.65% 94.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 319 2.34% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 147 1.08% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 94 0.69% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.49% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.29% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13618 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -438,119 +472,138 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23961 # The number of ROB reads -system.cpu.rob.rob_writes 22589 # The number of ROB writes -system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19931 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24277 # The number of ROB reads +system.cpu.rob.rob_writes 22442 # The number of ROB writes +system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29025 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 6.604732 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads -system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10750 # number of integer regfile reads -system.cpu.int_regfile_writes 5236 # number of integer regfile writes +system.cpu.cpi 8.440652 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.440652 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118474 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.118474 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10757 # number of integer regfile reads +system.cpu.int_regfile_writes 5239 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 150 # number of misc regfile reads +system.cpu.misc_regfile_reads 148 # number of misc regfile reads +system.cpu.toL2Bus.throughput 1414738390 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 430 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 30784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 508500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 162.197466 # Cycle average of tags in use -system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.130962 # Cycle average of tags in use +system.cpu.icache.total_refs 1541 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.545723 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 162.197466 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079198 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079198 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits -system.cpu.icache.overall_hits::total 1566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses -system.cpu.icache.overall_misses::total 446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22343000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22343000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22343000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22343000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22343000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22343000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2012 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2012 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2012 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2012 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221670 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.221670 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.221670 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.221670 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.221670 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.221670 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50096.412556 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50096.412556 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50096.412556 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50096.412556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50096.412556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50096.412556 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 161.130962 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078677 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078677 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1541 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1541 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1541 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1541 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1541 # number of overall hits +system.cpu.icache.overall_hits::total 1541 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses +system.cpu.icache.overall_misses::total 453 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30806000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30806000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30806000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30806000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30806000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30806000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1994 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1994 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1994 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1994 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1994 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227182 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.227182 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.227182 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.227182 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.227182 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.584950 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.776656 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005023 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006786 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 163.410737 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.683266 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004987 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006747 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34490000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23576500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10913500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34490000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 430 # number of ReadReq accesses(hits+misses) @@ -601,17 +654,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51900.297619 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64978.021978 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54687.353630 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52098.039216 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52098.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51900.297619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60352.112676 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54411.087866 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51900.297619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60352.112676 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54411.087866 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70168.154762 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77686.813187 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71770.491803 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75372.549020 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75372.549020 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70168.154762 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76855.633803 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72154.811715 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70168.154762 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76855.633803 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72154.811715 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,17 +684,17 @@ system.cpu.l2cache.demand_mshr_misses::total 478 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13259027 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4798293 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18057320 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13259027 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6830321 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20089348 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13259027 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6830321 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20089348 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19402750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5959000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25361750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3218500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3218500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19402750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9177500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28580250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19402750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9177500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28580250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses @@ -653,91 +706,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39461.389881 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52728.494505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42288.805621 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57746.279762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65483.516484 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59395.199063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63107.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63107.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57746.279762 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64630.281690 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57746.279762 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64630.281690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 91.619831 # Cycle average of tags in use -system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.370944 # Cycle average of tags in use +system.cpu.dcache.total_refs 2400 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.901408 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 91.619831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022368 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022368 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1852 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1852 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2424 # number of overall hits -system.cpu.dcache.overall_hits::total 2424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses -system.cpu.dcache.overall_misses::total 501 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8995500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8995500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15098999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15098999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24094499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24094499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24094499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24094499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2000 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 91.370944 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022307 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022307 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits +system.cpu.dcache.overall_hits::total 2400 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses +system.cpu.dcache.overall_misses::total 511 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10242000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22669999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22669999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32911999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32911999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32911999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32911999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1986 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2925 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2925 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2925 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2925 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074000 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.074000 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.171282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.171282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.171282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.171282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60780.405405 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60780.405405 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42773.368272 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42773.368272 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48092.812375 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48092.812375 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2911 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2911 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2911 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2911 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.175541 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175541 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175541 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175541 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68738.255034 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68738.255034 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62624.306630 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62624.306630 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64407.043053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64407.043053 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 642 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.363636 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 359 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 359 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 359 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 359 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -746,30 +799,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8716499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8716499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8716499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8716499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3895999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3895999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11059999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11059999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11059999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11059999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045821 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045821 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66016.483516 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66016.483516 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048780 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048780 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78725.274725 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78725.274725 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76392.137255 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76392.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 773dc4053..e850cb6a0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2907000 # Number of ticks simulated final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85249 # Simulator instruction rate (inst/s) -host_op_rate 85225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42601271 # Simulator tick rate (ticks/s) -host_mem_usage 261900 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 727521 # Simulator instruction rate (inst/s) +host_op_rate 725084 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 361375060 # Simulator tick rate (ticks/s) +host_mem_usage 216568 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1258341933 # Wr system.physmem.bw_total::cpu.inst 8001375989 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2762985896 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10764361885 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10764361885 # Throughput (bytes/s) +system.membus.data_through_bus 31292 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 45395bf9c..0d57ed336 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3112 # Simulator instruction rate (inst/s) -host_op_rate 3112 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16931146 # Simulator tick rate (ticks/s) -host_mem_usage 270356 # Number of bytes of host memory used -host_seconds 1.87 # Real time elapsed on the host +host_inst_rate 482351 # Simulator instruction rate (inst/s) +host_op_rate 481309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2613274672 # Simulator tick rate (ticks/s) +host_mem_usage 225064 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 608984289 # In system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 888186388 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 388 # Transaction distribution +system.membus.trans_dist::ReadResp 388 # Transaction distribution +system.membus.trans_dist::ReadExReq 51 # Transaction distribution +system.membus.trans_dist::ReadExResp 51 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 878 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 28096 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.5 # Layer utilization (%) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -369,5 +384,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 882 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 28224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 30ea78059..43017685d 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 14724500 # Number of ticks simulated -final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18326500 # Number of ticks simulated +final_tick 18326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 11850 # Simulator instruction rate (inst/s) -host_op_rate 11850 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30123505 # Simulator tick rate (ticks/s) -host_mem_usage 266600 # Number of bytes of host memory used -host_seconds 0.49 # Real time elapsed on the host +host_inst_rate 41507 # Simulator instruction rate (inst/s) +host_op_rate 41499 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131284333 # Simulator tick rate (ticks/s) +host_mem_usage 224304 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1499541580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 438996231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1938537811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1499541580 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1499541580 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1499541580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 438996231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1938537811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1204812703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 352713284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1557525987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1204812703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1204812703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1204812703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 352713284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1557525987 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 446 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 28544 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 56 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 14617000 # Total gap between requests +system.physmem.totGap 18199000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,35 +149,70 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2285750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12779500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation +system.physmem.totQLat 2004500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10972000 # Sum of mem lat for all requests system.physmem.totBusLat 2230000 # Total cycles spent in databus access -system.physmem.totBankLat 8263750 # Total cycles spent in bank access -system.physmem.avgQLat 5125.00 # Average queueing delay per request -system.physmem.avgBankLat 18528.59 # Average bank access latency per request +system.physmem.totBankLat 6737500 # Total cycles spent in bank access +system.physmem.avgQLat 4494.39 # Average queueing delay per request +system.physmem.avgBankLat 15106.50 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28653.59 # Average memory access latency -system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24600.90 # Average memory access latency +system.physmem.avgRdBW 1557.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1557.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.87 # Average read queue length over time +system.physmem.busUtil 12.17 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.60 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 338 # Number of row buffer hits during reads +system.physmem.readRowHits 380 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32773.54 # Average gap between requests -system.cpu.branchPred.lookups 2226 # Number of BP lookups -system.cpu.branchPred.condPredicted 1794 # Number of conditional branches predicted +system.physmem.avgGap 40804.93 # Average gap between requests +system.membus.throughput 1557525987 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 399 # Transaction distribution +system.membus.trans_dist::ReadResp 399 # Transaction distribution +system.membus.trans_dist::ReadExReq 47 # Transaction distribution +system.membus.trans_dist::ReadExResp 47 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 892 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 28544 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 559500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 4174500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.8 # Layer utilization (%) +system.cpu.branchPred.lookups 2238 # Number of BP lookups +system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1842 # Number of BTB lookups -system.cpu.branchPred.BTBHits 599 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1851 # Number of BTB lookups +system.cpu.branchPred.BTBHits 603 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.519001 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.576985 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -198,92 +233,92 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 29450 # number of cpu cycles simulated +system.cpu.numCycles 36654 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7448 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13075 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2226 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 797 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2246 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1279 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1007 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11551 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.131937 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7507 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13158 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1292 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.109724 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.526984 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9305 80.56% 80.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 175 1.52% 82.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 174 1.51% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 140 1.21% 84.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.97% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.14% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 256 2.22% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 108 0.93% 91.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1034 8.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9595 80.92% 80.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 1.50% 82.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.48% 83.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 141 1.19% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.91% 87.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.12% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.17% 90.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11551 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075586 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.443973 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7514 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1178 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2083 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 697 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 11857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.061057 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.358979 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7580 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1390 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2096 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 710 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11641 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 697 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 476 # Number of cycles rename is blocking +system.cpu.decode.DecodedInsts 11719 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 710 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7768 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 673 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1969 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 261 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11203 # Number of instructions processed by rename +system.cpu.rename.RunCycles 1984 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 273 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11300 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 218 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9614 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18041 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17986 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 232 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9692 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18178 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18123 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4616 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4694 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 553 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1993 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10211 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10310 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8907 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 171 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4167 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3342 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4245 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3499 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11551 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.771102 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.501710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11857 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.750864 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.481785 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8211 71.08% 71.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1072 9.28% 80.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 790 6.84% 87.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 498 4.31% 91.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 4.03% 95.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 301 2.61% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 134 1.16% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.38% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 35 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8486 71.57% 71.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1113 9.39% 80.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.65% 87.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 496 4.18% 91.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 461 3.89% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 303 2.56% 98.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 131 1.10% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11857 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available @@ -314,118 +349,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 69 40.35% 45.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 94 54.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5470 61.41% 61.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1795 20.15% 81.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1640 18.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8907 # Type of FU issued -system.cpu.iq.rate 0.302445 # Inst issue rate +system.cpu.iq.FU_type_0::total 8903 # Type of FU issued +system.cpu.iq.rate 0.242893 # Inst issue rate system.cpu.iq.fu_busy_cnt 171 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019198 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29645 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14405 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8123 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30013 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9044 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1032 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1062 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 757 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 697 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 276 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10268 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 710 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 456 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10367 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1993 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 329 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8493 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1673 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3204 # number of memory reference insts executed -system.cpu.iew.exec_branches 1349 # Number of branches executed -system.cpu.iew.exec_stores 1531 # Number of stores executed -system.cpu.iew.exec_rate 0.288387 # Inst execution rate -system.cpu.iew.wb_sent 8266 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8150 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4198 # num instructions producing a value -system.cpu.iew.wb_consumers 6619 # num instructions consuming a value +system.cpu.iew.exec_refs 3201 # number of memory reference insts executed +system.cpu.iew.exec_branches 1351 # Number of branches executed +system.cpu.iew.exec_stores 1523 # Number of stores executed +system.cpu.iew.exec_rate 0.231953 # Inst execution rate +system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8157 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4222 # num instructions producing a value +system.cpu.iew.wb_consumers 6684 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.276740 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.634235 # average fanout of values written-back +system.cpu.iew.wb_rate 0.222541 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631658 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4482 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4581 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.332953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11147 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.519602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.320329 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8474 78.07% 78.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 999 9.20% 87.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 620 5.71% 92.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 267 2.46% 95.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.60% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 109 1.00% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.62% 98.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 43 0.40% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8765 78.63% 78.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1011 9.07% 87.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 612 5.49% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 265 2.38% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.53% 97.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 71 0.64% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.39% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11147 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -438,116 +473,135 @@ system.cpu.commit.int_insts 5698 # Nu system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21027 # The number of ROB reads -system.cpu.rob.rob_writes 21246 # The number of ROB writes +system.cpu.rob.rob_reads 21419 # The number of ROB reads +system.cpu.rob.rob_writes 21457 # The number of ROB writes system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17899 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 24797 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 5.084599 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.084599 # CPI: Total CPI of All Threads -system.cpu.ipc 0.196672 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.196672 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13468 # number of integer regfile reads -system.cpu.int_regfile_writes 7037 # number of integer regfile writes +system.cpu.cpi 6.328384 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.328384 # CPI: Total CPI of All Threads +system.cpu.ipc 0.158018 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.158018 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13474 # number of integer regfile reads +system.cpu.int_regfile_writes 7049 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes +system.cpu.toL2Bus.throughput 1581971462 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 204 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 906 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 22464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 6528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 28992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 526500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 167.837630 # Cycle average of tags in use -system.cpu.icache.total_refs 1361 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 167.412828 # Cycle average of tags in use +system.cpu.icache.total_refs 1371 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.877493 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.905983 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 167.837630 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.081952 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.081952 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1361 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1361 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1361 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1361 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1361 # number of overall hits -system.cpu.icache.overall_hits::total 1361 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses -system.cpu.icache.overall_misses::total 441 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21880000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21880000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21880000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21880000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21880000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21880000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1802 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1802 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1802 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1802 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244728 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.244728 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.244728 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.244728 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.244728 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.244728 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49614.512472 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49614.512472 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49614.512472 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49614.512472 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 167.412828 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.081745 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.081745 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1371 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1371 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1371 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1371 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1371 # number of overall hits +system.cpu.icache.overall_hits::total 1371 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 442 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 442 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 442 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses +system.cpu.icache.overall_misses::total 442 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28629500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28629500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28629500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28629500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28629500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28629500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243795 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.243795 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.243795 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.243795 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.243795 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.243795 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64772.624434 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64772.624434 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64772.624434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64772.624434 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 425 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 52.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 70.833333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17781500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17781500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17781500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17781500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17781500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17781500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.194784 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.194784 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.194784 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50659.544160 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50659.544160 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23362000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23362000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23362000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23362000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23362000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23362000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66558.404558 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66558.404558 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.279092 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005075 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000955 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006030 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -568,17 +622,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17370000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3171000 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -601,17 +655,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50347.826087 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58722.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51481.203008 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61872.340426 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61872.340426 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50347.826087 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68836.322870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66523.188406 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68836.322870 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,17 +685,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6518500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25188500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -653,91 +707,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37915.272464 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.092593 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39072.796992 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.446809 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.446809 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54115.942029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64143.518519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55473.057644 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64994.680851 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64994.680851 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.324326 # Cycle average of tags in use -system.cpu.dcache.total_refs 2181 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.158434 # Cycle average of tags in use +system.cpu.dcache.total_refs 2188 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.382353 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.450980 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.324326 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015460 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015460 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1472 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 709 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 709 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2181 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2181 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2181 # number of overall hits -system.cpu.dcache.overall_hits::total 2181 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 337 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 337 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses -system.cpu.dcache.overall_misses::total 438 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5163000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5163000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14813997 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14813997 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19976997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19976997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19976997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19976997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1573 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1573 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 63.158434 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015420 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015420 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits +system.cpu.dcache.overall_hits::total 2188 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses +system.cpu.dcache.overall_misses::total 435 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7358500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7358500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19767997 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19767997 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27126497 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27126497 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27126497 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27126497 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2619 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2619 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2619 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2619 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064209 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.064209 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.322180 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.322180 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.167239 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.167239 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.167239 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.167239 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51118.811881 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51118.811881 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43958.448071 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43958.448071 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45609.582192 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45609.582192 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 419 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.807692 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.807692 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59722.045317 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59722.045317 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62359.763218 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62359.763218 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 100 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -746,30 +800,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2957499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2957499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6193999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6193999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034965 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034965 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4188500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4188500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7865499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7865499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7865499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7865499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038946 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038946 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58845.454545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58845.454545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62925.510638 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62925.510638 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76154.545455 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76154.545455 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78234.021277 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78234.021277 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 94ea423b8..759fbed05 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57024 # Simulator instruction rate (inst/s) -host_op_rate 57013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28496468 # Simulator tick rate (ticks/s) -host_mem_usage 257792 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 671850 # Simulator instruction rate (inst/s) +host_op_rate 669870 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 333940022 # Simulator tick rate (ticks/s) +host_mem_usage 212612 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1453383978 # Wr system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10739295580 # Throughput (bytes/s) +system.membus.data_through_bus 31101 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 91942b523..45ae1e677 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16783500 # Number of ticks simulated -final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 20764500 # Number of ticks simulated +final_tick 20764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 18770 # Simulator instruction rate (inst/s) -host_op_rate 18768 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59128079 # Simulator tick rate (ticks/s) -host_mem_usage 276316 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 44697 # Simulator instruction rate (inst/s) +host_op_rate 44687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174155494 # Simulator tick rate (ticks/s) +host_mem_usage 232524 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1102034736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 510978044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1613012780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1102034736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1102034736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1102034736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 510978044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1613012780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 890751041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 413012594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1303763635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 890751041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 890751041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 890751041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 413012594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1303763635 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27072 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 78 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 62 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 35 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 71 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16708000 # Total gap between requests +system.physmem.totGap 20696000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,27 +149,62 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2671750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12995500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.892308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 170.513476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 484.792485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 29 44.62% 44.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 12.31% 56.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 2 3.08% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 6.15% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 1 1.54% 67.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 5 7.69% 75.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.08% 78.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 3.08% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 4 6.15% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 3 4.62% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.54% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 1.54% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation +system.physmem.totQLat 3131250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11791250 # Sum of mem lat for all requests system.physmem.totBusLat 2115000 # Total cycles spent in databus access -system.physmem.totBankLat 8208750 # Total cycles spent in bank access -system.physmem.avgQLat 6316.19 # Average queueing delay per request -system.physmem.avgBankLat 19406.03 # Average bank access latency per request +system.physmem.totBankLat 6545000 # Total cycles spent in bank access +system.physmem.avgQLat 7402.48 # Average queueing delay per request +system.physmem.avgBankLat 15472.81 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30722.22 # Average memory access latency -system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27875.30 # Average memory access latency +system.physmem.avgRdBW 1303.76 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1303.76 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.60 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.77 # Average read queue length over time +system.physmem.busUtil 10.19 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 300 # Number of row buffer hits during reads +system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.92 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 39498.82 # Average gap between requests +system.physmem.avgGap 48926.71 # Average gap between requests +system.membus.throughput 1303763635 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 342 # Transaction distribution +system.membus.trans_dist::ReadResp 342 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 846 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 27072 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3936500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.0 # Layer utilization (%) system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -180,7 +215,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 33568 # number of cpu cycles simulated +system.cpu.numCycles 41530 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -202,12 +237,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9717 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. -system.cpu.activity 18.604028 # Percentage of cycles cpu is active +system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35284 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6246 # Number of cycles cpu stages are processed. +system.cpu.activity 15.039730 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -219,72 +254,72 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.301483 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.796133 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.301483 # CPI: Total CPI of All Threads -system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.796133 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128269 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 28928 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.128269 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 36890 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.822688 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 30373 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.172646 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38335 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.517993 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.693234 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38497 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 32593 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.303154 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40555 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.904552 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30411 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.347700 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38373 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.601734 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 141.184744 # Cycle average of tags in use -system.cpu.icache.total_refs 896 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 142.226837 # Cycle average of tags in use +system.cpu.icache.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 141.184744 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits -system.cpu.icache.overall_hits::total 896 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses -system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18997500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18997500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18997500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18997500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18997500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18997500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 142.226837 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069447 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069447 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 892 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 892 # number of overall hits +system.cpu.icache.overall_hits::total 892 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25702500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25702500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25702500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25702500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25702500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25702500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52479.281768 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52479.281768 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52479.281768 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52479.281768 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52479.281768 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52479.281768 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.290938 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.290938 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70225.409836 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70225.409836 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70225.409836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70225.409836 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -293,48 +328,67 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15424000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15424000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15424000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15424000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15424000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15424000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21114000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21114000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21114000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21114000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21114000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21114000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53003.436426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53003.436426 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53003.436426 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53003.436426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53003.436426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53003.436426 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72556.701031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72556.701031 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1313010186 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 27264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 167.396977 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 168.609847 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.660763 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.736213 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 141.647687 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.962160 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004323 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005146 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -355,17 +409,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15105500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3319000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18424500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4710000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4710000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15105500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8029000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23134500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15105500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8029000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23134500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20795500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3765500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24561000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5904000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5904000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20795500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9669500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30465000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20795500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9669500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30465000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -388,17 +442,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52268.166090 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62622.641509 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53872.807018 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58148.148148 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58148.148148 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52268.166090 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59917.910448 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54691.489362 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52268.166090 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59917.910448 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54691.489362 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71956.747405 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71047.169811 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71815.789474 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72888.888889 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72888.888889 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72021.276596 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72021.276596 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,17 +472,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527228 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2664291 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14191519 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719787 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719787 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527228 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6384078 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17911306 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527228 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6384078 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17911306 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17227750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3116250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20344000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4915500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4915500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17227750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8031750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25259500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17227750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8031750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25259500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -440,27 +494,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39886.602076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50269.641509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41495.669591 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47642.373134 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42343.513002 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47642.373134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42343.513002 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59611.591696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58797.169811 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59485.380117 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60685.185185 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.185185 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 84.923213 # Cycle average of tags in use system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 84.137936 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020541 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020541 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 84.923213 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020733 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020733 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -477,14 +531,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3817500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3817500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21812000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21812000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25629500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25629500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25629500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25629500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4316000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4316000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26761000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26761000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31077000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31077000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31077000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31077000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -501,19 +555,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62581.967213 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62581.967213 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54070.675105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54070.675105 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.098361 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.098361 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64796.610169 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64796.610169 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65563.291139 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65563.291139 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.406250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.406250 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -533,14 +587,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3385500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3385500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8179000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8179000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8179000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8179000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5987500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5987500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9819500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9819500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9819500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9819500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -549,14 +603,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.444444 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62694.444444 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70962.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70962.962963 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73919.753086 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73919.753086 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index bd3dfe2fe..b27d1e6f6 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73566 # Simulator instruction rate (inst/s) -host_op_rate 73547 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37192728 # Simulator tick rate (ticks/s) -host_mem_usage 269044 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 565055 # Simulator instruction rate (inst/s) +host_op_rate 563581 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 284338324 # Simulator tick rate (ticks/s) +host_mem_usage 222908 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1879755057 # Wr system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11559473001 # Throughput (bytes/s) +system.membus.data_through_bus 31147 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 5390 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 4cc5c5030..404dd533e 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116604 # Simulator instruction rate (inst/s) -host_op_rate 116555 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 608021957 # Simulator tick rate (ticks/s) -host_mem_usage 277492 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 413138 # Simulator instruction rate (inst/s) +host_op_rate 412367 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2148212772 # Simulator tick rate (ticks/s) +host_mem_usage 231400 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 587050360 # In system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 895539568 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 308 # Transaction distribution +system.membus.trans_dist::ReadResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 778 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 24896 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.6 # Layer utilization (%) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 55600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -354,5 +369,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 902446043 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 514 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 784 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 16448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 25088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index add7e0659..43264ddcf 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16021500 # Number of ticks simulated -final_tick 16021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 19589000 # Number of ticks simulated +final_tick 19589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25477 # Simulator instruction rate (inst/s) -host_op_rate 46153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75857343 # Simulator tick rate (ticks/s) -host_mem_usage 290184 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 1364 # Simulator instruction rate (inst/s) +host_op_rate 2472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4967212 # Simulator tick rate (ticks/s) +host_mem_usage 245432 # Number of bytes of host memory used +host_seconds 3.94 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory -system.physmem.bytes_read::total 26944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory -system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1110507755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 571232406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1681740162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1110507755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1110507755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1110507755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 571232406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1681740162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 422 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory +system.physmem.bytes_read::total 26432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory +system.physmem.num_reads::total 413 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 891929144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 457399561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1349328705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 891929144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 891929144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 891929144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 457399561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1349328705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 414 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 422 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 26944 # Total number of bytes read from memory +system.physmem.cpureqs 414 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 26432 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 26944 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 26432 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 50 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16004000 # Total gap between requests +system.physmem.totGap 19541000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 422 # Categorize read packet sizes +system.physmem.readPktSize::6 414 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,265 +149,303 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2229750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13029750 # Sum of mem lat for all requests -system.physmem.totBusLat 2110000 # Total cycles spent in databus access -system.physmem.totBankLat 8690000 # Total cycles spent in bank access -system.physmem.avgQLat 5283.77 # Average queueing delay per request -system.physmem.avgBankLat 20592.42 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 216.275862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 131.153640 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.056442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 43 49.43% 49.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 13 14.94% 64.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 9 10.34% 74.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 4.60% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 7 8.05% 87.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 3.45% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.15% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.15% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.15% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.15% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 2.30% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.15% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 1.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation +system.physmem.totQLat 1394000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11081500 # Sum of mem lat for all requests +system.physmem.totBusLat 2070000 # Total cycles spent in databus access +system.physmem.totBankLat 7617500 # Total cycles spent in bank access +system.physmem.avgQLat 3367.15 # Average queueing delay per request +system.physmem.avgBankLat 18399.76 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30876.18 # Average memory access latency -system.physmem.avgRdBW 1681.74 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26766.91 # Average memory access latency +system.physmem.avgRdBW 1349.33 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1681.74 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1349.33 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 13.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.81 # Average read queue length over time +system.physmem.busUtil 10.54 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 302 # Number of row buffer hits during reads +system.physmem.readRowHits 327 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.56 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 37924.17 # Average gap between requests -system.cpu.branchPred.lookups 3090 # Number of BP lookups -system.cpu.branchPred.condPredicted 3090 # Number of conditional branches predicted +system.physmem.avgGap 47200.48 # Average gap between requests +system.membus.throughput 1349328705 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 337 # Transaction distribution +system.membus.trans_dist::ReadResp 336 # Transaction distribution +system.membus.trans_dist::ReadExReq 77 # Transaction distribution +system.membus.trans_dist::ReadExResp 77 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 827 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26432 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26432 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 498000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3864000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.7 # Layer utilization (%) +system.cpu.branchPred.lookups 3089 # Number of BP lookups +system.cpu.branchPred.condPredicted 3089 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2310 # Number of BTB lookups -system.cpu.branchPred.BTBHits 714 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.909091 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 211 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 78 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 31.758530 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 32044 # number of cpu cycles simulated +system.cpu.numCycles 39179 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9523 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14230 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3090 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 925 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3948 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2389 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3636 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 340 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 19279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.312568 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.813131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10273 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14155 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3089 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3944 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5406 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 375 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21925 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.151015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.666624 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 15433 80.05% 80.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214 1.11% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 145 0.75% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 1.13% 83.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 192 1.00% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 169 0.88% 84.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 290 1.50% 86.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 155 0.80% 87.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2464 12.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18081 82.47% 82.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 213 0.97% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 143 0.65% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 223 1.02% 85.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 185 0.84% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 200 0.91% 86.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 277 1.26% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 0.72% 88.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2445 11.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 19279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.096430 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.444077 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 10008 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3780 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3579 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 127 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1785 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24215 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1785 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 10348 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2654 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3350 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 726 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22708 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 31 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 620 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25234 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 54863 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54847 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21925 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.078843 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.361290 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11051 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5299 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3578 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24188 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11417 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3782 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 753 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3333 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 783 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22649 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 669 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25230 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 54980 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54964 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14171 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1819 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2277 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1616 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 14167 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2073 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2281 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1568 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20098 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 251 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9536 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13688 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 19279 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.881996 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.736426 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 20212 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17024 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9720 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13890 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21925 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.776465 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.650682 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13831 71.74% 71.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1491 7.73% 79.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1108 5.75% 85.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 718 3.72% 88.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 686 3.56% 92.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 589 3.06% 95.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 582 3.02% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 230 1.19% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 44 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16429 74.93% 74.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1551 7.07% 82.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1089 4.97% 86.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 725 3.31% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 705 3.22% 93.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 574 2.62% 96.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 578 2.64% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 230 1.05% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 44 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 19279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21925 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 127 76.51% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 14.46% 90.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 9.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 139 76.80% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27 14.92% 91.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13619 80.09% 80.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1977 11.63% 91.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1394 8.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13662 80.25% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1972 11.58% 91.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1376 8.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17004 # Type of FU issued -system.cpu.iq.rate 0.530645 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009762 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53696 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 29666 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17024 # Type of FU issued +system.cpu.iq.rate 0.434518 # Inst issue rate +system.cpu.iq.fu_busy_cnt 181 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010632 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56436 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 29967 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15651 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17163 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17198 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 167 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 173 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1224 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1228 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 633 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1785 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1955 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20123 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2277 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1616 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2975 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20240 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 40 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2281 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1568 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 121 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 553 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 674 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16111 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 893 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 114 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 683 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16133 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1855 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 891 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3149 # number of memory reference insts executed -system.cpu.iew.exec_branches 1620 # Number of branches executed -system.cpu.iew.exec_stores 1296 # Number of stores executed -system.cpu.iew.exec_rate 0.502777 # Inst execution rate -system.cpu.iew.wb_sent 15852 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15645 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10112 # num instructions producing a value -system.cpu.iew.wb_consumers 15481 # num instructions consuming a value +system.cpu.iew.exec_refs 3133 # number of memory reference insts executed +system.cpu.iew.exec_branches 1621 # Number of branches executed +system.cpu.iew.exec_stores 1278 # Number of stores executed +system.cpu.iew.exec_rate 0.411777 # Inst execution rate +system.cpu.iew.wb_sent 15873 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15655 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10119 # num instructions producing a value +system.cpu.iew.wb_consumers 15566 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.488235 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653188 # average fanout of values written-back +system.cpu.iew.wb_rate 0.399576 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.650071 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10375 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10504 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 582 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 17494 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.557162 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.425293 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485699 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.341238 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13941 79.69% 79.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1339 7.65% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 594 3.40% 90.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 714 4.08% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 361 2.06% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 136 0.78% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 122 0.70% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 74 0.42% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 213 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16495 82.20% 82.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1364 6.80% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 592 2.95% 91.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 713 3.55% 95.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71 0.35% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 213 1.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 17494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20068 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -420,117 +458,136 @@ system.cpu.commit.int_insts 9654 # Nu system.cpu.commit.function_calls 106 # Number of function calls committed. system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 37403 # The number of ROB reads -system.cpu.rob.rob_writes 42056 # The number of ROB writes -system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12765 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40106 # The number of ROB reads +system.cpu.rob.rob_writes 42382 # The number of ROB writes +system.cpu.timesIdled 168 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17254 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 5.956134 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.956134 # CPI: Total CPI of All Threads -system.cpu.ipc 0.167894 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.167894 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28607 # number of integer regfile reads -system.cpu.int_regfile_writes 17139 # number of integer regfile writes +system.cpu.cpi 7.282342 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.282342 # CPI: Total CPI of All Threads +system.cpu.ipc 0.137318 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.137318 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28721 # number of integer regfile reads +system.cpu.int_regfile_writes 17199 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7155 # number of misc regfile reads +system.cpu.misc_regfile_reads 7135 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.toL2Bus.throughput 1355862984 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 338 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 283 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 831 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 26560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26560 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 411000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 134.419040 # Cycle average of tags in use -system.cpu.icache.total_refs 1594 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.713262 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 130.964375 # Cycle average of tags in use +system.cpu.icache.total_refs 1611 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 274 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.879562 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 134.419040 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.065634 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.065634 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1594 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1594 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1594 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1594 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1594 # number of overall hits -system.cpu.icache.overall_hits::total 1594 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses -system.cpu.icache.overall_misses::total 371 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19224000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19224000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19224000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19224000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19224000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19224000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.188804 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.188804 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.188804 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.188804 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.188804 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.188804 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51816.711590 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51816.711590 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51816.711590 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51816.711590 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51816.711590 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51816.711590 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 130.964375 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.063947 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.063947 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1611 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1611 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1611 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1611 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1611 # number of overall hits +system.cpu.icache.overall_hits::total 1611 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 370 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 370 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 370 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 370 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 370 # number of overall misses +system.cpu.icache.overall_misses::total 370 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24285500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24285500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24285500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24285500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24285500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24285500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186774 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186774 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186774 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186774 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186774 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186774 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65636.486486 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65636.486486 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65636.486486 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65636.486486 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65636.486486 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65636.486486 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15030000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15030000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15030000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15030000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15030000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15030000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142494 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142494 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142494 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142494 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53678.571429 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53678.571429 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53678.571429 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53678.571429 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53678.571429 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53678.571429 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 96 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 96 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 96 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 96 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 96 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18984000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18984000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18984000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18984000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18984000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18984000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69284.671533 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69284.671533 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69284.671533 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69284.671533 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69284.671533 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69284.671533 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 167.756635 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 162.651714 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 344 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005814 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 336 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005952 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 134.530220 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.226414 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004106 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001014 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005120 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 131.033866 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.617848 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003999 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004964 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits @@ -540,61 +597,61 @@ system.cpu.l2cache.demand_hits::total 2 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 345 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 337 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60303.030303 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54262.318841 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54629.870130 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54629.870130 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52833.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57248.251748 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54329.383886 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52833.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57248.251748 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54329.383886 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.992958 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995192 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.992958 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995192 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68494.505495 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76796.875000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70071.216617 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70370.129870 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70370.129870 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68494.505495 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73287.234043 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70126.811594 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68494.505495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73287.234043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70126.811594 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,154 +660,154 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8307000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8307000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4438000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4438000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12745000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12745000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12745000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12745000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1616 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1616 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses +system.cpu.dcache.overall_misses::total 208 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9350500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9350500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5649500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5649500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15000000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15000000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15000000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15000000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1607 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1607 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084158 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.084158 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2542 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2542 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2542 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2542 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081518 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081518 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.083497 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.083497 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.083497 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.083497 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61080.882353 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61080.882353 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57636.363636 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57636.363636 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59835.680751 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59835.680751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59835.680751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59835.680751 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.081825 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081825 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081825 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081825 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71377.862595 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71377.862595 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73370.129870 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73370.129870 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72115.384615 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72115.384615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72115.384615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72115.384615 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.400000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4057000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4057000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4284000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4284000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8341000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8341000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5495500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5495500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10484500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10484500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10484500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10484500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040448 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040448 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60552.238806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60552.238806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55636.363636 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55636.363636 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57923.611111 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57923.611111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57923.611111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57923.611111 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055862 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055862 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76753.846154 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76753.846154 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71370.129870 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71370.129870 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index d96944a1a..3b513d323 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1266607302 # Wr system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 12304541407 # Throughput (bytes/s) +system.membus.data_through_bus 69090 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 11231 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 496e32aca..7844ef634 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -27,6 +27,25 @@ system.physmem.bw_inst_read::total 512306933 # In system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 814726003 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 282 # Transaction distribution +system.membus.trans_dist::ReadResp 282 # Transaction distribution +system.membus.trans_dist::ReadExReq 79 # Transaction distribution +system.membus.trans_dist::ReadExResp 79 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 23104 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.5 # Layer utilization (%) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 56716 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -351,5 +370,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 456 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 268 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 724 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 14592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 23168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- |