diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/quick/se/00.hello | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/quick/se/00.hello')
10 files changed, 5355 insertions, 3775 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 062194e2a..ecf052997 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21628500 # Number of ticks simulated -final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 19841500 # Number of ticks simulated +final_tick 19841500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34038 # Simulator instruction rate (inst/s) -host_op_rate 34033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115179622 # Simulator tick rate (ticks/s) -host_mem_usage 212112 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 31060 # Simulator instruction rate (inst/s) +host_op_rate 31057 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96425663 # Simulator tick rate (ticks/s) +host_mem_usage 216044 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::total 30016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 29952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19200 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 890676653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 497121853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1387798507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 890676653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 890676653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 890676653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 497121853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1387798507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 468 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 967668775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 541894514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1509563289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 967668775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 967668775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 967668775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 541894514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1509563289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 469 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 29952 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 69 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 66 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 19827000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 469 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1719468 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11463468 # Sum of mem lat for all requests +system.physmem.totBusLat 1876000 # Total cycles spent in databus access +system.physmem.totBankLat 7868000 # Total cycles spent in bank access +system.physmem.avgQLat 3666.24 # Average queueing delay per request +system.physmem.avgBankLat 16776.12 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24442.36 # Average memory access latency +system.physmem.avgRdBW 1509.56 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1509.56 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.43 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 401 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42275.05 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +218,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 43258 # number of cpu cycles simulated +system.cpu.numCycles 39684 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1606 # Number of BP lookups @@ -90,12 +248,12 @@ system.cpu.execution_unit.executions 4463 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11913 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 526 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35855 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7403 # Number of cycles cpu stages are processed. -system.cpu.activity 17.113597 # Percentage of cycles cpu is active +system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32282 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7402 # Number of cycles cpu stages are processed. +system.cpu.activity 18.652354 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -107,72 +265,72 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 6.769640 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.210329 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.769640 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147718 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.210329 # CPI: Total CPI of All Threads +system.cpu.ipc 0.161022 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147718 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 38346 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.161022 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34772 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.355125 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 39380 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 12.377784 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35806 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.964816 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 39087 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.642147 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41918 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 9.772200 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 35512 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4172 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 10.513053 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 38344 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.097693 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38800 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.376676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35226 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.305608 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 11.233747 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.677886 # Cycle average of tags in use -system.cpu.icache.total_refs 557 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 142.150123 # Cycle average of tags in use +system.cpu.icache.total_refs 558 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.677886 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 557 # number of overall hits -system.cpu.icache.overall_hits::total 557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses -system.cpu.icache.overall_misses::total 351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19444500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19444500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19444500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19444500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19444500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19444500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 142.150123 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069409 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069409 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits +system.cpu.icache.overall_hits::total 558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17305000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17305000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17305000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17305000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17305000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17305000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386564 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.386564 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55397.435897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55397.435897 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49442.857143 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49442.857143 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49442.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49442.857143 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,46 +339,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 49 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 49 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 49 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 49 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16495000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16495000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16495000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16495000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16495000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16495000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14791500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14791500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14791500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14791500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14791500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14791500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54619.205298 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54619.205298 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48978.476821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48978.476821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.512660 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 104.047429 # Cycle average of tags in use system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.512660 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025028 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025028 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 104.047429 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025402 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits @@ -237,14 +395,14 @@ system.cpu.dcache.demand_misses::cpu.data 348 # n system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses system.cpu.dcache.overall_misses::total 348 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5810500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5810500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13883000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13883000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19693500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19693500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19693500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19693500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11296500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11296500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16650500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16650500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16650500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16650500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -261,20 +419,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.169922 system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59902.061856 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59902.061856 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55310.756972 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55310.756972 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55195.876289 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55195.876289 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45005.976096 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45005.976096 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47846.264368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47846.264368 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2586 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 91.351351 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 69.891892 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits @@ -293,14 +451,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9608500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9608500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9608500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9608500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8525500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8525500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8525500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8525500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -309,26 +467,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58021.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58021.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53457.894737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53457.894737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47219.178082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47219.178082 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 194.915514 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.193487 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.751655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.163860 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001714 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005948 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.245680 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.947807 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006079 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -346,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16176500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5410500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21587000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4019000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4019000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16176500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9429500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25606000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16176500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9429500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25606000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14473000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19450000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3369500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3369500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8346500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22819500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14473000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8346500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22819500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -379,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53742.524917 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56952.631579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54512.626263 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55054.794521 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55054.794521 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54597.014925 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54597.014925 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48083.056478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52389.473684 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49116.161616 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46157.534247 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46157.534247 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 48655.650320 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 48655.650320 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12511500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4259000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16770500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3141000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3141000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12511500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19911500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12511500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19911500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10688499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3791620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14480119 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2447596 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2447596 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10688499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6239216 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16927715 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10688499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6239216 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16927715 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -431,17 +589,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41566.445183 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44831.578947 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42349.747475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43027.397260 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43027.397260 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35509.963455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39911.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36565.957071 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33528.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33528.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 1c9a49b18..d5736f11f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,210 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12394500 # Number of ticks simulated -final_tick 12394500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11568000 # Number of ticks simulated +final_tick 11568000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52290 # Simulator instruction rate (inst/s) -host_op_rate 52282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101684511 # Simulator tick rate (ticks/s) -host_mem_usage 219660 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 27765 # Simulator instruction rate (inst/s) +host_op_rate 27764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50400871 # Simulator tick rate (ticks/s) +host_mem_usage 217072 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11328 # Number of bytes read from this memory -system.physmem.bytes_read::total 31296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 177 # Number of read requests responded to by this memory -system.physmem.num_reads::total 489 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1611037154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 913953770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2524990923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1611037154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1611037154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1611037154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 913953770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2524990923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory +system.physmem.bytes_read::total 31104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory +system.physmem.num_reads::total 486 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1731673582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 957123098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2688796680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1731673582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1731673582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1731673582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 957123098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2688796680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 486 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 31104 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 11441000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 486 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3089486 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12593486 # Sum of mem lat for all requests +system.physmem.totBusLat 1944000 # Total cycles spent in databus access +system.physmem.totBankLat 7560000 # Total cycles spent in bank access +system.physmem.avgQLat 6356.97 # Average queueing delay per request +system.physmem.avgBankLat 15555.56 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25912.52 # Average memory access latency +system.physmem.avgRdBW 2688.80 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2688.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 16.80 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.09 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 416 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 23541.15 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1990 # DTB read hits -system.cpu.dtb.read_misses 56 # DTB read misses +system.cpu.dtb.read_hits 1960 # DTB read hits +system.cpu.dtb.read_misses 58 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2046 # DTB read accesses -system.cpu.dtb.write_hits 1084 # DTB write hits -system.cpu.dtb.write_misses 30 # DTB write misses +system.cpu.dtb.read_accesses 2018 # DTB read accesses +system.cpu.dtb.write_hits 1076 # DTB write hits +system.cpu.dtb.write_misses 32 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1114 # DTB write accesses -system.cpu.dtb.data_hits 3074 # DTB hits -system.cpu.dtb.data_misses 86 # DTB misses +system.cpu.dtb.write_accesses 1108 # DTB write accesses +system.cpu.dtb.data_hits 3036 # DTB hits +system.cpu.dtb.data_misses 90 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3160 # DTB accesses -system.cpu.itb.fetch_hits 2336 # ITB hits +system.cpu.dtb.data_accesses 3126 # DTB accesses +system.cpu.itb.fetch_hits 2261 # ITB hits system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2374 # ITB accesses +system.cpu.itb.fetch_accesses 2299 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,244 +218,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24790 # number of cpu cycles simulated +system.cpu.numCycles 23137 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2873 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 545 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2164 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits +system.cpu.BPredUnit.lookups 2774 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1638 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 514 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2124 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 769 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8141 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16442 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1200 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1838 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 885 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 405 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7948 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15915 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2774 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1174 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2854 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1765 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 730 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 739 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2336 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175940 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.562615 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2261 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.177755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.562670 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11043 78.98% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 296 2.12% 81.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 231 1.65% 82.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 234 1.67% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 276 1.97% 86.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 200 1.43% 87.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 274 1.96% 89.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 190 1.36% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1238 8.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10659 78.88% 78.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 293 2.17% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 218 1.61% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 238 1.76% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 276 2.04% 86.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 191 1.41% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 258 1.91% 89.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.30% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1205 8.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115894 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.663251 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9096 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 904 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2739 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1171 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 257 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 89 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15180 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1171 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9315 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 364 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2589 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 284 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14415 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 250 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10802 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18056 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18039 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119895 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.687859 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8886 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 751 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2667 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1129 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 236 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 88 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14776 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1129 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9097 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 177 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2538 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 227 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14039 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10509 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17564 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17547 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6232 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 728 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2652 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 5939 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 34 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 671 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2611 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1355 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12813 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10578 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6130 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13982 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.756544 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.394074 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10392 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3411 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.769037 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.410550 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9591 68.60% 68.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1568 11.21% 79.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1143 8.17% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 728 5.21% 93.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 479 3.43% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 273 1.95% 98.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 154 1.10% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33 0.24% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9295 68.79% 68.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1391 10.29% 79.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1141 8.44% 87.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 752 5.57% 93.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 3.45% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 269 1.99% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 153 1.13% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 32 0.24% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13513 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 8.70% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 56.52% 65.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 40 34.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 9.57% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 56.52% 66.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 33.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7162 67.71% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2248 21.25% 89.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1163 10.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7044 67.78% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2192 21.09% 88.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1151 11.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10578 # Type of FU issued -system.cpu.iq.rate 0.426704 # Inst issue rate +system.cpu.iq.FU_type_0::total 10392 # Type of FU issued +system.cpu.iq.rate 0.449151 # Inst issue rate system.cpu.iq.fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010872 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35279 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18978 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9581 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.011066 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34450 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18472 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9469 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10680 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10494 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1469 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 490 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1171 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12931 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2652 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1129 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2611 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1355 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 151 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 403 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 554 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9992 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2057 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 586 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 142 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 377 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9865 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2029 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 527 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88 # number of nop insts executed -system.cpu.iew.exec_refs 3174 # number of memory reference insts executed -system.cpu.iew.exec_branches 1621 # Number of branches executed -system.cpu.iew.exec_stores 1117 # Number of stores executed -system.cpu.iew.exec_rate 0.403066 # Inst execution rate -system.cpu.iew.wb_sent 9749 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9591 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5054 # num instructions producing a value -system.cpu.iew.wb_consumers 6863 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 3139 # number of memory reference insts executed +system.cpu.iew.exec_branches 1600 # Number of branches executed +system.cpu.iew.exec_stores 1110 # Number of stores executed +system.cpu.iew.exec_rate 0.426373 # Inst execution rate +system.cpu.iew.wb_sent 9638 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9479 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5022 # num instructions producing a value +system.cpu.iew.wb_consumers 6814 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.386890 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736413 # average fanout of values written-back +system.cpu.iew.wb_rate 0.409690 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737012 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6541 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6282 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12811 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.498712 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314684 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 432 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12384 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.515908 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.366435 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10031 78.30% 78.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1473 11.50% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 525 4.10% 93.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 241 1.88% 95.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.28% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 92 0.72% 97.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 108 0.84% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 98.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 140 1.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9732 78.59% 78.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1344 10.85% 89.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 509 4.11% 93.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 223 1.80% 95.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 188 1.52% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 75 0.61% 97.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 105 0.85% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 63 0.51% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 145 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12811 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12384 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -308,70 +466,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 140 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25250 # The number of ROB reads -system.cpu.rob.rob_writes 27045 # The number of ROB writes -system.cpu.timesIdled 255 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10808 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24559 # The number of ROB reads +system.cpu.rob.rob_writes 26483 # The number of ROB writes +system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9624 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 3.890458 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.890458 # CPI: Total CPI of All Threads -system.cpu.ipc 0.257039 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.257039 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12699 # number of integer regfile reads -system.cpu.int_regfile_writes 7211 # number of integer regfile writes +system.cpu.cpi 3.631042 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.631042 # CPI: Total CPI of All Threads +system.cpu.ipc 0.275403 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.275403 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12554 # number of integer regfile reads +system.cpu.int_regfile_writes 7112 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 158.537993 # Cycle average of tags in use -system.cpu.icache.total_refs 1881 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.009585 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 160.502909 # Cycle average of tags in use +system.cpu.icache.total_refs 1827 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.818471 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 158.537993 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077411 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077411 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1881 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1881 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1881 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1881 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1881 # number of overall hits -system.cpu.icache.overall_hits::total 1881 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses -system.cpu.icache.overall_misses::total 455 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15830500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15830500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15830500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15830500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15830500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15830500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2336 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2336 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2336 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2336 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194777 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194777 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194777 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194777 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194777 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194777 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34792.307692 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34792.307692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34792.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34792.307692 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 160.502909 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078371 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078371 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1827 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1827 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1827 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1827 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1827 # number of overall hits +system.cpu.icache.overall_hits::total 1827 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 434 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 434 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 434 # number of overall misses +system.cpu.icache.overall_misses::total 434 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13420000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13420000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13420000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13420000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13420000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13420000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2261 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2261 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2261 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2261 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2261 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2261 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191950 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.191950 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.191950 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.191950 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.191950 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.191950 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30921.658986 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30921.658986 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30921.658986 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30921.658986 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30921.658986 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30921.658986 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,94 +538,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 142 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 142 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11526000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11526000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11526000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11526000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133990 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.133990 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.133990 # 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number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 120 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10333000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10333000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10333000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10333000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10333000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10333000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138877 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138877 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138877 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32907.643312 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32907.643312 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32907.643312 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32907.643312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32907.643312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32907.643312 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.969871 # Cycle average of tags in use -system.cpu.dcache.total_refs 2254 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 177 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.734463 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.685258 # Cycle average of tags in use +system.cpu.dcache.total_refs 2236 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.924855 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.969871 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026360 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026360 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1748 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1748 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2254 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2254 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2254 # number of overall hits -system.cpu.dcache.overall_hits::total 2254 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 527 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 527 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 527 # number of overall misses -system.cpu.dcache.overall_misses::total 527 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6365000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6365000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12897000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12897000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19262000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19262000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19262000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19262000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1916 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1916 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 107.685258 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026290 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026290 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1732 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1732 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 504 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 504 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits +system.cpu.dcache.overall_hits::total 2236 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 158 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 158 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 361 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 361 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 519 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 519 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 519 # number of overall misses +system.cpu.dcache.overall_misses::total 519 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6015000 # 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number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2781 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2781 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2781 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2781 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087683 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087683 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.189500 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.189500 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.189500 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.189500 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37886.904762 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37886.904762 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35924.791086 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35924.791086 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36550.284630 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36550.284630 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2755 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2755 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2755 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2755 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083598 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083598 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.417341 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.188385 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188385 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188385 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188385 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38069.620253 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38069.620253 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26717.451524 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26717.451524 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.410405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30173.410405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.410405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30173.410405 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,119 +634,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # 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average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39513.698630 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40822.033898 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 40822.033898 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40822.033898 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 40822.033898 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 289 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 289 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 346 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 60.914522 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004838 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001859 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006697 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 160.499801 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 60.322135 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004898 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006739 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # 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average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38472.602740 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38472.602740 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35927.884615 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39748.587571 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37310.838446 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35927.884615 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39748.587571 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37310.838446 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41310 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8904460 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3801580 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12706040 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2007032 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2007032 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8904460 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5808612 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14713072 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8904460 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5808612 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14713072 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997959 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997959 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32733.974359 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37548.076923 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33937.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35301.369863 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35301.369863 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28448.753994 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38015.800000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30765.230024 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 27493.589041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27493.589041 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 7f4e477cc..d5e0f20d7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7079000 # Number of ticks simulated -final_tick 7079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 6408000 # Number of ticks simulated +final_tick 6408000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 8209 # Simulator instruction rate (inst/s) -host_op_rate 8209 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24342914 # Simulator tick rate (ticks/s) -host_mem_usage 218360 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 494 # Simulator instruction rate (inst/s) +host_op_rate 494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1327192 # Simulator tick rate (ticks/s) +host_mem_usage 215760 # Number of bytes of host memory used +host_seconds 4.83 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,34 +19,192 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1699675095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 768470123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2468145218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1699675095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1699675095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1699675095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 768470123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2468145218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1877652934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 848938826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2726591760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1877652934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1877652934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1877652934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 848938826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2726591760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 273 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 17472 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 6357500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 273 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1341773 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7053773 # Sum of mem lat for all requests +system.physmem.totBusLat 1092000 # Total cycles spent in databus access +system.physmem.totBankLat 4620000 # Total cycles spent in bank access +system.physmem.avgQLat 4914.92 # Average queueing delay per request +system.physmem.avgBankLat 16923.08 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25838.00 # Average memory access latency +system.physmem.avgRdBW 2726.59 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2726.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 17.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.10 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 229 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.88 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 23287.55 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 712 # DTB read hits -system.cpu.dtb.read_misses 34 # DTB read misses +system.cpu.dtb.read_hits 718 # DTB read hits +system.cpu.dtb.read_misses 36 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 746 # DTB read accesses -system.cpu.dtb.write_hits 367 # DTB write hits -system.cpu.dtb.write_misses 20 # DTB write misses +system.cpu.dtb.read_accesses 754 # DTB read accesses +system.cpu.dtb.write_hits 382 # DTB write hits +system.cpu.dtb.write_misses 24 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 387 # DTB write accesses -system.cpu.dtb.data_hits 1079 # DTB hits -system.cpu.dtb.data_misses 54 # DTB misses +system.cpu.dtb.write_accesses 406 # DTB write accesses +system.cpu.dtb.data_hits 1100 # DTB hits +system.cpu.dtb.data_misses 60 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1133 # DTB accesses -system.cpu.itb.fetch_hits 1015 # ITB hits +system.cpu.dtb.data_accesses 1160 # DTB accesses +system.cpu.itb.fetch_hits 1042 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1045 # ITB accesses +system.cpu.itb.fetch_accesses 1072 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,244 +218,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 14159 # number of cpu cycles simulated +system.cpu.numCycles 12817 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1131 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 255 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 792 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits +system.cpu.BPredUnit.lookups 1162 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 576 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 259 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 820 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 228 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 213 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4177 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6936 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 432 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 862 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 243 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 224 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 4082 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7077 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1162 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 261 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 902 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1015 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7112 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.975253 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.397370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 857 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1042 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.004827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.418564 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5922 83.27% 83.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 52 0.73% 84.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 129 1.81% 85.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100 1.41% 87.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 139 1.95% 89.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63 0.89% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 67 0.94% 91.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 67 0.94% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 573 8.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5820 82.64% 82.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52 0.74% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 133 1.89% 85.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 101 1.43% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 157 2.23% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 70 0.99% 89.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 69 0.98% 90.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.91% 91.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 577 8.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7112 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.079879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.489865 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5180 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1148 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 503 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 169 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6175 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 503 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5278 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 59 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 172 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1058 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5909 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 15 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4299 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6685 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6673 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 7043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090661 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.552157 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5035 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 297 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1173 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 523 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 176 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 84 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6290 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 301 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 523 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5140 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 24 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 214 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1083 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 59 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 6004 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4336 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6797 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6785 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2531 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2568 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 136 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 172 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 984 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 506 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5173 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4054 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4204 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2615 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1486 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7112 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.570022 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.279366 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7043 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.596905 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.307061 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5467 76.87% 76.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 597 8.39% 85.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 392 5.51% 90.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.70% 94.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 194 2.73% 97.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 122 1.72% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 53 0.75% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12 0.17% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5344 75.88% 75.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 621 8.82% 84.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 394 5.59% 90.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 268 3.81% 94.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 205 2.91% 97.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 132 1.87% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 55 0.78% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11 0.16% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7112 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7043 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 4.65% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18 41.86% 46.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.26% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 46.81% 51.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 48.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2869 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 786 19.39% 90.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 398 9.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2977 70.81% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 808 19.22% 90.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 418 9.94% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4054 # Type of FU issued -system.cpu.iq.rate 0.286320 # Inst issue rate -system.cpu.iq.fu_busy_cnt 43 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010607 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7459 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3702 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4204 # Type of FU issued +system.cpu.iq.rate 0.328002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 47 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011180 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15542 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7792 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3821 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4090 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4244 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 569 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 182 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 212 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 503 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 46 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5379 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 523 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5532 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 984 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 506 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 154 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 211 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3894 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 747 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 160 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 221 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 4011 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 193 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 342 # number of nop insts executed -system.cpu.iew.exec_refs 1134 # number of memory reference insts executed -system.cpu.iew.exec_branches 652 # Number of branches executed -system.cpu.iew.exec_stores 387 # Number of stores executed -system.cpu.iew.exec_rate 0.275019 # Inst execution rate -system.cpu.iew.wb_sent 3793 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3708 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1740 # num instructions producing a value -system.cpu.iew.wb_consumers 2258 # num instructions consuming a value +system.cpu.iew.exec_nop 353 # number of nop insts executed +system.cpu.iew.exec_refs 1161 # number of memory reference insts executed +system.cpu.iew.exec_branches 678 # Number of branches executed +system.cpu.iew.exec_stores 406 # Number of stores executed +system.cpu.iew.exec_rate 0.312944 # Inst execution rate +system.cpu.iew.wb_sent 3922 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3827 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1795 # num instructions producing a value +system.cpu.iew.wb_consumers 2353 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.261883 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.770593 # average fanout of values written-back +system.cpu.iew.wb_rate 0.298588 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762856 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2798 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2928 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 175 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6609 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.389772 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.242894 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.395092 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.243251 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5727 86.65% 86.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 217 3.28% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 312 4.72% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 115 1.74% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 67 1.01% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.80% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 34 0.51% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 19 0.29% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 65 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5631 86.37% 86.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 221 3.39% 89.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 313 4.80% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 120 1.84% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 64 0.98% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 55 0.84% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 34 0.52% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22 0.34% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 60 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6520 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -308,69 +466,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 65 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11671 # The number of ROB reads -system.cpu.rob.rob_writes 11260 # The number of ROB writes -system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7047 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11717 # The number of ROB reads +system.cpu.rob.rob_writes 11541 # The number of ROB writes +system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5774 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.931713 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.931713 # CPI: Total CPI of All Threads -system.cpu.ipc 0.168585 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.168585 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4712 # number of integer regfile reads -system.cpu.int_regfile_writes 2874 # number of integer regfile writes +system.cpu.cpi 5.369501 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.369501 # CPI: Total CPI of All Threads +system.cpu.ipc 0.186237 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.186237 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4858 # number of integer regfile reads +system.cpu.int_regfile_writes 2964 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 93.783034 # Cycle average of tags in use -system.cpu.icache.total_refs 767 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 92.000483 # Cycle average of tags in use +system.cpu.icache.total_refs 799 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.079787 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.250000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 93.783034 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045792 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045792 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 767 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 767 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 767 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 767 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 767 # number of overall hits -system.cpu.icache.overall_hits::total 767 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses -system.cpu.icache.overall_misses::total 248 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 9016000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 9016000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 9016000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 9016000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 9016000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 9016000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1015 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1015 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1015 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1015 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1015 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1015 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244335 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.244335 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.244335 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.244335 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.244335 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.244335 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36354.838710 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36354.838710 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36354.838710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36354.838710 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 92.000483 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.044922 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.044922 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 799 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 799 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 799 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 799 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 799 # number of overall hits +system.cpu.icache.overall_hits::total 799 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 243 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 243 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 243 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 243 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 243 # number of overall misses +system.cpu.icache.overall_misses::total 243 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 7449000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 7449000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 7449000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 7449000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 7449000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 7449000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1042 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233205 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.233205 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.233205 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.233205 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.233205 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.233205 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30654.320988 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30654.320988 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30654.320988 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30654.320988 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30654.320988 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30654.320988 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,94 +537,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 55 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 55 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 55 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # 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number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185222 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.185222 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.185222 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36960.106383 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36960.106383 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5938000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5938000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5938000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5938000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5938000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5938000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.180422 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.180422 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.180422 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31585.106383 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31585.106383 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31585.106383 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 31585.106383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31585.106383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 31585.106383 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.970482 # Cycle average of tags in use -system.cpu.dcache.total_refs 773 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 44.834744 # Cycle average of tags in use +system.cpu.dcache.total_refs 777 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.094118 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.141176 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.970482 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011223 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011223 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 560 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 560 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 44.834744 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.010946 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.010946 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 564 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 564 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 773 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 773 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 773 # number of overall hits -system.cpu.dcache.overall_hits::total 773 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 777 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 777 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 777 # number of overall hits +system.cpu.dcache.overall_hits::total 777 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 120 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 120 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses -system.cpu.dcache.overall_misses::total 202 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4078500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4078500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3119500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3119500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7198000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7198000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7198000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7198000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 681 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 681 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 201 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 201 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 201 # number of overall misses +system.cpu.dcache.overall_misses::total 201 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3706500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3706500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2874500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2874500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6581000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6581000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6581000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6581000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 684 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 684 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 975 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 975 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 975 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 975 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.177680 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.177680 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 978 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 978 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 978 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 978 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.175439 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.175439 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.207179 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.207179 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.207179 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.207179 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33706.611570 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33706.611570 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38512.345679 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38512.345679 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35633.663366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35633.663366 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.205521 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.205521 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.205521 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.205521 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30887.500000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30887.500000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35487.654321 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35487.654321 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32741.293532 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32741.293532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32741.293532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32741.293532 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,14 +633,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 117 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 117 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 117 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 116 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 116 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 116 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -491,42 +649,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2530500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2530500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 981500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3512000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3512000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3512000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3512000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089574 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089574 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 953500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 953500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3370500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3370500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3370500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3370500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089181 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087179 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087179 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41483.606557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41483.606557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40895.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40895.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086912 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.086912 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086912 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.086912 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39622.950820 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39622.950820 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39652.941176 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 39652.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39652.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 39652.941176 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 122.770960 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 120.198004 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.868144 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.902816 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002865 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000882 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003747 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 92.103751 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.094254 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002811 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000857 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -538,17 +696,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6760000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2469500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9229500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 956000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 956000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3425500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10185500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6760000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3425500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10185500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 5749500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8105500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 928000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 928000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 5749500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3284000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9033500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 5749500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3284000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9033500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -571,17 +729,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35957.446809 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40483.606557 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 37066.265060 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39833.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39833.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40300 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37309.523810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40300 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37309.523810 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 30582.446809 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38622.950820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 32552.208835 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 30582.446809 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38635.294118 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 33089.743590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 30582.446809 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38635.294118 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 33089.743590 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,17 +759,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6157500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2280500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8438000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 881500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 881500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6157500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3162000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9319500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6157500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3162000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9319500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5087760 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2153056 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7240816 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 847024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5087760 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3000080 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8087840 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5087760 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3000080 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8087840 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -623,17 +781,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32752.659574 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37385.245902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33887.550201 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36729.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36729.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 27062.553191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29079.582329 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35292.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35292.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 27062.553191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35295.058824 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29625.787546 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 27062.553191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35295.058824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29625.787546 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index cbe28c826..122d34e0f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10412000 # Number of ticks simulated -final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10062000 # Number of ticks simulated +final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32172 # Simulator instruction rate (inst/s) -host_op_rate 40134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72868464 # Simulator tick rate (ticks/s) -host_mem_usage 233868 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 57856 # Simulator instruction rate (inst/s) +host_op_rate 72170 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 126623534 # Simulator tick rate (ticks/s) +host_mem_usage 231188 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory -system.physmem.bytes_read::total 25600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory +system.physmem.bytes_read::total 25472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory +system.physmem.num_reads::total 398 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1755515802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 775988869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2531504671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1755515802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1755515802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1755515802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 775988869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2531504671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 398 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25472 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 10004500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 398 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2567898 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests +system.physmem.totBusLat 1592000 # Total cycles spent in databus access +system.physmem.totBankLat 6552000 # Total cycles spent in bank access +system.physmem.avgQLat 6452.01 # Average queueing delay per request +system.physmem.avgBankLat 16462.31 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26914.32 # Average memory access latency +system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.82 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.06 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 323 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 25136.93 # Average gap between requests system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -115,243 +273,243 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 20825 # number of cpu cycles simulated +system.cpu.numCycles 20125 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2492 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits +system.cpu.BPredUnit.lookups 2519 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2432 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2229 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2441 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2242 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 47 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 46 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8838 # Type of FU issued -system.cpu.iq.rate 0.424394 # Inst issue rate -system.cpu.iq.fu_busy_cnt 221 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8888 # Type of FU issued +system.cpu.iq.rate 0.441640 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3246 # number of memory reference insts executed -system.cpu.iew.exec_branches 1415 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.404994 # Inst execution rate -system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7997 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3850 # num instructions producing a value -system.cpu.iew.wb_consumers 7766 # num instructions consuming a value +system.cpu.iew.exec_refs 3261 # number of memory reference insts executed +system.cpu.iew.exec_branches 1428 # Number of branches executed +system.cpu.iew.exec_stores 1173 # Number of stores executed +system.cpu.iew.exec_rate 0.421615 # Inst execution rate +system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8062 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3862 # num instructions producing a value +system.cpu.iew.wb_consumers 7771 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back +system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 166 1.46% 98.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.49% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 36 0.32% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 114 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11403 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -362,69 +520,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22290 # The number of ROB reads -system.cpu.rob.rob_writes 23328 # The number of ROB writes -system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22426 # The number of ROB reads +system.cpu.rob.rob_writes 23541 # The number of ROB writes +system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7781 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads -system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 38756 # number of integer regfile reads -system.cpu.int_regfile_writes 7886 # number of integer regfile writes +system.cpu.cpi 4.378808 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.378808 # CPI: Total CPI of All Threads +system.cpu.ipc 0.228373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.228373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39006 # number of integer regfile reads +system.cpu.int_regfile_writes 7962 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15116 # number of misc regfile reads +system.cpu.misc_regfile_reads 15230 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use -system.cpu.icache.total_refs 1564 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 152.520984 # Cycle average of tags in use +system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.396610 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits -system.cpu.icache.overall_hits::total 1564 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 152.520984 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074473 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074473 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits +system.cpu.icache.overall_hits::total 1592 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 358 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 358 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 358 # number of overall misses +system.cpu.icache.overall_misses::total 358 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11241000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11241000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11241000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11241000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11241000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11241000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183590 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183590 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183590 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183590 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183590 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183590 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31399.441341 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31399.441341 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31399.441341 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31399.441341 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,110 +591,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 72 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.153209 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35204.391892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35204.391892 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9141000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.151282 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.151282 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.151282 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30986.440678 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30986.440678 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use -system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.982117 # Cycle average of tags in use +system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.986301 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.982117 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021480 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021480 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1717 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1717 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits -system.cpu.dcache.overall_hits::total 2306 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2309 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2309 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2309 # number of overall hits +system.cpu.dcache.overall_hits::total 2309 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 185 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 185 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 321 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 321 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 506 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 506 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 506 # number of overall misses +system.cpu.dcache.overall_misses::total 506 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5690000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5690000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10922000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 53000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 53000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16612000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16612000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16612000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16612000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1902 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2815 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2815 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2815 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2815 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097266 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097266 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.351588 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.351588 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.179751 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.179751 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.179751 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.179751 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30756.756757 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30756.756757 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34024.922118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34024.922118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32830.039526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32830.039526 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -547,58 +705,58 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5249000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5249000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055409 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055409 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3250000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3250000 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40152.941176 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 37115.384615 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39452.380952 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39452.380952 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37357.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37357.142857 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942373 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39615.079365 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34196.782178 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31741.007194 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39615.079365 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34196.782178 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,50 +838,50 @@ system.cpu.l2cache.demand_mshr_hits::total 6 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9207000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12243500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9207000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4564000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13771000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9207000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4564000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13771000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.771429 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892768 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7843874 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2768060 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10611934 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1736536 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1736536 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7843874 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4504596 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12348470 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7843874 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4504596 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12348470 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.769231 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892231 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28419.833333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34600.750000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29808.803371 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41346.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41346.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 4110b4ea0..f60a54b23 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10412000 # Number of ticks simulated -final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10062000 # Number of ticks simulated +final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40558 # Simulator instruction rate (inst/s) -host_op_rate 50593 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91854675 # Simulator tick rate (ticks/s) -host_mem_usage 232720 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 70596 # Simulator instruction rate (inst/s) +host_op_rate 88057 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154493805 # Simulator tick rate (ticks/s) +host_mem_usage 230168 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory -system.physmem.bytes_read::total 25600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory +system.physmem.bytes_read::total 25472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory +system.physmem.num_reads::total 398 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1755515802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 775988869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2531504671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1755515802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1755515802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1755515802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 775988869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2531504671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 398 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25472 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 10004500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 398 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2567898 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests +system.physmem.totBusLat 1592000 # Total cycles spent in databus access +system.physmem.totBankLat 6552000 # Total cycles spent in bank access +system.physmem.avgQLat 6452.01 # Average queueing delay per request +system.physmem.avgBankLat 16462.31 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26914.32 # Average memory access latency +system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.82 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.06 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 323 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 25136.93 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,243 +228,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20825 # number of cpu cycles simulated +system.cpu.numCycles 20125 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2492 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits +system.cpu.BPredUnit.lookups 2519 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2432 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2229 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2441 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2242 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 47 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 46 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8838 # Type of FU issued -system.cpu.iq.rate 0.424394 # Inst issue rate -system.cpu.iq.fu_busy_cnt 221 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8888 # Type of FU issued +system.cpu.iq.rate 0.441640 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3246 # number of memory reference insts executed -system.cpu.iew.exec_branches 1415 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.404994 # Inst execution rate -system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7997 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3850 # num instructions producing a value -system.cpu.iew.wb_consumers 7766 # num instructions consuming a value +system.cpu.iew.exec_refs 3261 # number of memory reference insts executed +system.cpu.iew.exec_branches 1428 # Number of branches executed +system.cpu.iew.exec_stores 1173 # Number of stores executed +system.cpu.iew.exec_rate 0.421615 # Inst execution rate +system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8062 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3862 # num instructions producing a value +system.cpu.iew.wb_consumers 7771 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back +system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 166 1.46% 98.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.49% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 36 0.32% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 114 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11403 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -317,69 +475,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22290 # The number of ROB reads -system.cpu.rob.rob_writes 23328 # The number of ROB writes -system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22426 # The number of ROB reads +system.cpu.rob.rob_writes 23541 # The number of ROB writes +system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7781 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads -system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 38756 # number of integer regfile reads -system.cpu.int_regfile_writes 7886 # number of integer regfile writes +system.cpu.cpi 4.378808 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.378808 # CPI: Total CPI of All Threads +system.cpu.ipc 0.228373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.228373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39006 # number of integer regfile reads +system.cpu.int_regfile_writes 7962 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15116 # number of misc regfile reads +system.cpu.misc_regfile_reads 15230 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use -system.cpu.icache.total_refs 1564 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 152.520984 # Cycle average of tags in use +system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.396610 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits -system.cpu.icache.overall_hits::total 1564 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 152.520984 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074473 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074473 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits +system.cpu.icache.overall_hits::total 1592 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 358 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 358 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 358 # number of overall misses +system.cpu.icache.overall_misses::total 358 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11241000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11241000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11241000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11241000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11241000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11241000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183590 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183590 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183590 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183590 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183590 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183590 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31399.441341 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31399.441341 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31399.441341 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31399.441341 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,110 +546,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10420500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10420500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9141000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9141000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9141000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.151282 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.151282 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.151282 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30986.440678 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30986.440678 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use -system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.982117 # Cycle average of tags in use +system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.986301 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.982117 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021480 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021480 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1717 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1717 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits -system.cpu.dcache.overall_hits::total 2306 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2309 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2309 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2309 # number of overall hits +system.cpu.dcache.overall_hits::total 2309 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 185 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 185 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 321 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 321 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 506 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 506 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 506 # number of overall misses +system.cpu.dcache.overall_misses::total 506 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5690000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5690000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10922000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 53000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 53000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16612000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16612000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16612000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16612000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1902 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2815 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2815 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2815 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2815 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097266 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097266 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.351588 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.351588 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.179751 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.179751 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.179751 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.179751 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30756.756757 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30756.756757 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34024.922118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34024.922118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32830.039526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32830.039526 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,58 +660,58 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # 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mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28419.833333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34600.750000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29808.803371 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41346.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41346.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 04aaa0ff5..8aae2e3f0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20184000 # Number of ticks simulated -final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 19373000 # Number of ticks simulated +final_tick 19373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91753 # Simulator instruction rate (inst/s) -host_op_rate 91718 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 318298211 # Simulator tick rate (ticks/s) -host_mem_usage 212944 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 54522 # Simulator instruction rate (inst/s) +host_op_rate 54510 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 181593348 # Simulator tick rate (ticks/s) +host_mem_usage 216696 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1005152596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 437574316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1442726912 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1005152596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1005152596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1005152596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 437574316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1442726912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1047230682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455892221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1503122903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1047230682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1047230682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1047230682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455892221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1503122903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 455 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 29120 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 53 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 19298000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 455 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2404453 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12694453 # Sum of mem lat for all requests +system.physmem.totBusLat 1820000 # Total cycles spent in databus access +system.physmem.totBankLat 8470000 # Total cycles spent in bank access +system.physmem.avgQLat 5284.51 # Average queueing delay per request +system.physmem.avgBankLat 18615.38 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27899.90 # Average memory access latency +system.physmem.avgRdBW 1503.12 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1503.12 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.39 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.66 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 357 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42413.19 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,7 +204,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 40369 # number of cpu cycles simulated +system.cpu.numCycles 38747 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1146 # Number of BP lookups @@ -79,9 +237,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34984 # Number of cycles cpu's stages were not processed +system.cpu.idleCycles 33362 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5385 # Number of cycles cpu stages are processed. -system.cpu.activity 13.339444 # Percentage of cycles cpu is active +system.cpu.activity 13.897850 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -93,36 +251,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 6.943412 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.664431 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.943412 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144021 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.664431 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150050 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.144021 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 36744 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.150050 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 35122 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 8.979663 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 37547 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.355563 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35925 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 6.990513 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 37585 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.283145 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 35963 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 6.896381 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 39127 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.185072 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 37505 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.076618 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 37465 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.205409 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35843 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.193639 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.494774 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 147.108411 # Cycle average of tags in use +system.cpu.icache.tagsinuse 148.105671 # Cycle average of tags in use system.cpu.icache.total_refs 410 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.108411 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071830 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071830 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 148.105671 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072317 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072317 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits @@ -135,12 +293,12 @@ system.cpu.icache.demand_misses::cpu.inst 344 # n system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19298000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19298000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19298000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19298000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19298000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19298000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18000000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18000000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18000000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18000000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18000000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18000000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses @@ -153,18 +311,18 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.456233 system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56098.837209 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56098.837209 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56098.837209 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52325.581395 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52325.581395 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52325.581395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52325.581395 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 58 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 34 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits @@ -179,34 +337,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17456000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17456000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17456000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17456000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17456000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17456000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16448000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16448000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16448000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16448000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16448000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16448000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54721.003135 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54721.003135 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51561.128527 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51561.128527 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.235833 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.430963 # Cycle average of tags in use system.cpu.dcache.total_refs 1834 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.235833 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021786 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021786 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 89.430963 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021834 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021834 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1072 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1072 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits @@ -223,14 +381,14 @@ system.cpu.dcache.demand_misses::cpu.data 254 # n system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses system.cpu.dcache.overall_misses::total 254 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5402500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5402500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9244000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9244000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14646500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14646500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14646500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14646500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8188000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8188000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13685500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13685500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13685500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13685500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -247,20 +405,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.121648 system.cpu.dcache.demand_miss_rate::total 0.121648 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.121648 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.121648 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59368.131868 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59368.131868 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56711.656442 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56711.656442 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57663.385827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60412.087912 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60412.087912 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50233.128834 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 50233.128834 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53879.921260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53879.921260 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2389 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2069 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 103.869565 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.956522 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits @@ -279,14 +437,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2905000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2905000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8016000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8016000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8016000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8016000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5201000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5201000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7806000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7806000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7806000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7806000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -295,26 +453,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58747.126437 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58747.126437 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56960.784314 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56960.784314 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59781.609195 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59781.609195 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51078.431373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51078.431373 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 204.139180 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 205.347343 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 148.719836 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.419344 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004539 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006230 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 149.740781 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.606562 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004570 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001697 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006267 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -332,17 +490,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17110500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5017500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 22128000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2851000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2851000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 17110500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7868500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24979000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 17110500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7868500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24979000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16102500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5107500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21210000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2551000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2551000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16102500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7658500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23761000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16102500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7658500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23761000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -365,17 +523,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53976.340694 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57672.413793 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54772.277228 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55901.960784 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55901.960784 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54898.901099 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54898.901099 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50796.529968 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58706.896552 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50019.607843 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50019.607843 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52221.978022 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52221.978022 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +553,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13248500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17211000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2227500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2227500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13248500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6190000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19438500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13248500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6190000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19438500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12097521 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4026597 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16124118 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1915572 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1915572 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12097521 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5942169 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18039690 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12097521 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5942169 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18039690 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -417,17 +575,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41793.375394 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45545.977011 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42601.485149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43676.470588 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43676.470588 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38162.526814 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46282.724138 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39911.183168 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37560.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37560.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 1fd33095f..85090bc10 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12603500 # Number of ticks simulated -final_tick 12603500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12097500 # Number of ticks simulated +final_tick 12097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49943 # Simulator instruction rate (inst/s) -host_op_rate 49935 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 122043566 # Simulator tick rate (ticks/s) -host_mem_usage 220512 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 46391 # Simulator instruction rate (inst/s) +host_op_rate 46381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108798708 # Simulator tick rate (ticks/s) +host_mem_usage 217720 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory @@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 21696 # Nu system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 480 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1721426588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 715991590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2437418177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1721426588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1721426588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1721426588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 715991590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2437418177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1793428394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 745939244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2539367638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1793428394 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1793428394 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1793428394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 745939244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2539367638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 480 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30720 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 30720 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 30 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 12035000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 480 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3039980 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13667980 # Sum of mem lat for all requests +system.physmem.totBusLat 1920000 # Total cycles spent in databus access +system.physmem.totBankLat 8708000 # Total cycles spent in bank access +system.physmem.avgQLat 6333.29 # Average queueing delay per request +system.physmem.avgBankLat 18141.67 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28474.96 # Average memory access latency +system.physmem.avgRdBW 2539.37 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2539.37 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.87 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.13 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 380 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 25072.92 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,243 +204,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 25208 # number of cpu cycles simulated +system.cpu.numCycles 24196 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2076 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1377 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1640 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 471 # Number of BTB hits +system.cpu.BPredUnit.lookups 2174 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1443 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1705 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 494 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 262 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12782 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2076 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 733 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3147 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1298 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 705 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 283 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8516 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1345 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 699 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1923 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.958099 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.266693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 13523 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.974414 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.279455 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10194 76.41% 76.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1306 9.79% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 106 0.79% 86.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 141 1.06% 88.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 294 2.20% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 100 0.75% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 154 1.15% 92.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 127 0.95% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 919 6.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10263 75.89% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1359 10.05% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113 0.84% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 150 1.11% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 301 2.23% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 101 0.75% 90.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 159 1.18% 92.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 137 1.01% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 940 6.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.082355 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.507061 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8622 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 899 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2969 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11860 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 13523 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.089850 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.544594 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8657 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3079 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 844 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 154 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12246 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8807 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 544 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2833 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11360 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 96 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13521 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13517 # Number of integer rename lookups +system.cpu.rename.SquashCycles 844 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8855 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 196 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 599 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2928 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 101 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11668 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 92 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7112 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13873 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13869 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3542 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 277 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2388 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3714 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2456 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1189 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8869 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8060 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3246 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1840 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13341 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.604153 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.265993 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9092 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8231 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3471 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1958 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13523 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.608667 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.271089 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9853 73.86% 73.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1401 10.50% 84.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 847 6.35% 90.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 533 4.00% 94.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 353 2.65% 97.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 227 1.70% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 84 0.63% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.22% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9982 73.81% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1399 10.35% 84.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 867 6.41% 90.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 551 4.07% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 358 2.65% 97.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 239 1.77% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 85 0.63% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 28 0.21% 99.90% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13523 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 97 63.82% 65.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 2.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 95 63.33% 65.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 34.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4766 59.13% 59.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2195 27.23% 86.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1090 13.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4866 59.12% 59.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2254 27.38% 86.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1102 13.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8060 # Type of FU issued -system.cpu.iq.rate 0.319740 # Inst issue rate -system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018859 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29653 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12136 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7261 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8231 # Type of FU issued +system.cpu.iq.rate 0.340180 # Inst issue rate +system.cpu.iq.fu_busy_cnt 150 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018224 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30186 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12584 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7378 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8210 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8379 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1225 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1293 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 264 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 170 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 844 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10299 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2388 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2456 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1189 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 360 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7692 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2065 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 368 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 364 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7823 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2103 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1417 # number of nop insts executed -system.cpu.iew.exec_refs 3127 # number of memory reference insts executed -system.cpu.iew.exec_branches 1305 # Number of branches executed -system.cpu.iew.exec_stores 1062 # Number of stores executed -system.cpu.iew.exec_rate 0.305141 # Inst execution rate -system.cpu.iew.wb_sent 7351 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7263 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2827 # num instructions producing a value -system.cpu.iew.wb_consumers 4035 # num instructions consuming a value +system.cpu.iew.exec_nop 1455 # number of nop insts executed +system.cpu.iew.exec_refs 3177 # number of memory reference insts executed +system.cpu.iew.exec_branches 1335 # Number of branches executed +system.cpu.iew.exec_stores 1074 # Number of stores executed +system.cpu.iew.exec_rate 0.323318 # Inst execution rate +system.cpu.iew.wb_sent 7479 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7380 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2890 # num instructions producing a value +system.cpu.iew.wb_consumers 4129 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.288123 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.700620 # average fanout of values written-back +system.cpu.iew.wb_rate 0.305009 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.699927 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4478 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4740 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12537 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.463668 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.253066 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12679 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.458475 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.250836 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10143 80.90% 80.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 988 7.88% 88.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 634 5.06% 93.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 313 2.50% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.18% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 91 0.73% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 75 0.60% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.31% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10300 81.24% 81.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 973 7.67% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 629 4.96% 93.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 317 2.50% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.17% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 88 0.69% 98.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 75 0.59% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 43 0.34% 99.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12679 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,67 +453,67 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22709 # The number of ROB reads -system.cpu.rob.rob_writes 21393 # The number of ROB writes -system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11867 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23113 # The number of ROB reads +system.cpu.rob.rob_writes 21959 # The number of ROB writes +system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10673 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 4.889061 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.889061 # CPI: Total CPI of All Threads -system.cpu.ipc 0.204538 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.204538 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10482 # number of integer regfile reads -system.cpu.int_regfile_writes 5097 # number of integer regfile writes +system.cpu.cpi 4.692785 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.692785 # CPI: Total CPI of All Threads +system.cpu.ipc 0.213093 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.213093 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10646 # number of integer regfile reads +system.cpu.int_regfile_writes 5184 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 151 # number of misc regfile reads +system.cpu.misc_regfile_reads 155 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.691170 # Cycle average of tags in use -system.cpu.icache.total_refs 1486 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 162.253661 # Cycle average of tags in use +system.cpu.icache.total_refs 1552 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.345029 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.538012 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.691170 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078951 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078951 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1486 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1486 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1486 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1486 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1486 # number of overall hits -system.cpu.icache.overall_hits::total 1486 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses -system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15633000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15633000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15633000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15633000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15633000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15633000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1923 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1923 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1923 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1923 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227249 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.227249 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.227249 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.227249 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.227249 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.227249 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35773.455378 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35773.455378 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35773.455378 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35773.455378 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35773.455378 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35773.455378 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 162.253661 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079225 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079225 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1552 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1552 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1552 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1552 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1552 # number of overall hits +system.cpu.icache.overall_hits::total 1552 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 427 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 427 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 427 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 427 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 427 # number of overall misses +system.cpu.icache.overall_misses::total 427 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14343000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14343000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14343000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14343000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14343000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14343000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.215766 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.215766 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.215766 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.215766 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.215766 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.215766 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33590.163934 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33590.163934 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33590.163934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33590.163934 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,94 +522,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 85 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12431000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12431000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12431000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12431000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12431000 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36347.953216 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36347.953216 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36347.953216 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11802500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11802500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11802500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11802500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11802500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11802500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172815 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.172815 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.172815 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34510.233918 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34510.233918 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34510.233918 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34510.233918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34510.233918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34510.233918 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 90.751581 # Cycle average of tags in use -system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.817694 # Cycle average of tags in use +system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.085106 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 17.340426 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 90.751581 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022156 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022156 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1833 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1833 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 576 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2409 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2409 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2409 # number of overall hits -system.cpu.dcache.overall_hits::total 2409 # number of overall hits +system.cpu.dcache.occ_blocks::cpu.data 91.817694 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022416 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022416 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1868 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1868 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 577 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 577 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits +system.cpu.dcache.overall_hits::total 2445 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses -system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5432500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5432500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11660000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11660000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17092500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17092500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17092500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17092500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1982 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 348 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15425000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2017 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075177 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075177 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377297 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.377297 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.171311 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.171311 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.171311 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.171311 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36459.731544 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36459.731544 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33409.742120 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33409.742120 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34322.289157 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34322.289157 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2942 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2942 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2942 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2942 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073872 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.073872 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.376216 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.376216 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.168933 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.168933 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.168933 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.168933 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39704.697987 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39704.697987 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27324.712644 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27324.712644 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31036.217304 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31036.217304 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31036.217304 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31036.217304 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,12 +620,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 298 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 298 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 357 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 357 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 357 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 357 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 297 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 297 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -476,42 +634,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3834500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3834500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2072000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2072000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5906500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5906500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5906500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5906500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045409 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045409 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1859000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1859000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5691000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5691000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5691000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5691000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044621 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048504 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048504 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42605.555556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42605.555556 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047927 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047927 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42577.777778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42577.777778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36450.980392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36450.980392 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40361.702128 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 40361.702128 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40361.702128 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 40361.702128 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 220.970580 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.617700 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 163.825301 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.145280 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001744 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 164.369429 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.248271 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005016 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001778 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006794 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -529,17 +687,17 @@ system.cpu.l2cache.demand_misses::total 480 # nu system.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 480 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3740000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15824000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2020500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2020500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12084000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5760500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17844500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12084000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5760500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17844500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11455500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3737500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15193000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1807500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1807500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11455500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5545000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17000500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11455500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5545000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17000500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses) @@ -562,17 +720,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993789 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35646.017699 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41555.555556 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36885.780886 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39617.647059 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39617.647059 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37176.041667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37176.041667 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33792.035398 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41527.777778 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35414.918415 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35441.176471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 35441.176471 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 35417.708333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 35417.708333 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,17 +750,17 @@ system.cpu.l2cache.demand_mshr_misses::total 480 system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11000500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14466000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1861500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1861500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11000500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5327000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16327500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11000500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5327000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16327500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10252004 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3439074 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13691078 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1635054 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1635054 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10252004 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5074128 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15326132 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10252004 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5074128 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15326132 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses @@ -614,17 +772,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32449.852507 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38505.555556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33720.279720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30241.899705 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38211.933333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31913.934732 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32059.882353 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32059.882353 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 233f5f73b..3c312e713 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11490500 # Number of ticks simulated -final_tick 11490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 10184500 # Number of ticks simulated +final_tick 10184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46998 # Simulator instruction rate (inst/s) -host_op_rate 46991 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93211132 # Simulator tick rate (ticks/s) -host_mem_usage 217464 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 98086 # Simulator instruction rate (inst/s) +host_op_rate 98064 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172399568 # Simulator tick rate (ticks/s) +host_mem_usage 213936 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory -system.physmem.bytes_read::total 28992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 29056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory -system.physmem.num_reads::total 453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1955006310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 568121492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2523127801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1955006310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1955006310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1955006310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 568121492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2523127801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 454 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2211988807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 640974029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2852962836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2211988807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2211988807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2211988807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 640974029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2852962836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 454 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 454 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 29056 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 29056 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 49 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 10067000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 454 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2091454 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11313454 # Sum of mem lat for all requests +system.physmem.totBusLat 1816000 # Total cycles spent in databus access +system.physmem.totBankLat 7406000 # Total cycles spent in bank access +system.physmem.avgQLat 4606.73 # Average queueing delay per request +system.physmem.avgBankLat 16312.78 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24919.50 # Average memory access latency +system.physmem.avgRdBW 2852.96 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2852.96 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 17.83 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.11 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 377 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 22174.01 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,243 +204,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 22982 # number of cpu cycles simulated +system.cpu.numCycles 20370 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2481 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2031 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2060 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 620 # Number of BTB hits +system.cpu.BPredUnit.lookups 2504 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2048 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 453 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2080 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 624 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7156 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14473 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 780 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2399 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1409 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 837 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 7226 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14617 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2504 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 786 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2424 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1424 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 732 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1870 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 316 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11344 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.275829 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.704070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11348 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.288068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.714156 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8945 78.85% 78.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 173 1.53% 80.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 163 1.44% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 136 1.20% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 199 1.75% 84.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 148 1.30% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 251 2.21% 88.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 108 0.95% 89.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1221 10.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8924 78.64% 78.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 176 1.55% 80.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 165 1.45% 81.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 138 1.22% 82.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 200 1.76% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 150 1.32% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 252 2.22% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 109 0.96% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1234 10.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11344 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.107954 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.629754 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7303 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 957 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2216 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 11348 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122926 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.717575 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7362 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2237 # Number of cycles decode is running system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 791 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 355 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12764 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 791 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7518 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 384 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2068 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 254 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12054 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 208 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10357 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19653 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19598 # Number of integer rename lookups +system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 358 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12862 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 473 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7582 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 226 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2090 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 230 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12157 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 192 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10431 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19827 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19772 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5359 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5433 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 528 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2068 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1915 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 56 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10860 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 524 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2089 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1950 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 35 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10962 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9235 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4823 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 9314 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4943 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4190 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11344 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.814087 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.547249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11348 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.820761 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.558908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7932 69.92% 69.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1090 9.61% 79.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 771 6.80% 86.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 520 4.58% 90.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 472 4.16% 95.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 326 2.87% 97.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 145 1.28% 99.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 49 0.43% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 39 0.34% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7942 69.99% 69.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1067 9.40% 79.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 770 6.79% 86.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 514 4.53% 90.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 477 4.20% 94.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 338 2.98% 97.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 150 1.32% 99.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.47% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 37 0.33% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11348 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 2.29% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 76 43.43% 45.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 95 54.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 2.22% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 78 43.33% 45.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 98 54.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5682 61.53% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1849 20.02% 81.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1702 18.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5730 61.52% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1859 19.96% 81.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1723 18.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9235 # Type of FU issued -system.cpu.iq.rate 0.401836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 175 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018950 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30091 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15718 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8353 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9314 # Type of FU issued +system.cpu.iq.rate 0.457241 # Inst issue rate +system.cpu.iq.fu_busy_cnt 180 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019326 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30270 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15941 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8417 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9376 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9460 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 77 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1107 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1128 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 869 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 904 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 138 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10924 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2068 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1915 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11026 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2089 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1950 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 381 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8741 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1709 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3273 # number of memory reference insts executed -system.cpu.iew.exec_branches 1381 # Number of branches executed -system.cpu.iew.exec_stores 1564 # Number of stores executed -system.cpu.iew.exec_rate 0.380341 # Inst execution rate -system.cpu.iew.wb_sent 8540 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8380 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4334 # num instructions producing a value -system.cpu.iew.wb_consumers 6987 # num instructions consuming a value +system.cpu.iew.exec_refs 3293 # number of memory reference insts executed +system.cpu.iew.exec_branches 1392 # Number of branches executed +system.cpu.iew.exec_stores 1577 # Number of stores executed +system.cpu.iew.exec_rate 0.432351 # Inst execution rate +system.cpu.iew.wb_sent 8605 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8444 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4397 # num instructions producing a value +system.cpu.iew.wb_consumers 7138 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.364633 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.620295 # average fanout of values written-back +system.cpu.iew.wb_rate 0.414531 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.615999 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5141 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5240 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10553 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.548849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.335888 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10544 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.549317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.355880 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8133 77.07% 77.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1033 9.79% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 640 6.06% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 254 2.41% 95.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 184 1.74% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 109 1.03% 98.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 61 0.58% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.40% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 97 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8175 77.53% 77.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 992 9.41% 86.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 623 5.91% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 255 2.42% 95.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 176 1.67% 96.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 1.02% 97.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.64% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.39% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 107 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10553 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10544 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -293,68 +451,68 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21389 # The number of ROB reads -system.cpu.rob.rob_writes 22658 # The number of ROB writes -system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11638 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21469 # The number of ROB reads +system.cpu.rob.rob_writes 22869 # The number of ROB writes +system.cpu.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9022 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 3.967887 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.967887 # CPI: Total CPI of All Threads -system.cpu.ipc 0.252023 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.252023 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13882 # number of integer regfile reads -system.cpu.int_regfile_writes 7254 # number of integer regfile writes +system.cpu.cpi 3.516920 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.516920 # CPI: Total CPI of All Threads +system.cpu.ipc 0.284340 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.284340 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13990 # number of integer regfile reads +system.cpu.int_regfile_writes 7309 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 173.017509 # Cycle average of tags in use -system.cpu.icache.total_refs 1435 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.030899 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 172.348292 # Cycle average of tags in use +system.cpu.icache.total_refs 1461 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.092437 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 173.017509 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084481 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084481 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits -system.cpu.icache.overall_hits::total 1435 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses -system.cpu.icache.overall_misses::total 435 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15962500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15962500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15962500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15962500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15962500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15962500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1870 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1870 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1870 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1870 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.232620 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.232620 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.232620 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.232620 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.232620 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.232620 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36695.402299 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36695.402299 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36695.402299 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36695.402299 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36695.402299 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36695.402299 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.348292 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084154 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084154 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1461 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1461 # number of overall hits +system.cpu.icache.overall_hits::total 1461 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 426 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 426 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 426 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 426 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 426 # number of overall misses +system.cpu.icache.overall_misses::total 426 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13125000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13125000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13125000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13125000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13125000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13125000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1887 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1887 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1887 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1887 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.225755 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.225755 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.225755 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.225755 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.225755 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.225755 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30809.859155 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30809.859155 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30809.859155 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30809.859155 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30809.859155 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30809.859155 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -363,94 +521,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13118500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13118500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13118500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13118500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13118500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13118500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.190374 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.190374 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.190374 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36849.719101 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36849.719101 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36849.719101 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36849.719101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36849.719101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36849.719101 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 357 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 357 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 357 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 357 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 357 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10853500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10853500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10853500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10853500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10853500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10853500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.189189 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.189189 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.189189 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30401.960784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30401.960784 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30401.960784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 30401.960784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30401.960784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 30401.960784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.294290 # Cycle average of tags in use -system.cpu.dcache.total_refs 2199 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.058180 # Cycle average of tags in use +system.cpu.dcache.total_refs 2201 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.558824 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.578431 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.294290 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015453 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015453 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1487 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1487 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 712 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 712 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits -system.cpu.dcache.overall_hits::total 2199 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 94 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 94 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 334 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 334 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 428 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 428 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 428 # number of overall misses -system.cpu.dcache.overall_misses::total 428 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3573500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3573500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11341500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11341500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14915000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14915000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14915000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14915000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1581 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 63.058180 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015395 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015395 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 718 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 718 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2201 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2201 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2201 # number of overall hits +system.cpu.dcache.overall_hits::total 2201 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 92 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 92 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 328 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 328 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 420 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 420 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 420 # number of overall misses +system.cpu.dcache.overall_misses::total 420 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3276500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3276500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9157000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9157000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12433500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12433500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12433500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12433500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1575 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1575 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2627 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2627 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2627 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2627 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.059456 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.059456 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319312 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319312 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162923 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162923 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.162923 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.162923 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38015.957447 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38015.957447 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33956.586826 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33956.586826 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34848.130841 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34848.130841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34848.130841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34848.130841 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2621 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2621 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2621 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2621 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058413 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.058413 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.313576 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.313576 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.160244 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.160244 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.160244 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.160244 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35614.130435 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35614.130435 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27917.682927 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27917.682927 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29603.571429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29603.571429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29603.571429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29603.571429 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -459,14 +617,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11632000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3833500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15465500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11632000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3833500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15465500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 454 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9262482 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1897546 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11160028 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1863544 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1863544 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9262482 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3761090 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13023572 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9262482 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3761090 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13023572 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987835 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987864 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989083 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989107 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989083 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33139.601140 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36009.090909 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33528.325123 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39425.531915 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39425.531915 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33139.601140 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37583.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34140.176600 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33139.601140 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37583.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34140.176600 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989107 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 26313.869318 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34500.836364 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 27420.216216 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39649.872340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39649.872340 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 26313.869318 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36873.431373 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28686.281938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 26313.869318 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36873.431373 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28686.281938 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index a6445a723..8df237734 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18570500 # Number of ticks simulated -final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 17991500 # Number of ticks simulated +final_tick 17991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78205 # Simulator instruction rate (inst/s) -host_op_rate 78177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272440141 # Simulator tick rate (ticks/s) -host_mem_usage 214124 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 44971 # Simulator instruction rate (inst/s) +host_op_rate 44961 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 151823718 # Simulator tick rate (ticks/s) +host_mem_usage 222708 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,28 +19,186 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 995988261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 461807706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1457795967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 995988261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 995988261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 995988261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 461807706 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1457795967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1028041019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 476669538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1504710558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1028041019 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1028041019 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1028041019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 476669538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1504710558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 27072 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 59 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 62 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 54 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 17940000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 423 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1964422 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11356422 # Sum of mem lat for all requests +system.physmem.totBusLat 1692000 # Total cycles spent in databus access +system.physmem.totBankLat 7700000 # Total cycles spent in bank access +system.physmem.avgQLat 4644.02 # Average queueing delay per request +system.physmem.avgBankLat 18203.31 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26847.33 # Average memory access latency +system.physmem.avgRdBW 1504.71 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1504.71 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.40 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.63 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 336 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42411.35 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 37142 # number of cpu cycles simulated +system.cpu.numCycles 35984 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1632 # Number of BP lookups +system.cpu.branch_predictor.lookups 1634 # Number of BP lookups system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1167 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 1169 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 37.532134 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 37.467921 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedNotTaken 1129 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File @@ -58,12 +216,12 @@ system.cpu.execution_unit.executions 3966 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9963 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9941 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 471 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30915 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. -system.cpu.activity 16.765387 # Percentage of cycles cpu is active +system.cpu.timesIdled 470 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29760 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6224 # Number of cycles cpu stages are processed. +system.cpu.activity 17.296576 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -75,120 +233,120 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.972405 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.755022 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.972405 # CPI: Total CPI of All Threads -system.cpu.ipc 0.143423 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.755022 # CPI: Total CPI of All Threads +system.cpu.ipc 0.148038 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.143423 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32576 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4566 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.293361 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33943 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3199 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.612891 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34098 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.148038 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 31416 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4568 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.694531 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 32782 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3202 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.898399 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 32940 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.195574 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 36160 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.459315 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 35002 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.643907 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33973 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.728991 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 32815 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3169 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.532120 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 8.806692 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.328432 # Cycle average of tags in use -system.cpu.icache.total_refs 828 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.057869 # Cycle average of tags in use +system.cpu.icache.total_refs 829 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.845361 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.848797 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 136.328432 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.066567 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.066567 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 828 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 828 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 828 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 828 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 828 # number of overall hits -system.cpu.icache.overall_hits::total 828 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19327000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19327000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19327000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19327000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19327000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19327000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.297114 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.297114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.297114 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.297114 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.297114 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.297114 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 138.057869 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067411 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067411 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 829 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 829 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 829 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 829 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 829 # number of overall hits +system.cpu.icache.overall_hits::total 829 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses +system.cpu.icache.overall_misses::total 348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18017500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18017500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18017500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18017500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18017500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18017500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1177 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1177 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1177 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1177 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1177 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1177 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295667 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.295667 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.295667 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.295667 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.295667 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.295667 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51774.425287 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51774.425287 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51774.425287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51774.425287 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 218 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 72.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 49.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15994000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15994000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15994000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15994000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15994000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15994000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54962.199313 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54962.199313 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15219500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15219500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15219500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15219500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15219500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15219500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247239 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.247239 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.247239 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52300.687285 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52300.687285 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.607202 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.298060 # Cycle average of tags in use system.cpu.dcache.total_refs 1045 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.740741 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.607202 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020168 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020168 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.298060 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020336 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020336 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits @@ -205,14 +363,14 @@ system.cpu.dcache.demand_misses::cpu.data 343 # n system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses system.cpu.dcache.overall_misses::total 343 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3485500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3485500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15720000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15720000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19205500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19205500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19205500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19205500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3323500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3323500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13337500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13337500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16661000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16661000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16661000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16661000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -229,20 +387,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.247118 system.cpu.dcache.demand_miss_rate::total 0.247118 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.247118 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.247118 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57139.344262 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 57139.344262 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55744.680851 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55744.680851 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55992.711370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54483.606557 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54483.606557 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47296.099291 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47296.099291 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48574.344023 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48574.344023 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4614 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3752 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 102.533333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 83.377778 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits @@ -261,14 +419,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3073000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3073000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4525000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4525000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7598000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7598000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7598000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7598000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3959500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3959500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6874500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6874500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6874500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6874500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -277,26 +435,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56907.407407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56907.407407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55864.197531 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55864.197531 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53981.481481 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53981.481481 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48882.716049 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48882.716049 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 161.896728 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 163.809669 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 135.841585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.055143 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004146 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000795 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004941 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 137.551022 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.258647 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004198 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000801 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004999 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -317,17 +475,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15675500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3006500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18682000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4441500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4441500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15675500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7448000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23123500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15675500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7448000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23123500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14901000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2848500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17749500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3876000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3876000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14901000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6724500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21625500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14901000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6724500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21625500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -350,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54240.484429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56726.415094 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54625.730994 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54833.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54833.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54665.484634 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54665.484634 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51560.553633 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53745.283019 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51899.122807 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47851.851852 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47851.851852 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51124.113475 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51124.113475 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14525000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5827500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17987500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5827500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17987500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259441 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2182574 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13442015 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2846130 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2846130 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259441 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5028704 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16288145 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259441 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5028704 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16288145 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -402,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42076.124567 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44622.641509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42470.760234 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42746.913580 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42746.913580 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38960.003460 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41180.641509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39304.137427 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35137.407407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35137.407407 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 36ed22f0b..91efbc873 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,269 +1,427 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12215000 # Number of ticks simulated -final_tick 12215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12009000 # Number of ticks simulated +final_tick 12009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33465 # Simulator instruction rate (inst/s) -host_op_rate 60609 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75963972 # Simulator tick rate (ticks/s) -host_mem_usage 227744 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 10920 # Simulator instruction rate (inst/s) +host_op_rate 19780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24373770 # Simulator tick rate (ticks/s) +host_mem_usage 225464 # Number of bytes of host memory used +host_seconds 0.49 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 28928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory +system.physmem.bytes_read::total 28800 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1598035203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 770200573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2368235776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1598035203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1598035203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1598035203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 770200573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2368235776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1625447581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 772753768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2398201349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1625447581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1625447581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1625447581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 772753768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2398201349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28800 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28800 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 11990500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 451 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3096951 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13440951 # Sum of mem lat for all requests +system.physmem.totBusLat 1804000 # Total cycles spent in databus access +system.physmem.totBankLat 8540000 # Total cycles spent in bank access +system.physmem.avgQLat 6866.85 # Average queueing delay per request +system.physmem.avgBankLat 18935.70 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29802.55 # Average memory access latency +system.physmem.avgRdBW 2398.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2398.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.99 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.12 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 353 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 26586.47 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 24431 # number of cpu cycles simulated +system.cpu.numCycles 24019 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3187 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3187 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 588 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2597 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits +system.cpu.BPredUnit.lookups 3185 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3185 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 589 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2591 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7858 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15336 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3187 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4160 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2551 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3088 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 59 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 17124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.595013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.047737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8560 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15317 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3185 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4169 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2596 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2320 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 297 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 17196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.587346 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.039622 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 13067 76.31% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 184 1.07% 77.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 158 0.92% 78.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 198 1.16% 79.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 177 1.03% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 181 1.06% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 237 1.38% 82.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 192 1.12% 84.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2730 15.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 13133 76.37% 76.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 180 1.05% 77.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 163 0.95% 78.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 205 1.19% 79.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 179 1.04% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 184 1.07% 81.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 242 1.41% 83.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 193 1.12% 84.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2717 15.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 17124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130449 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.627727 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8263 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3049 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3749 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 116 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1947 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26028 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1947 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8634 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1940 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3487 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 694 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24257 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 601 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 26511 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 58176 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 58160 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 17196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.132603 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.637703 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9044 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2277 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3768 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1981 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26083 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1981 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9405 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 293 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3524 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 714 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24459 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 613 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 26793 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 58583 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 58567 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 15451 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2379 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1816 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21504 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18146 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 221 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10979 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14783 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 17124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.059682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.899800 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 15733 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 29 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2012 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2439 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1809 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21719 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18260 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 229 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11155 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15144 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 17196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.061875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.899452 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11674 68.17% 68.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1321 7.71% 75.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 996 5.82% 81.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 705 4.12% 85.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 752 4.39% 90.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 712 4.16% 94.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 641 3.74% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 280 1.64% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 43 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11700 68.04% 68.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1330 7.73% 75.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1020 5.93% 81.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 704 4.09% 85.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 773 4.50% 90.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 702 4.08% 94.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 638 3.71% 98.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 284 1.65% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 45 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 17124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 17196 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166 80.19% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21 10.14% 90.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 20 9.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 154 78.97% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 11.28% 90.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19 9.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14557 80.22% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2050 11.30% 91.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1535 8.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14636 80.15% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2090 11.45% 91.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1529 8.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18146 # Type of FU issued -system.cpu.iq.rate 0.742745 # Inst issue rate -system.cpu.iq.fu_busy_cnt 207 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011407 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53836 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32525 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16639 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18260 # Type of FU issued +system.cpu.iq.rate 0.760231 # Inst issue rate +system.cpu.iq.fu_busy_cnt 195 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010679 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 54132 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32913 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16722 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18345 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18446 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 130 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 141 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1327 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1387 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 875 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1947 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1327 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1981 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 687 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21541 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 44 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2379 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1816 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispatchedInsts 21753 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 45 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2439 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1809 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 70 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 643 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17109 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1898 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1037 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 723 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17199 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1930 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3313 # number of memory reference insts executed -system.cpu.iew.exec_branches 1690 # Number of branches executed -system.cpu.iew.exec_stores 1415 # Number of stores executed -system.cpu.iew.exec_rate 0.700299 # Inst execution rate -system.cpu.iew.wb_sent 16835 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16643 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10619 # num instructions producing a value -system.cpu.iew.wb_consumers 16444 # num instructions consuming a value +system.cpu.iew.exec_refs 3340 # number of memory reference insts executed +system.cpu.iew.exec_branches 1687 # Number of branches executed +system.cpu.iew.exec_stores 1410 # Number of stores executed +system.cpu.iew.exec_rate 0.716058 # Inst execution rate +system.cpu.iew.wb_sent 16930 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16726 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10734 # num instructions producing a value +system.cpu.iew.wb_consumers 16630 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.681225 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.645767 # average fanout of values written-back +system.cpu.iew.wb_rate 0.696365 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.645460 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11795 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12007 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 595 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15177 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.642090 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.514380 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 606 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.640486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.512697 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11633 76.65% 76.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1329 8.76% 85.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 606 3.99% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 700 4.61% 94.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 357 2.35% 96.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 136 0.90% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 126 0.83% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 80 0.53% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 210 1.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11677 76.75% 76.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1319 8.67% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 603 3.96% 89.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 704 4.63% 94.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 365 2.40% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 135 0.89% 97.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 125 0.82% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 73 0.48% 98.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 214 1.41% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15177 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15215 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,68 +432,68 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9650 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 210 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36507 # The number of ROB reads -system.cpu.rob.rob_writes 45058 # The number of ROB writes -system.cpu.timesIdled 145 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7307 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 36753 # The number of ROB reads +system.cpu.rob.rob_writes 45519 # The number of ROB writes +system.cpu.timesIdled 141 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6823 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 4.541078 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.541078 # CPI: Total CPI of All Threads -system.cpu.ipc 0.220212 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.220212 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 30201 # number of integer regfile reads -system.cpu.int_regfile_writes 17927 # number of integer regfile writes +system.cpu.cpi 4.464498 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.464498 # CPI: Total CPI of All Threads +system.cpu.ipc 0.223989 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.223989 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 30259 # number of integer regfile reads +system.cpu.int_regfile_writes 18088 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7454 # number of misc regfile reads +system.cpu.misc_regfile_reads 7500 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 147.121871 # Cycle average of tags in use -system.cpu.icache.total_refs 1595 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.195440 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 149.891095 # Cycle average of tags in use +system.cpu.icache.total_refs 1605 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.262295 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.121871 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071837 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071837 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1595 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1595 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1595 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1595 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1595 # number of overall hits -system.cpu.icache.overall_hits::total 1595 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses -system.cpu.icache.overall_misses::total 399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14232000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14232000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14232000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14232000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14232000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14232000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1994 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1994 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1994 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1994 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1994 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.200100 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.200100 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.200100 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.200100 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.200100 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35669.172932 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35669.172932 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35669.172932 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35669.172932 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35669.172932 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35669.172932 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 149.891095 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073189 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073189 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1605 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1605 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1605 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1605 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1605 # number of overall hits +system.cpu.icache.overall_hits::total 1605 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses +system.cpu.icache.overall_misses::total 394 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13338000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13338000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13338000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13338000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13338000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13338000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1999 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197099 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.197099 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.197099 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.197099 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.197099 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.197099 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33852.791878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33852.791878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33852.791878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33852.791878 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,94 +502,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 307 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 307 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 307 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 307 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 307 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11314000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11314000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11314000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11314000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11314000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11314000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153962 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153962 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.153962 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36853.420195 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36853.420195 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36853.420195 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36853.420195 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36853.420195 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36853.420195 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 306 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 306 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 306 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 306 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 306 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 306 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10626000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10626000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10626000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10626000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10626000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10626000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34725.490196 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34725.490196 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.059195 # Cycle average of tags in use -system.cpu.dcache.total_refs 2428 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.630137 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 84.879845 # Cycle average of tags in use +system.cpu.dcache.total_refs 2447 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.875862 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.059195 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020766 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020766 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1570 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 84.879845 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020723 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020723 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1589 # 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number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses -system.cpu.dcache.overall_misses::total 209 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4790000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4790000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3017000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3017000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7807000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7807000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7807000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7807000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1703 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1703 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses +system.cpu.dcache.overall_misses::total 208 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5132000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5132000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3133000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3133000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8265000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8265000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8265000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8265000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2637 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2637 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2637 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2637 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078097 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078097 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2655 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2655 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076700 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076700 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.079257 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.079257 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.079257 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.079257 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36015.037594 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36015.037594 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39697.368421 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39697.368421 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37354.066986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37354.066986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37354.066986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37354.066986 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.078343 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.078343 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.078343 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.078343 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38878.787879 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38878.787879 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.684211 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.684211 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39735.576923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39735.576923 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,111 +604,111 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 62 system.cpu.dcache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2865000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2865000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5691000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5691000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5691000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5691000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041691 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041691 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3278500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3278500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2981000 # 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mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055745 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055745 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055745 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39802.816901 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39802.816901 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37697.368421 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37697.368421 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38714.285714 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38714.285714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38714.285714 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36611.725664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36078.688525 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37717.687075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36611.725664 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33832.786885 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36076 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38223.684211 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38223.684211 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33832.786885 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5097500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15132500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9239430 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2977566 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12216996 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2628106 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2628106 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9239430 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5605672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14845102 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9239430 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5605672 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14845102 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994709 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995595 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995595 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.639344 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35767.605634 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33442.819149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33657.894737 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33657.894737 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30293.213115 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42536.657143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32578.656000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34580.342105 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34580.342105 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |