all: Update stats for memory per master and total fix.

112 files changed, 1904 insertions, 862 deletions

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
index 1a7fdb0b3..5cc0911e9 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -209,9 +208,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
index 69eabeb32..b9f1a2caf 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:37:08
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:15:31
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index c4f4b062b..6887d118d 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000021                       # Nu
 sim_ticks                                    21234500                       # Number of ticks simulated
 final_tick                                   21234500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  37422                       # Simulator instruction rate (inst/s)
-host_op_rate                                    37415                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              124041463                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214024                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                  73768                       # Simulator instruction rate (inst/s)
+host_op_rate                                    73752                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              244499363                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214444                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       30016                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  19264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          469                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     1413548706                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 907202901                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    1413548706                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             10752                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                30016                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        19264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           19264                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   469                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            907202901                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            506345805                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1413548706                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       907202901                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          907202901                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           907202901                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           506345805                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1413548706                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -155,11 +162,17 @@ system.cpu.icache.demand_accesses::total          908                       # nu
 system.cpu.icache.overall_accesses::cpu.inst          908                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total          908                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.385463                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.385463                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.385463                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.385463                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.385463                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.385463                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55267.142857                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55267.142857                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55267.142857                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -187,11 +200,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     16051500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16051500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     16051500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.332599                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.332599                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.332599                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.332599                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.332599                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.332599                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.662252                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.662252                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.662252                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                102.711534                       # Cycle average of tags in use
@@ -235,13 +254,21 @@ system.cpu.dcache.demand_accesses::total         2050                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2050                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2050                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081857                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.081857                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289017                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.289017                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.169268                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.169268                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.169268                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.169268                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 56778.350515                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        54220                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        54220                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54935.158501                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54935.158501                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      1656000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -275,13 +302,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      9022500
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9022500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      9022500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080169                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080169                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.081951                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.081951                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53821.052632                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53554.794521                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53705.357143                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53705.357143                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               195.300582                       # Cycle average of tags in use
@@ -335,18 +370,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          168
 system.cpu.l2cache.overall_accesses::total          470                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996689                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.997481                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996689                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997872                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996689                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.997872                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52277.777778                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52349.315068                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52288.912580                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52288.912580                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -379,18 +422,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6780500
 system.cpu.l2cache.overall_mshr_miss_latency::total     18819000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997481                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997872                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997872                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40400                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40092.171717                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40308.219178                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40125.799574                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40125.799574                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index f1e336f90..280f44c05 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -507,9 +506,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index a5a801059..bcee17b83 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:41:05
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:03:27
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index ff51eef95..e9f17ec08 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    12450500                       # Number of ticks simulated
 final_tick                                   12450500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  42940                       # Simulator instruction rate (inst/s)
-host_op_rate                                    42933                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               83690683                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215012                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  73568                       # Simulator instruction rate (inst/s)
+host_op_rate                                    73552                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              143373020                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215332                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6386                       # Number of instructions simulated
 sim_ops                                          6386                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       31360                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  20096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          490                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     2518774346                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1614071724                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    2518774346                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             20096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             11264                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                31360                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        20096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           20096                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                314                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                176                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   490                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1614071724                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            904702622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2518774346                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1614071724                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1614071724                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1614071724                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           904702622                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2518774346                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -356,11 +363,17 @@ system.cpu.icache.demand_accesses::total         2367                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         2367                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         2367                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.193494                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.193494                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.193494                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.193494                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.193494                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.193494                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 34992.358079                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 34992.358079                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -388,11 +401,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     11133500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11133500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     11133500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.133080                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.133080                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.133080                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.133080                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.133080                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.133080                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                109.847039                       # Cycle average of tags in use
@@ -436,13 +455,21 @@ system.cpu.dcache.demand_accesses::total         2744                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2744                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2744                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076637                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.076637                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.411561                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.411561                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.182216                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.182216                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.182216                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.182216                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data        35451                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        35451                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data        35451                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        35451                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -476,13 +503,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      6297500
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6297500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      6297500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.055349                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.055349                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.064140                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.064140                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.064140                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.064140                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35788.461538                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               224.787735                       # Cycle average of tags in use
@@ -536,18 +571,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          176
 system.cpu.l2cache.overall_accesses::total          491                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996825                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.997613                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996825                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997963                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996825                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.997963                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34400.717703                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34562.500000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34424.489796                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34424.489796                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -580,18 +623,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5537500
 system.cpu.l2cache.overall_mshr_miss_latency::total     15308000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997613                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997963                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997963                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 73aad5a2d..6e91910a0 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -94,9 +94,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
index e45cd058f..7edd901b2 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
+warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
index fcc8cf92e..1bf93074b 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:36:56
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:46:44
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index d2827f261..d49eba0fa 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     3215000                       # Number of ticks simulated
 final_tick                                    3215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 399216                       # Simulator instruction rate (inst/s)
-host_op_rate                                   398861                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              200076048                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204908                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                1264163                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1259559                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              630191855                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 205200                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
-system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                    10718506998                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                7980093313                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    2082737170                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   12801244168                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           7980093313                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2738413686                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             10718506998                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7980093313                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7980093313                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          2082737170                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             2082737170                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7980093313                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          4821150855                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            12801244168                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index ad599d493..a36a875c9 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:36:34
+Real time: Jun/04/2012 13:42:36
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.34
-Virtual_time_in_minutes: 0.00566667
-Virtual_time_in_hours:   9.44444e-05
-Virtual_time_in_days:    3.93519e-06
+Virtual_time_in_seconds: 0.43
+Virtual_time_in_minutes: 0.00716667
+Virtual_time_in_hours:   0.000119444
+Virtual_time_in_days:    4.97685e-06
 
 Ruby_current_time: 279353
 Ruby_start_time: 0
 Ruby_cycles: 279353
 
-mbytes_resident: 48.7227
-mbytes_total: 220.605
-resident_ratio: 0.220859
+mbytes_resident: 49.4727
+mbytes_total: 221.031
+resident_ratio: 0.223827
 
 ruby_cycles_executed: [ 279354 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12930
-page_faults: 0
+page_reclaims: 13079
+page_faults: 9
 swaps: 0
-block_inputs: 8
-block_outputs: 88
+block_inputs: 1264
+block_outputs: 96
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index 5a83168a9..0c7f2991f 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:08:30
-gem5 started May  8 2012 15:36:34
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:53:20
+gem5 started Jun  4 2012 13:42:35
+gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index f4fb755b0..bae589857 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000279                       # Nu
 sim_ticks                                      279353                       # Number of ticks simulated
 final_tick                                     279353                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  40898                       # Simulator instruction rate (inst/s)
-host_op_rate                                    40895                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1783759                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225904                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  12119                       # Simulator instruction rate (inst/s)
+host_op_rate                                    12118                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 528605                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226340                       # Number of bytes of host memory used
+host_seconds                                     0.53                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
-system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      123356470                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                  91840789                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      23969673                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     147326143                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             91840789                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             31515681                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               123356470                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        91840789                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           91840789                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            23969673                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               23969673                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            91840789                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            55485354                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              147326143                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 122dbb303..cc70c5701 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:36:38
+Real time: Jun/04/2012 14:41:05
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.36
-Virtual_time_in_minutes: 0.006
-Virtual_time_in_hours:   0.0001
-Virtual_time_in_days:    4.16667e-06
+Virtual_time_in_seconds: 0.44
+Virtual_time_in_minutes: 0.00733333
+Virtual_time_in_hours:   0.000122222
+Virtual_time_in_days:    5.09259e-06
 
 Ruby_current_time: 223694
 Ruby_start_time: 0
 Ruby_cycles: 223694
 
-mbytes_resident: 48.6758
-mbytes_total: 220.844
-resident_ratio: 0.220408
+mbytes_resident: 49.4922
+mbytes_total: 221.148
+resident_ratio: 0.223796
 
 ruby_cycles_executed: [ 223695 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12940
-page_faults: 0
+page_reclaims: 13086
+page_faults: 12
 swaps: 0
-block_inputs: 8
-block_outputs: 88
+block_inputs: 1728
+block_outputs: 96
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index 4a55f22f7..691f6347c 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:14:18
-gem5 started May  8 2012 15:36:38
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:54:55
+gem5 started Jun  4 2012 14:41:04
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index b6ec472df..ddb3e7d12 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000224                       # Nu
 sim_ticks                                      223694                       # Number of ticks simulated
 final_tick                                     223694                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  36304                       # Simulator instruction rate (inst/s)
-host_op_rate                                    36301                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1267928                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226148                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_inst_rate                                  30014                       # Simulator instruction rate (inst/s)
+host_op_rate                                    30012                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1048235                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226460                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
-system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      154049729                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 114692392                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      29933749                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     183983477                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            114692392                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             39357336                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               154049729                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       114692392                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          114692392                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            29933749                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               29933749                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           114692392                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            69291085                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              183983477                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 75506a0a9..7f8f438c6 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:36:41
+Real time: Jun/04/2012 14:42:12
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.3
-Virtual_time_in_minutes: 0.005
-Virtual_time_in_hours:   8.33333e-05
-Virtual_time_in_days:    3.47222e-06
+Virtual_time_in_seconds: 0.35
+Virtual_time_in_minutes: 0.00583333
+Virtual_time_in_hours:   9.72222e-05
+Virtual_time_in_days:    4.05093e-06
 
 Ruby_current_time: 231701
 Ruby_start_time: 0
 Ruby_cycles: 231701
 
-mbytes_resident: 46.9062
-mbytes_total: 219.027
-resident_ratio: 0.214157
+mbytes_resident: 47.9062
+mbytes_total: 219.422
+resident_ratio: 0.218329
 
 ruby_cycles_executed: [ 231702 ]
 
@@ -127,11 +127,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12491
-page_faults: 0
+page_reclaims: 12630
+page_faults: 12
 swaps: 0
-block_inputs: 16
-block_outputs: 88
+block_inputs: 1736
+block_outputs: 96
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index b67f551de..63d892f7f 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:11:25
-gem5 started May  8 2012 15:36:41
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:56:32
+gem5 started Jun  4 2012 14:42:12
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 4bd1591ab..9ad88fcd3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000232                       # Nu
 sim_ticks                                      231701                       # Number of ticks simulated
 final_tick                                     231701                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  57269                       # Simulator instruction rate (inst/s)
-host_op_rate                                    57262                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                2071522                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224288                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  50012                       # Simulator instruction rate (inst/s)
+host_op_rate                                    50005                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1808952                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224692                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
-system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      148726160                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 110728914                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      28899314                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     177625474                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            110728914                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             37997246                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               148726160                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       110728914                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          110728914                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            28899314                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               28899314                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           110728914                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            66896561                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              177625474                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index 24c3821ed..68ec07392 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:36:31
+Real time: Jun/04/2012 13:41:27
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.31
-Virtual_time_in_minutes: 0.00516667
-Virtual_time_in_hours:   8.61111e-05
-Virtual_time_in_days:    3.58796e-06
+Virtual_time_in_seconds: 0.34
+Virtual_time_in_minutes: 0.00566667
+Virtual_time_in_hours:   9.44444e-05
+Virtual_time_in_days:    3.93519e-06
 
 Ruby_current_time: 208400
 Ruby_start_time: 0
 Ruby_cycles: 208400
 
-mbytes_resident: 46.2461
-mbytes_total: 218.586
-resident_ratio: 0.211569
+mbytes_resident: 47.2969
+mbytes_total: 218.926
+resident_ratio: 0.216041
 
 ruby_cycles_executed: [ 208401 ]
 
@@ -126,11 +126,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12336
-page_faults: 10
+page_reclaims: 12505
+page_faults: 5
 swaps: 0
-block_inputs: 1632
-block_outputs: 88
+block_inputs: 1000
+block_outputs: 96
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 7aaac31e8..f1ba4ed84 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:12:50
-gem5 started May  8 2012 15:36:31
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:51:44
+gem5 started Jun  4 2012 13:41:27
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 30017b1e1..842792d27 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000208                       # Nu
 sim_ticks                                      208400                       # Number of ticks simulated
 final_tick                                     208400                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60692                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60683                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1974491                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223836                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  52133                       # Simulator instruction rate (inst/s)
+host_op_rate                                    52125                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1696034                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224184                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
-system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      165355086                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 123109405                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      32130518                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     197485605                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            123109405                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             42245681                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               165355086                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       123109405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          123109405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            32130518                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               32130518                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           123109405                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            74376200                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              197485605                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
index e165866f9..dd0f48010 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:37:08
+Real time: Jun/04/2012 13:42:47
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.5
-Virtual_time_in_minutes: 0.00833333
-Virtual_time_in_hours:   0.000138889
-Virtual_time_in_days:    5.78704e-06
+Virtual_time_in_seconds: 0.35
+Virtual_time_in_minutes: 0.00583333
+Virtual_time_in_hours:   9.72222e-05
+Virtual_time_in_days:    4.05093e-06
 
 Ruby_current_time: 342698
 Ruby_start_time: 0
 Ruby_cycles: 342698
 
-mbytes_resident: 47.6289
-mbytes_total: 219.488
-resident_ratio: 0.217
+mbytes_resident: 48.4648
+mbytes_total: 219.84
+resident_ratio: 0.220455
 
 ruby_cycles_executed: [ 342699 ]
 
@@ -122,7 +122,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12667
+page_reclaims: 12835
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index 5e2ce6170..0b4993316 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:37:08
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:42:46
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index 333553551..a6b69bd54 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000343                       # Nu
 sim_ticks                                      342698                       # Number of ticks simulated
 final_tick                                     342698                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  30902                       # Simulator instruction rate (inst/s)
-host_op_rate                                    30898                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1653235                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224760                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
+host_inst_rate                                  17946                       # Simulator instruction rate (inst/s)
+host_op_rate                                    17945                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 960252                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225120                       # Number of bytes of host memory used
+host_seconds                                     0.36                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
-system.physmem.num_reads                         7599                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         865                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      100555008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                  74864750                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      19539069                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     120094077                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             74864750                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             25690258                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               100555008                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        74864750                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           74864750                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            19539069                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               19539069                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            74864750                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            45229327                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              120094077                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 2cc7bb879..b0aed7d88 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -176,9 +175,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
index 87ec501fc..00df1b420 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:42:48
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:52:31
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index cd14cede6..0370e845f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000033                       # Nu
 sim_ticks                                    33007000                       # Number of ticks simulated
 final_tick                                   33007000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 236370                       # Simulator instruction rate (inst/s)
-host_op_rate                                   236114                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1215776788                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213800                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 524144                       # Simulator instruction rate (inst/s)
+host_op_rate                                   523337                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2693393609                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214140                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       28544                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  17792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          446                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      864786257                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 539037174                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     864786257                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             10752                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        17792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17792                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            539037174                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            325749084                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               864786257                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       539037174                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          539037174                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           539037174                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           325749084                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              864786257                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total         6415                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         6415                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         6415                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043492                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.043492                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.043492                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.043492                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.043492                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.043492                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55849.462366                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55849.462366                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     14745000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14745000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     14745000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.043492                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.043492                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.043492                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.043492                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.043492                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.043492                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                103.680615                       # Cycle average of tags in use
@@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total         2050                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2050                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2050                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080169                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.080169                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084393                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.084393                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.081951                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.081951                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.081951                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.081951                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -215,13 +242,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      8904000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8904000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      8904000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080169                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080169                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.081951                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.081951                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               184.342479                       # Cycle average of tags in use
@@ -275,18 +310,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          168
 system.cpu.l2cache.overall_accesses::total          447                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996416                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.997326                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996416                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997763                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996416                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.997763                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -319,18 +362,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6720000
 system.cpu.l2cache.overall_mshr_miss_latency::total     17840000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997326                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997763                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997763                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index e812354d2..3b6b2b818 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -507,9 +506,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index 992260cf4..157d28a7a 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:41:16
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:45:03
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 28a756060..119328db2 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000007                       # Nu
 sim_ticks                                     7015000                       # Number of ticks simulated
 final_tick                                    7015000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  31687                       # Simulator instruction rate (inst/s)
-host_op_rate                                    31676                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               93063477                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214220                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  16156                       # Simulator instruction rate (inst/s)
+host_op_rate                                    16154                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47467285                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214556                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       17600                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  12096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          275                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     2508909480                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1724305061                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    2508909480                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             12096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              5504                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                17600                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        12096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           12096                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                189                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                 86                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   275                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1724305061                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            784604419                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2508909480                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1724305061                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1724305061                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1724305061                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           784604419                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2508909480                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -355,11 +362,17 @@ system.cpu.icache.demand_accesses::total         1067                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         1067                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         1067                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.234302                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.234302                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.234302                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.234302                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.234302                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.234302                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        35830                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total        35830                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst        35830                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total        35830                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst        35830                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total        35830                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -387,11 +400,17 @@ system.cpu.icache.demand_mshr_miss_latency::total      6695500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst      6695500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total      6695500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.177132                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.177132                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.177132                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.177132                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.177132                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.177132                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35425.925926                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35425.925926                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35425.925926                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 46.152964                       # Cycle average of tags in use
@@ -435,13 +454,21 @@ system.cpu.dcache.demand_accesses::total          972                       # nu
 system.cpu.dcache.overall_accesses::cpu.data          972                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total          972                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.157817                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.157817                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.244898                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.244898                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.184156                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.184156                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.184156                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.184156                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34359.813084                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39111.111111                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 36270.949721                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 36270.949721                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -475,13 +502,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      3078500
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      3078500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      3078500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.091445                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.091445                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081633                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.088477                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.088477                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.088477                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.088477                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35564.516129                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36395.833333                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35796.511628                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 35796.511628                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               122.732805                       # Cycle average of tags in use
@@ -529,18 +564,26 @@ system.cpu.l2cache.overall_accesses::cpu.data           86
 system.cpu.l2cache.overall_accesses::total          275                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34340.637450                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34666.666667                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34369.090909                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34369.090909                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -573,18 +616,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      2694000
 system.cpu.l2cache.overall_mshr_miss_latency::total      8575500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.410359                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31562.500000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31183.636364                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31183.636364                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 4f5452325..198cad098 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -94,9 +94,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
index 31ae36f2e..bcbfa5445 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
@@ -1,3 +1,4 @@
+warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
index d7b73cec1..4dbe62d94 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:37:01
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:15:42
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index 2f22610c9..cc1232526 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000001                       # Nu
 sim_ticks                                     1297500                       # Number of ticks simulated
 final_tick                                    1297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 381497                       # Simulator instruction rate (inst/s)
-host_op_rate                                   379897                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              190598632                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204064                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 760610                       # Simulator instruction rate (inst/s)
+host_op_rate                                   756680                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              379104629                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204432                       # Number of bytes of host memory used
+host_seconds                                     0.00                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
-system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                    10293641618                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                7969171484                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1586127168                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   11879768786                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              3016                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           2058                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              2058                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2585                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               294                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  294                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           7969171484                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2324470135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             10293641618                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7969171484                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7969171484                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1586127168                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1586127168                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7969171484                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3910597303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            11879768786                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index bda71aafd..5ef992e40 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:36:34
+Real time: Jun/04/2012 13:42:36
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.24
-Virtual_time_in_minutes: 0.004
-Virtual_time_in_hours:   6.66667e-05
-Virtual_time_in_days:    2.77778e-06
+Virtual_time_in_seconds: 0.31
+Virtual_time_in_minutes: 0.00516667
+Virtual_time_in_hours:   8.61111e-05
+Virtual_time_in_days:    3.58796e-06
 
 Ruby_current_time: 104867
 Ruby_start_time: 0
 Ruby_cycles: 104867
 
-mbytes_resident: 45.8906
-mbytes_total: 218.43
-resident_ratio: 0.210093
+mbytes_resident: 46.8984
+mbytes_total: 218.785
+resident_ratio: 0.214358
 
 ruby_cycles_executed: [ 104868 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12254
-page_faults: 0
+page_reclaims: 12410
+page_faults: 4
 swaps: 0
-block_inputs: 0
-block_outputs: 88
+block_inputs: 480
+block_outputs: 96
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index 59ad2cc4d..d8d70a93e 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:08:30
-gem5 started May  8 2012 15:36:34
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:53:20
+gem5 started Jun  4 2012 13:42:35
+gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index bd57039cb..748d8a973 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000105                       # Nu
 sim_ticks                                      104867                       # Number of ticks simulated
 final_tick                                     104867                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  38145                       # Simulator instruction rate (inst/s)
-host_op_rate                                    38137                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1551633                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223676                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                   4864                       # Simulator instruction rate (inst/s)
+host_op_rate                                     4864                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 197908                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224040                       # Number of bytes of host memory used
+host_seconds                                     0.53                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
-system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      127361324                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                  98601085                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      19624858                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     146986182                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              3016                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           2058                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              2058                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2585                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               294                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  294                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             98601085                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             28760239                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               127361324                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        98601085                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           98601085                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            19624858                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               19624858                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            98601085                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            48385097                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              146986182                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 232722c59..0769bb48a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:36:38
+Real time: Jun/04/2012 14:41:15
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.26
-Virtual_time_in_minutes: 0.00433333
-Virtual_time_in_hours:   7.22222e-05
-Virtual_time_in_days:    3.00926e-06
+Virtual_time_in_seconds: 0.3
+Virtual_time_in_minutes: 0.005
+Virtual_time_in_hours:   8.33333e-05
+Virtual_time_in_days:    3.47222e-06
 
 Ruby_current_time: 85418
 Ruby_start_time: 0
 Ruby_cycles: 85418
 
-mbytes_resident: 46.1016
-mbytes_total: 218.602
-resident_ratio: 0.210893
+mbytes_resident: 46.9141
+mbytes_total: 218.969
+resident_ratio: 0.21425
 
 ruby_cycles_executed: [ 85419 ]
 
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12263
+page_reclaims: 12428
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 80
+block_outputs: 88
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index fe8db74fc..dc8b54148 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:14:18
-gem5 started May  8 2012 15:36:38
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:54:55
+gem5 started Jun  4 2012 14:41:15
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 5143cdcae..07e9173f4 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000085                       # Nu
 sim_ticks                                       85418                       # Number of ticks simulated
 final_tick                                      85418                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  33831                       # Simulator instruction rate (inst/s)
-host_op_rate                                    33824                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1120953                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223852                       # Number of bytes of host memory used
+host_inst_rate                                  30509                       # Simulator instruction rate (inst/s)
+host_op_rate                                    30502                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1010829                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224228                       # Number of bytes of host memory used
 host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
-system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      156360486                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 121051769                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      24093282                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     180453769                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              3016                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           2058                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              2058                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2585                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               294                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  294                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            121051769                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             35308717                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               156360486                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       121051769                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          121051769                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            24093282                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               24093282                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           121051769                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            59402000                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              180453769                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index a538bb5ac..1584bb895 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:36:42
+Real time: Jun/04/2012 14:42:22
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.23
-Virtual_time_in_minutes: 0.00383333
-Virtual_time_in_hours:   6.38889e-05
-Virtual_time_in_days:    2.66204e-06
+Virtual_time_in_seconds: 0.27
+Virtual_time_in_minutes: 0.0045
+Virtual_time_in_hours:   7.5e-05
+Virtual_time_in_days:    3.125e-06
 
 Ruby_current_time: 87899
 Ruby_start_time: 0
 Ruby_cycles: 87899
 
-mbytes_resident: 45.1094
-mbytes_total: 217.598
-resident_ratio: 0.207306
+mbytes_resident: 46.1055
+mbytes_total: 217.996
+resident_ratio: 0.211497
 
 ruby_cycles_executed: [ 87900 ]
 
@@ -127,11 +127,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12024
+page_reclaims: 12179
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 88
+block_outputs: 96
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index f849b0d8f..3e1c7a0df 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:11:25
-gem5 started May  8 2012 15:36:41
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:56:32
+gem5 started Jun  4 2012 14:42:22
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 253fc28f1..0b4d202c9 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                       87899                       # Number of ticks simulated
 final_tick                                      87899                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46491                       # Simulator instruction rate (inst/s)
-host_op_rate                                    46479                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1584970                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222824                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  49141                       # Simulator instruction rate (inst/s)
+host_op_rate                                    49125                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1675041                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223232                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
-system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      151947121                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 117635013                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      23413236                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     175360357                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              3016                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           2058                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              2058                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2585                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               294                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  294                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            117635013                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             34312108                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               151947121                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       117635013                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          117635013                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            23413236                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               23413236                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           117635013                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            57725344                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              175360357                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
index 6835e2100..f062dbc78 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:36:31
+Real time: Jun/04/2012 13:42:34
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.24
-Virtual_time_in_minutes: 0.004
-Virtual_time_in_hours:   6.66667e-05
-Virtual_time_in_days:    2.77778e-06
+Virtual_time_in_seconds: 0.34
+Virtual_time_in_minutes: 0.00566667
+Virtual_time_in_hours:   9.44444e-05
+Virtual_time_in_days:    3.93519e-06
 
 Ruby_current_time: 78448
 Ruby_start_time: 0
 Ruby_cycles: 78448
 
-mbytes_resident: 44.707
-mbytes_total: 217.324
-resident_ratio: 0.205716
+mbytes_resident: 45.7539
+mbytes_total: 217.664
+resident_ratio: 0.210204
 
 ruby_cycles_executed: [ 78449 ]
 
@@ -126,11 +126,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11920
-page_faults: 3
+page_reclaims: 12072
+page_faults: 20
 swaps: 0
-block_inputs: 824
-block_outputs: 88
+block_inputs: 2944
+block_outputs: 96
 
 Network Stats
 -------------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index 7b52a0c21..423daf7c7 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:12:50
-gem5 started May  8 2012 15:36:31
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:51:44
+gem5 started Jun  4 2012 13:42:34
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index f21155c2f..002b923d5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000078                       # Nu
 sim_ticks                                       78448                       # Number of ticks simulated
 final_tick                                      78448                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  48255                       # Simulator instruction rate (inst/s)
-host_op_rate                                    48240                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1468118                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222544                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                   9618                       # Simulator instruction rate (inst/s)
+host_op_rate                                     9618                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 292754                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222892                       # Number of bytes of host memory used
+host_seconds                                     0.27                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
-system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      170252906                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 131807057                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      26233938                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     196486845                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              3016                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           2058                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              2058                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2585                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               294                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  294                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            131807057                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             38445849                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               170252906                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       131807057                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          131807057                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            26233938                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               26233938                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           131807057                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            64679788                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              196486845                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index cc4333b9c..0115257b7 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:37:51
+Real time: Jun/04/2012 14:06:25
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.4
-Virtual_time_in_minutes: 0.00666667
-Virtual_time_in_hours:   0.000111111
-Virtual_time_in_days:    4.62963e-06
+Virtual_time_in_seconds: 0.26
+Virtual_time_in_minutes: 0.00433333
+Virtual_time_in_hours:   7.22222e-05
+Virtual_time_in_days:    3.00926e-06
 
 Ruby_current_time: 123378
 Ruby_start_time: 0
 Ruby_cycles: 123378
 
-mbytes_resident: 45.0547
-mbytes_total: 217.531
-resident_ratio: 0.207118
+mbytes_resident: 46.1406
+mbytes_total: 217.871
+resident_ratio: 0.211779
 
 ruby_cycles_executed: [ 123379 ]
 
@@ -122,7 +122,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12045
+page_reclaims: 12216
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 6ae96cee0..ef2e2d974 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:37:51
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:06:24
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 6c31e7bc8..d4f9035ad 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000123                       # Nu
 sim_ticks                                      123378                       # Number of ticks simulated
 final_tick                                     123378                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  23789                       # Simulator instruction rate (inst/s)
-host_op_rate                                    23782                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1138300                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222756                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  56001                       # Simulator instruction rate (inst/s)
+host_op_rate                                    55979                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2679090                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223104                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
-system.physmem.num_reads                         3000                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         294                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      108252687                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                  83807486                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      16680445                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     124933132                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              3016                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                13356                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           10340                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           2058                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              2058                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2585                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3000                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               294                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  294                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             83807486                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             24445201                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               108252687                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        83807486                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           83807486                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            16680445                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               16680445                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            83807486                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            41125646                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              124933132                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 1cfaa4239..3d54d7382 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -176,9 +175,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
index 194a972c4..803a08b4e 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:36:56
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:39:41
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 2a4818376..fab613981 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    16769000                       # Number of ticks simulated
 final_tick                                   16769000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 149101                       # Simulator instruction rate (inst/s)
-host_op_rate                                   148981                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              968734693                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212944                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 308591                       # Simulator instruction rate (inst/s)
+host_op_rate                                   307918                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1999557615                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213304                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       15680                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  10432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          245                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      935058739                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 622100304                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     935058739                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             10432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              5248                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                15680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        10432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           10432                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                 82                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   245                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            622100304                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            312958435                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               935058739                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       622100304                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          622100304                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           622100304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           312958435                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              935058739                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total         2586                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         2586                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         2586                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.063032                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.063032                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.063032                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.063032                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.063032                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.063032                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total        56000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total      8639000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst      8639000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total      8639000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.063032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.063032                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.063032                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 47.418751                       # Cycle average of tags in use
@@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total          709                       # nu
 system.cpu.dcache.overall_accesses::cpu.data          709                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total          709                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.132530                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.132530                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.091837                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.091837                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.115656                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.115656                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.115656                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.115656                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -215,13 +242,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      4346000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4346000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      4346000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.132530                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.132530                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.091837                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.091837                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.115656                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.115656                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.115656                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.115656                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               107.101205                       # Cycle average of tags in use
@@ -269,18 +304,26 @@ system.cpu.l2cache.overall_accesses::cpu.data           82
 system.cpu.l2cache.overall_accesses::total          245                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -313,18 +356,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3280000
 system.cpu.l2cache.overall_mshr_miss_latency::total      9800000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 34353ab5e..d0f59b4b6 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -551,9 +551,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -584,9 +583,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index a7713ed58..9fb63a7a7 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:20:46
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:23:41
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 7aa4a6157..ea50665b2 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000010                       # Nu
 sim_ticks                                    10303500                       # Number of ticks simulated
 final_tick                                   10303500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  20985                       # Simulator instruction rate (inst/s)
-host_op_rate                                    26178                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               46991642                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229632                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
+host_inst_rate                                  43907                       # Simulator instruction rate (inst/s)
+host_op_rate                                    54769                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               98312554                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230064                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        4600                       # Number of instructions simulated
 sim_ops                                          5739                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       25664                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  17664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          401                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     2490804096                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1714368904                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    2490804096                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             17664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8000                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                25664                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        17664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17664                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                276                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                125                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   401                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1714368904                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            776435192                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2490804096                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1714368904                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1714368904                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1714368904                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           776435192                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2490804096                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
@@ -410,11 +417,17 @@ system.cpu.icache.demand_accesses::total         2031                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         2031                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         2031                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.180207                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.180207                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.180207                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.180207                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.180207                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.180207                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 34474.043716                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 34474.043716                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -442,11 +455,17 @@ system.cpu.icache.demand_mshr_miss_latency::total      9833500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst      9833500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total      9833500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.145741                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.145741                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.145741                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.145741                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.145741                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.145741                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 87.257006                       # Cycle average of tags in use
@@ -502,15 +521,25 @@ system.cpu.dcache.demand_accesses::total         2879                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2879                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2879                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.086470                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.086470                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.332968                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.332968                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.181818                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.181818                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.164641                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.164641                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.164641                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.164641                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38250                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        38250                       # average LoadLockedReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 34568.565401                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34568.565401                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -546,13 +575,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      4693500
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4693500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      4693500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054425                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054425                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051754                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.051754                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051754                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.051754                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        35750                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        35750                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        31500                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        31500                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        31500                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        31500                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               188.789311                       # Cycle average of tags in use
@@ -609,18 +646,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          149
 system.cpu.l2cache.overall_accesses::total          445                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.932432                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.813084                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.900744                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.932432                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.865772                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.910112                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.932432                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.865772                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.910112                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -659,18 +704,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3927000
 system.cpu.l2cache.overall_mshr_miss_latency::total     12517500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.775701                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.890819                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.838926                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.901124                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.838926                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.901124                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        31125                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        31125                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        31416                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        31125                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        31416                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index 816c7ba86..693c71c0c 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -525,9 +524,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index fa47f77da..fc15b65e3 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:20:46
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:23:30
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 82d7d38dc..85d0d7401 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000010                       # Nu
 sim_ticks                                    10303500                       # Number of ticks simulated
 final_tick                                   10303500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29431                       # Simulator instruction rate (inst/s)
-host_op_rate                                    36712                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               65901409                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229344                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  49511                       # Simulator instruction rate (inst/s)
+host_op_rate                                    61757                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              110854808                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229756                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        4600                       # Number of instructions simulated
 sim_ops                                          5739                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       25664                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  17664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          401                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     2490804096                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1714368904                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    2490804096                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             17664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8000                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                25664                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        17664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17664                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                276                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                125                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   401                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1714368904                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            776435192                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2490804096                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1714368904                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1714368904                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1714368904                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           776435192                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2490804096                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -365,11 +372,17 @@ system.cpu.icache.demand_accesses::total         2031                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         2031                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         2031                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.180207                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.180207                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.180207                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.180207                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.180207                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.180207                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 34474.043716                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 34474.043716                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -397,11 +410,17 @@ system.cpu.icache.demand_mshr_miss_latency::total      9833500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst      9833500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total      9833500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.145741                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.145741                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.145741                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.145741                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.145741                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.145741                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 87.257006                       # Cycle average of tags in use
@@ -457,15 +476,25 @@ system.cpu.dcache.demand_accesses::total         2879                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2879                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2879                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.086470                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.086470                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.332968                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.332968                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.181818                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.181818                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.164641                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.164641                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.164641                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.164641                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38250                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        38250                       # average LoadLockedReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 34568.565401                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34568.565401                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -501,13 +530,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      4693500
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4693500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      4693500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054425                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054425                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051754                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.051754                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051754                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.051754                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        35750                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        35750                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        31500                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        31500                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        31500                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        31500                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               188.789311                       # Cycle average of tags in use
@@ -564,18 +601,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          149
 system.cpu.l2cache.overall_accesses::total          445                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.932432                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.813084                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.900744                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.932432                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.865772                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.910112                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.932432                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.865772                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.910112                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -614,18 +659,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3927000
 system.cpu.l2cache.overall_mshr_miss_latency::total     12517500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.775701                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.890819                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.838926                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.901124                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.838926                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.901124                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        31125                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        31125                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        31416                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        31125                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        31416                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index 151e2cd8c..f9ef190bc 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -166,9 +166,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
index 435d1afac..a8cf8ab9b 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:20:46
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:24:03
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 1b101d03e..a4d8f3fa5 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2875500                       # Number of ticks simulated
 final_tick                                    2875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 415244                       # Simulator instruction rate (inst/s)
-host_op_rate                                   516464                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              258032084                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219364                       # Number of bytes of host memory used
+host_inst_rate                                 760705                       # Simulator instruction rate (inst/s)
+host_op_rate                                   946184                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              472746039                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219832                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4600                       # Number of instructions simulated
 sim_ops                                          5739                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       22944                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  18452                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     3648                       # Number of bytes written to this memory
-system.physmem.num_reads                         5771                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         924                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     7979134064                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                6416970962                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1268648931                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    9247782994                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             18452                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4492                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                22944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        18452                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           18452                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           3648                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              3648                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4613                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1158                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5771                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               924                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  924                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           6416970962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1562163102                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              7979134064                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      6416970962                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         6416970962                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1268648931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1268648931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          6416970962                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2830812033                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9247782994                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
index da6096ffc..10416c8b5 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -112,9 +112,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
index 73791bcc0..f818842dc 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:20:46
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:23:52
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index da264e87e..44b5714ac 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2875500                       # Number of ticks simulated
 final_tick                                    2875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 249779                       # Simulator instruction rate (inst/s)
-host_op_rate                                   311187                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              155712783                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219320                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 577592                       # Simulator instruction rate (inst/s)
+host_op_rate                                   718947                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              359450620                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219740                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4600                       # Number of instructions simulated
 sim_ops                                          5739                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       22944                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  18452                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     3648                       # Number of bytes written to this memory
-system.physmem.num_reads                         5771                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         924                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     7979134064                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                6416970962                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1268648931                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    9247782994                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             18452                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4492                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                22944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        18452                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           18452                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           3648                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              3648                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4613                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1158                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5771                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               924                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  924                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           6416970962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1562163102                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              7979134064                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      6416970962                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         6416970962                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1268648931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1268648931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          6416970962                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2830812033                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9247782994                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 91f39c039..89402c0d8 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -194,9 +193,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
index f409a27fc..a6d6adcc2 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:20:46
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:24:13
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 55e20828c..0449db647 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    26361000                       # Number of ticks simulated
 final_tick                                   26361000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 148609                       # Simulator instruction rate (inst/s)
-host_op_rate                                   184448                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              855039933                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228200                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 366471                       # Simulator instruction rate (inst/s)
+host_op_rate                                   454532                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2105652624                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228652                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4574                       # Number of instructions simulated
 sim_ops                                          5682                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       22400                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  14400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          350                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      849740146                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 546261523                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     849740146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             14400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8000                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                22400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        14400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           14400                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                225                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                125                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   350                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            546261523                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            303478624                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               849740146                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       546261523                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          546261523                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           546261523                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           303478624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              849740146                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -119,11 +126,17 @@ system.cpu.icache.demand_accesses::total         4614                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         4614                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         4614                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.052232                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.052232                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.052232                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.052232                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.052232                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.052232                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53211.618257                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53211.618257                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -145,11 +158,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     12101000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12101000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     12101000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052232                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052232                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052232                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.052232                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052232                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.052232                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 82.937979                       # Cycle average of tags in use
@@ -201,13 +220,21 @@ system.cpu.dcache.demand_accesses::total         2060                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2060                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2060                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085440                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.085440                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.047097                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.047097                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.068447                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.068447                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.068447                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.068447                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 51234.042553                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 51234.042553                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -233,13 +260,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      6801000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6801000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      6801000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.085440                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.085440                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.068447                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.068447                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.068447                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.068447                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               153.954484                       # Cycle average of tags in use
@@ -296,18 +331,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          141
 system.cpu.l2cache.overall_accesses::total          382                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.933610                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.836735                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.905605                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.933610                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.886525                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.916230                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.933610                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.886525                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.916230                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -340,18 +383,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5000000
 system.cpu.l2cache.overall_mshr_miss_latency::total     14000000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.933610                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.836735                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.905605                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.933610                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.886525                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.916230                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.933610                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.886525                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.916230                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
index 6db06c5ff..ee123d638 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -209,9 +208,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
index 8cbac12cb..40197f717 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:07:01
-gem5 started May  8 2012 15:36:45
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:58:11
+gem5 started Jun  4 2012 14:43:16
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 2d3519846..705e8dbde 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    19775000                       # Number of ticks simulated
 final_tick                                   19775000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  83973                       # Simulator instruction rate (inst/s)
-host_op_rate                                    83956                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              284866754                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214812                       # Number of bytes of host memory used
+host_inst_rate                                  79967                       # Simulator instruction rate (inst/s)
+host_op_rate                                    79947                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              271245925                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215348                       # Number of bytes of host memory used
 host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       29120                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  20288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          455                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     1472566372                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1025941846                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    1472566372                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             20288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                29120                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        20288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           20288                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                317                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   455                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1025941846                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            446624526                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1472566372                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1025941846                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1025941846                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1025941846                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           446624526                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1472566372                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -141,11 +148,17 @@ system.cpu.icache.demand_accesses::total          754                       # nu
 system.cpu.icache.overall_accesses::cpu.inst          754                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total          754                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.454907                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.454907                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.454907                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.454907                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.454907                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.454907                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55768.221574                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55768.221574                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55768.221574                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -173,11 +186,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     16951500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16951500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     16951500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.423077                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.423077                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.423077                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53139.498433                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53139.498433                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53139.498433                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 89.746602                       # Cycle average of tags in use
@@ -221,13 +240,21 @@ system.cpu.dcache.demand_accesses::total         2089                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2089                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2089                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076460                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.076460                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.175135                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.175135                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.120153                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.120153                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.120153                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.120153                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 56994.382022                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55003.086420                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55709.163347                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55709.163347                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      1153500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -261,13 +288,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      7448000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7448000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7448000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074742                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074742                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.066060                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.066060                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54051.724138                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53833.333333                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53971.014493                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53971.014493                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               205.517886                       # Cycle average of tags in use
@@ -321,18 +356,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          138
 system.cpu.l2cache.overall_accesses::total          457                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993730                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.995074                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993730                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.995624                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993730                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.995624                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52400.990099                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52588.235294                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52421.978022                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52421.978022                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -365,18 +408,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5587500
 system.cpu.l2cache.overall_mshr_miss_latency::total     18305000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995074                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995624                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995624                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40215.346535                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40352.941176                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40230.769231                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40230.769231                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 5535b7c1b..a70bd3d3a 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -507,9 +506,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index 6efd85bce..c92fa97a1 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:07:01
-gem5 started May  8 2012 15:36:45
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:58:11
+gem5 started Jun  4 2012 14:43:27
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 0f84e872e..69e82fc15 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000013                       # Nu
 sim_ticks                                    12671500                       # Number of ticks simulated
 final_tick                                   12671500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  56172                       # Simulator instruction rate (inst/s)
-host_op_rate                                    56163                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              137660070                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215596                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  63611                       # Simulator instruction rate (inst/s)
+host_op_rate                                    63597                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              155871053                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216124                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5169                       # Number of instructions simulated
 sim_ops                                          5169                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       30912                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  21824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          483                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     2439490195                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1722290179                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    2439490195                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             21824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9088                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                30912                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21824                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                341                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                142                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   483                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1722290179                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            717200016                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2439490195                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1722290179                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1722290179                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1722290179                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           717200016                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2439490195                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -340,11 +347,17 @@ system.cpu.icache.demand_accesses::total         2039                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         2039                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         2039                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.219225                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.219225                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.219225                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.219225                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.219225                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.219225                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35591.722595                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35591.722595                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35591.722595                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -372,11 +385,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     12065000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12065000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     12065000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.168710                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.168710                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.168710                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.168710                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.168710                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.168710                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35072.674419                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35072.674419                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35072.674419                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 92.322697                       # Cycle average of tags in use
@@ -420,13 +439,21 @@ system.cpu.dcache.demand_accesses::total         2944                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2944                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2944                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.065874                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.065874                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.366486                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.366486                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.160326                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.160326                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.160326                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.160326                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36289.473684                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33609.144543                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 34364.406780                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34364.406780                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -460,13 +487,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      5113000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5113000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      5113000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.045072                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.045072                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048234                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.048234                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048234                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.048234                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35906.593407                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36186.274510                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36007.042254                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 36007.042254                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               226.359524                       # Cycle average of tags in use
@@ -520,18 +555,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          142
 system.cpu.l2cache.overall_accesses::total          486                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.991279                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.993103                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.991279                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.993827                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.991279                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.993827                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34335.648148                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34686.274510                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34372.670807                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34372.670807                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -564,18 +607,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4462000
 system.cpu.l2cache.overall_mshr_miss_latency::total     15052500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991279                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.993103                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.991279                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.993827                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991279                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.993827                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31130.787037                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.596273                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.596273                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index b0d54d9f2..bb362afce 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -94,9 +94,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
index e45cd058f..7edd901b2 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
+warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
index 289fd9d0d..43669dc21 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:07:01
-gem5 started May  8 2012 15:36:45
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:58:11
+gem5 started Jun  4 2012 14:43:38
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 91924afa4..fa97a6f47 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2913500                       # Number of ticks simulated
 final_tick                                    2913500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 826404                       # Simulator instruction rate (inst/s)
-host_op_rate                                   824787                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              411656542                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 205596                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                1277439                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1267147                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              631162418                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 206236                       # Number of bytes of host memory used
+host_seconds                                     0.00                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       27687                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  23312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     3658                       # Number of bytes written to this memory
-system.physmem.num_reads                         6992                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         925                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     9503003261                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                8001372919                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1255534580                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   10758537841                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             23312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4375                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                27687                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        23312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           23312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           3658                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              3658                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               5828                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1164                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6992                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               925                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  925                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           8001372919                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1501630342                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9503003261                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      8001372919                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         8001372919                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1255534580                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1255534580                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          8001372919                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2757164922                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10758537841                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
index 4fad25b5f..9ce456b52 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:07:01
-gem5 started May  8 2012 15:36:45
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:58:11
+gem5 started Jun  4 2012 14:43:59
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index b950c6483..1e3413864 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000293                       # Nu
 sim_ticks                                      292960                       # Number of ticks simulated
 final_tick                                     292960                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60937                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60929                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                3062846                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226192                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  55490                       # Simulator instruction rate (inst/s)
+host_op_rate                                    55480                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2788890                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226736                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       27687                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  23312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     3658                       # Number of bytes written to this memory
-system.physmem.num_reads                         6992                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         925                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       94507783                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                  79574003                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      12486346                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     106994129                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             23312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4375                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                27687                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        23312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           23312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           3658                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              3658                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               5828                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1164                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6992                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               925                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  925                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             79574003                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             14933779                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                94507783                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        79574003                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           79574003                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            12486346                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               12486346                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            79574003                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            27420126                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              106994129                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index c6b1fd816..f7cc4efef 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -176,9 +175,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
index 0276ca4b7..ac53df969 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:07:01
-gem5 started May  8 2012 15:36:45
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:58:11
+gem5 started Jun  4 2012 14:43:48
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index 6c79a4c95..8f49928a9 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000032                       # Nu
 sim_ticks                                    32088000                       # Number of ticks simulated
 final_tick                                   32088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 273601                       # Simulator instruction rate (inst/s)
-host_op_rate                                   273420                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1504754975                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214572                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 540307                       # Simulator instruction rate (inst/s)
+host_op_rate                                   539410                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2965678153                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215020                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       28096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  19264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          439                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      875592122                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 600349040                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     875592122                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                28096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        19264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           19264                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   439                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            600349040                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            275243082                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               875592122                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       600349040                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          600349040                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           600349040                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           275243082                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              875592122                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -95,11 +102,17 @@ system.cpu.icache.demand_accesses::total         5829                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         5829                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         5829                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.051981                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.051981                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.051981                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.051981                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.051981                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.051981                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55722.772277                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55722.772277                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -121,11 +134,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     15975000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15975000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     15975000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.051981                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.051981                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.051981                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 87.458397                       # Cycle average of tags in use
@@ -169,13 +188,21 @@ system.cpu.dcache.demand_accesses::total         2089                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2089                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2089                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074742                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.074742                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.055135                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.055135                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.066060                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.066060                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.066060                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.066060                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -201,13 +228,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      7314000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074742                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074742                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.066060                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.066060                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               188.045319                       # Cycle average of tags in use
@@ -261,18 +296,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          138
 system.cpu.l2cache.overall_accesses::total          441                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993399                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.994872                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993399                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.995465                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993399                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.995465                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -305,18 +348,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5520000
 system.cpu.l2cache.overall_mshr_miss_latency::total     17560000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993399                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994872                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993399                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995465                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993399                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995465                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index b22bc0367..928f0469f 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -475,9 +475,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -508,9 +507,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
index 7aac87cd9..b797dcfe3 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:03:54
-gem5 started May  8 2012 15:36:49
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:59:33
+gem5 started Jun  4 2012 14:44:10
+gem5 executing on zizzer
 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 129f4d9d2..975867801 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000011                       # Nu
 sim_ticks                                    11243500                       # Number of ticks simulated
 final_tick                                   11243500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  73653                       # Simulator instruction rate (inst/s)
-host_op_rate                                    73641                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              142731766                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211540                       # Number of bytes of host memory used
+host_inst_rate                                  72271                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72256                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              140039967                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211876                       # Number of bytes of host memory used
 host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5800                       # Number of instructions simulated
 sim_ops                                          5800                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       28736                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  22400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          449                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     2555787789                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1992262196                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    2555787789                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             22400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              6336                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                28736                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        22400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           22400                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                350                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                 99                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   449                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1992262196                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            563525593                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2555787789                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1992262196                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1992262196                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1992262196                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           563525593                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2555787789                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -339,11 +346,17 @@ system.cpu.icache.demand_accesses::total         1899                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         1899                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         1899                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.230121                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.230121                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.230121                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.230121                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.230121                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.230121                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36004.576659                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36004.576659                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -371,11 +384,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     12417500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12417500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     12417500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.186940                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.186940                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.186940                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.186940                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.186940                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.186940                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 62.512522                       # Cycle average of tags in use
@@ -419,13 +438,21 @@ system.cpu.dcache.demand_accesses::total         2615                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2615                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2615                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052900                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.052900                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.302103                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.302103                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.152581                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.152581                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.152581                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.152581                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 34036.340852                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34036.340852                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -459,13 +486,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      3570000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      3570000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      3570000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032505                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032505                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.045889                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.045889                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037859                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.037859                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037859                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.037859                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               201.766772                       # Cycle average of tags in use
@@ -519,18 +554,26 @@ system.cpu.l2cache.overall_accesses::cpu.data           99
 system.cpu.l2cache.overall_accesses::total          454                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.985915                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.987685                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.985915                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.988987                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.985915                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.988987                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -563,18 +606,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3121500
 system.cpu.l2cache.overall_mshr_miss_latency::total     14026500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.985915                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.987685                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.985915                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.988987                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.985915                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.988987                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index 0a48b581e..aaab5c18b 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -95,9 +95,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
index e45cd058f..7edd901b2 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
+warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
index 4ba999389..b409adbd2 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:03:54
-gem5 started May  8 2012 15:36:50
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:59:33
+gem5 started Jun  4 2012 14:44:21
+gem5 executing on zizzer
 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
index 87b1b3e66..c355893c5 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2900000                       # Number of ticks simulated
 final_tick                                    2900000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 413372                       # Simulator instruction rate (inst/s)
-host_op_rate                                   412979                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              206267825                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 201744                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                1223636                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1219143                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              607261041                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 202160                       # Number of bytes of host memory used
+host_seconds                                     0.00                       # Real time elapsed on the host
 sim_insts                                        5801                       # Number of instructions simulated
 sim_ops                                          5801                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       26925                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  23204                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     4209                       # Number of bytes written to this memory
-system.physmem.num_reads                         6763                       # Number of read requests responded to by this memory
-system.physmem.num_writes                        1046                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     9284482759                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                8001379310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1451379310                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   10735862069                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             23204                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              3721                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26925                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        23204                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           23204                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           4209                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              4209                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               5801                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                962                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6763                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data              1046                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                 1046                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           8001379310                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1283103448                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9284482759                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      8001379310                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         8001379310                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1451379310                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1451379310                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          8001379310                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2734482759                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10735862069                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index 61b03b911..d62e06b17 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -209,9 +208,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
index 19ecb4795..76c88733e 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:42
-gem5 started May  8 2012 15:36:55
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:01:47
+gem5 started Jun  4 2012 14:44:31
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index 5aea2d352..b45b5b881 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000018                       # Nu
 sim_ticks                                    18196500                       # Number of ticks simulated
 final_tick                                   18196500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72963                       # Simulator instruction rate (inst/s)
-host_op_rate                                    72948                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              248531385                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221204                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  58781                       # Simulator instruction rate (inst/s)
+host_op_rate                                    58769                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              200221364                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221628                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       27072                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  18496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          423                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     1487758635                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1016459209                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    1487758635                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             18496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                27072                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        18496                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           18496                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                289                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   423                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1016459209                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            471299426                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1487758635                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1016459209                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1016459209                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1016459209                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           471299426                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1487758635                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            36394                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -123,11 +130,17 @@ system.cpu.icache.demand_accesses::total         1174                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         1174                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         1174                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.295571                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.295571                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.295571                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.295571                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.295571                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.295571                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55063.400576                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55063.400576                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55063.400576                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets       106000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -155,11 +168,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     15468000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15468000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     15468000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.247871                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.247871                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.247871                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.247871                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.247871                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.247871                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53154.639175                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53154.639175                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53154.639175                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 82.864730                       # Cycle average of tags in use
@@ -203,13 +222,21 @@ system.cpu.dcache.demand_accesses::total         1389                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         1389                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         1389                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.082402                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.082402                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.417533                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.417533                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.244780                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.244780                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.244780                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.244780                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55788.135593                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55010.676157                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55145.588235                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55145.588235                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      2259500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -243,13 +270,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      7193500
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7193500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7193500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075419                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075419                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.120357                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.097192                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.097192                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53074.074074                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53425.925926                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53285.185185                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53285.185185                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               162.299655                       # Cycle average of tags in use
@@ -306,18 +341,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          135
 system.cpu.l2cache.overall_accesses::total          426                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993127                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.981481                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.991304                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993127                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.992593                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.992958                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993127                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.992958                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52390.350877                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52228.395062                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52359.338061                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52359.338061                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -350,18 +393,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5399000
 system.cpu.l2cache.overall_mshr_miss_latency::total     17002500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.991304                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.992958                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.992958                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40195.906433                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40191.358025                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40195.035461                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40195.035461                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 3550cbb34..9462bf460 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -94,9 +94,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr
index e45cd058f..7edd901b2 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
+warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
index 467d94a16..a096c2705 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:42
-gem5 started May  8 2012 15:36:55
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:01:47
+gem5 started Jun  4 2012 14:44:41
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index a0bb29684..c78599e75 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2701000                       # Number of ticks simulated
 final_tick                                    2701000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 660534                       # Simulator instruction rate (inst/s)
-host_op_rate                                   659359                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              332979355                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211860                       # Number of bytes of host memory used
+host_inst_rate                                 947128                       # Simulator instruction rate (inst/s)
+host_op_rate                                   944143                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              476131381                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212364                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       26135                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  21532                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     5065                       # Number of bytes written to this memory
-system.physmem.num_reads                         6099                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         673                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     9676045909                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                7971862273                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1875231396                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   11551277305                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             21532                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4603                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26135                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21532                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21532                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           5065                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              5065                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               5383                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                716                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6099                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               673                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  673                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           7971862273                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1704183636                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9676045909                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7971862273                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7971862273                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1875231396                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1875231396                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7971862273                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3579415031                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            11551277305                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                             5403                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
index 5940396eb..095eef676 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/08/2012 15:36:55
+Real time: Jun/04/2012 14:44:51
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.28
-Virtual_time_in_minutes: 0.00466667
-Virtual_time_in_hours:   7.77778e-05
-Virtual_time_in_days:    3.24074e-06
+Virtual_time_in_seconds: 0.31
+Virtual_time_in_minutes: 0.00516667
+Virtual_time_in_hours:   8.61111e-05
+Virtual_time_in_days:    3.58796e-06
 
 Ruby_current_time: 253364
 Ruby_start_time: 0
 Ruby_cycles: 253364
 
-mbytes_resident: 48.3438
-mbytes_total: 226.668
-resident_ratio: 0.21328
+mbytes_resident: 49.3359
+mbytes_total: 227.086
+resident_ratio: 0.217257
 
 ruby_cycles_executed: [ 253365 ]
 
@@ -122,7 +122,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 12864
+page_reclaims: 13015
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index dd8a0a7b3..e4a7b2f0d 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:42
-gem5 started May  8 2012 15:36:55
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:01:47
+gem5 started Jun  4 2012 14:44:51
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 362724c03..2f30e2be2 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000253                       # Nu
 sim_ticks                                      253364                       # Number of ticks simulated
 final_tick                                     253364                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60301                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60291                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                2860139                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232112                       # Number of bytes of host memory used
+host_inst_rate                                  57491                       # Simulator instruction rate (inst/s)
+host_op_rate                                    57480                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2726732                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232540                       # Number of bytes of host memory used
 host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       26135                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  21532                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     5065                       # Number of bytes written to this memory
-system.physmem.num_reads                         6099                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         673                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      103151987                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                  84984449                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      19991001                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     123142988                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             21532                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4603                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26135                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21532                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21532                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           5065                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              5065                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               5383                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                716                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6099                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               673                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  673                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             84984449                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             18167538                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               103151987                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        84984449                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           84984449                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            19991001                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               19991001                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            84984449                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            38158539                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              123142988                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                           253364                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 958c9bb97..232d3350e 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -176,9 +175,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index 702411d18..e4af58bc7 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:42
-gem5 started May  8 2012 15:36:55
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:01:47
+gem5 started Jun  4 2012 14:44:42
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index d2987c02e..3580b75db 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28206000                       # Number of ticks simulated
 final_tick                                   28206000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 240215                       # Simulator instruction rate (inst/s)
-host_op_rate                                   240049                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1267195715                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220748                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 427855                       # Simulator instruction rate (inst/s)
+host_op_rate                                   427237                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2253599179                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221156                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       24896                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  16320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          389                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      882649082                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 578600298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     882649082                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             16320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                24896                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        16320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           16320                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                255                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   389                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            578600298                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            304048784                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               882649082                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       578600298                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          578600298                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           578600298                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           304048784                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              882649082                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            56412                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total         5384                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         5384                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         5384                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.047734                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.047734                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.047734                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.047734                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.047734                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.047734                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55673.151751                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55673.151751                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     13537000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13537000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     13537000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.047734                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.047734                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.047734                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 82.065697                       # Cycle average of tags in use
@@ -151,13 +170,21 @@ system.cpu.dcache.demand_accesses::total         1389                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         1389                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         1389                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.075419                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.075419                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.120357                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.120357                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.097192                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.097192                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.097192                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.097192                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55688.888889                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55688.888889                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -183,13 +210,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      7113000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7113000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7113000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075419                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075419                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.120357                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.097192                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.097192                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               142.102892                       # Cycle average of tags in use
@@ -246,18 +281,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          135
 system.cpu.l2cache.overall_accesses::total          392                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992218                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.981481                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.990354                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992218                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.992593                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.992347                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992218                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.992347                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -290,18 +333,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5360000
 system.cpu.l2cache.overall_mshr_miss_latency::total     15560000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.990354                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.992347                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.992347                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index ebb140a84..19d634444 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  3 2012 13:30:44
-gem5 started Jun  3 2012 13:30:58
-gem5 executing on burrito
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 15:03:58
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 5a009d0f1..b16a10afa 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    12198000                       # Number of ticks simulated
 final_tick                                   12198000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  27776                       # Simulator instruction rate (inst/s)
-host_op_rate                                    50299                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               62542635                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245428                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  39950                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72345                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               89952499                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224288                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        5416                       # Number of instructions simulated
 sim_ops                                          9809                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       28864                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  19328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          451                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     2366289556                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1584522053                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    2366289556                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             19328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9536                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                28864                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        19328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           19328                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                302                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                149                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   451                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1584522053                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            781767503                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2366289556                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1584522053                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1584522053                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1584522053                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           781767503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2366289556                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            24397                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -321,11 +328,17 @@ system.cpu.icache.demand_accesses::total         1951                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         1951                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         1951                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.199897                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.199897                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.199897                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.199897                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.199897                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.199897                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35555.128205                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35555.128205                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -353,11 +366,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     10687000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     10687000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     10687000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.155818                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.155818                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.155818                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.155818                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.155818                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.155818                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35154.605263                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35154.605263                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35154.605263                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 84.751522                       # Cycle average of tags in use
@@ -401,13 +420,21 @@ system.cpu.dcache.demand_accesses::total         2556                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2556                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2556                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070900                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070900                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081370                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.081370                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.074726                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074726                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.074726                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074726                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 36376.963351                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 36376.963351                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -439,13 +466,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      5263500
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5263500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      5263500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.045006                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.045006                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081370                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081370                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.058294                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.058294                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.058294                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.058294                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35260.273973                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35388.157895                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35325.503356                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 35325.503356                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               179.622577                       # Cycle average of tags in use
@@ -499,18 +534,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          149
 system.cpu.l2cache.overall_accesses::total          453                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993421                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.994695                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993421                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.995585                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993421                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.995585                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34278.666667                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        34250                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        34250                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34273.835920                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34273.835920                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -543,18 +586,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4633000
 system.cpu.l2cache.overall_mshr_miss_latency::total     14027000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993421                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994695                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993421                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995585                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993421                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995585                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
index 0daaf6112..85d4b3244 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  3 2012 13:30:44
-gem5 started Jun  3 2012 13:30:59
-gem5 executing on burrito
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 15:04:09
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 2c5d9e840..971607574 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000006                       # Nu
 sim_ticks                                     5651000                       # Number of ticks simulated
 final_tick                                    5651000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   8235                       # Simulator instruction rate (inst/s)
-host_op_rate                                    14913                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                8590426                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234908                       # Number of bytes of host memory used
-host_seconds                                     0.66                       # Real time elapsed on the host
+host_inst_rate                                 420667                       # Simulator instruction rate (inst/s)
+host_op_rate                                   760787                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              437668419                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214072                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5417                       # Number of instructions simulated
 sim_ops                                          9810                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       62348                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  55280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     7110                       # Number of bytes written to this memory
-system.physmem.num_reads                         7966                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         934                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                    11033091488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                9782339409                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1258184392                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   12291275880                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             55280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              7068                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                62348                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        55280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           55280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           7110                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              7110                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6910                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1056                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7966                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               934                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  934                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           9782339409                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1250752079                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             11033091488                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      9782339409                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         9782339409                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1258184392                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1258184392                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          9782339409                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2508936471                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            12291275880                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            11303                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index a0ea73428..400138927 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jun/03/2012 13:31:00
+Real time: Jun/04/2012 15:04:30
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.35
-Virtual_time_in_minutes: 0.00583333
-Virtual_time_in_hours:   9.72222e-05
-Virtual_time_in_days:    4.05093e-06
+Virtual_time_in_seconds: 0.36
+Virtual_time_in_minutes: 0.006
+Virtual_time_in_hours:   0.0001
+Virtual_time_in_days:    4.16667e-06
 
 Ruby_current_time: 276484
 Ruby_start_time: 0
 Ruby_cycles: 276484
 
-mbytes_resident: 52.5547
-mbytes_total: 249.254
-resident_ratio: 0.210848
+mbytes_resident: 52.9648
+mbytes_total: 228.941
+resident_ratio: 0.232473
 
 ruby_cycles_executed: [ 276485 ]
 
@@ -125,7 +125,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11223
+page_reclaims: 14034
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
index bef47caec..781f2a777 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  3 2012 13:30:44
-gem5 started Jun  3 2012 13:30:58
-gem5 executing on burrito
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 15:04:30
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 436ded977..37cc5b98f 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000276                       # Nu
 sim_ticks                                      276484                       # Number of ticks simulated
 final_tick                                     276484                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  34222                       # Simulator instruction rate (inst/s)
-host_op_rate                                    61969                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1746397                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 255240                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  48659                       # Simulator instruction rate (inst/s)
+host_op_rate                                    88106                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2482786                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234440                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        5417                       # Number of instructions simulated
 sim_ops                                          9810                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       62348                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  55280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     7110                       # Number of bytes written to this memory
-system.physmem.num_reads                         7966                       # Number of read requests responded to by this memory
-system.physmem.num_writes                         934                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      225503103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 199939237                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      25715774                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     251218877                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             55280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              7068                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                62348                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        55280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           55280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           7110                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              7110                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6910                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1056                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7966                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data               934                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  934                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            199939237                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             25563866                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               225503103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       199939237                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          199939237                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            25715774                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               25715774                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           199939237                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            51279640                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              251218877                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                           276484                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index 91d5c9297..62a044b81 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  3 2012 13:30:44
-gem5 started Jun  3 2012 13:30:59
-gem5 executing on burrito
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 15:04:19
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index 2325f81a1..1e89d36d4 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000029                       # Nu
 sim_ticks                                    28768000                       # Number of ticks simulated
 final_tick                                   28768000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39729                       # Simulator instruction rate (inst/s)
-host_op_rate                                    71940                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              210944443                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244104                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                 318234                       # Simulator instruction rate (inst/s)
+host_op_rate                                   575684                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1686451163                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223048                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5417                       # Number of instructions simulated
 sim_ops                                          9810                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       23104                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  14528                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          361                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      803114572                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 505005562                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     803114572                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             14528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                23104                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        14528                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           14528                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                227                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   361                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            505005562                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            298109010                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               803114572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       505005562                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          505005562                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           505005562                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           298109010                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              803114572                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            57536                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total         6911                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         6911                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         6911                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.032991                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.032991                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.032991                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.032991                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.032991                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.032991                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55815.789474                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55815.789474                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     12042000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12042000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     12042000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.032991                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.032991                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.032991                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.032991                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.032991                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.032991                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 80.668870                       # Cycle average of tags in use
@@ -151,13 +170,21 @@ system.cpu.dcache.demand_accesses::total         1990                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         1990                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         1990                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052083                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.052083                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084582                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.084582                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.067337                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.067337                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.067337                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.067337                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -183,13 +210,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      7102000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7102000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7102000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.052083                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.052083                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084582                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084582                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067337                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.067337                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067337                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.067337                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               133.809342                       # Cycle average of tags in use
@@ -243,18 +278,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          134
 system.cpu.l2cache.overall_accesses::total          362                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.995614                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.996466                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.995614                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997238                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.995614                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.997238                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -287,18 +330,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5360000
 system.cpu.l2cache.overall_mshr_miss_latency::total     14440000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.996466                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997238                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997238                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------