diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/quick/se/00.hello | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/quick/se/00.hello')
10 files changed, 4226 insertions, 4143 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index dde2aed4b..3b67933ac 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25046000 # Number of ticks simulated -final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25485000 # Number of ticks simulated +final_tick 25485000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22373 # Simulator instruction rate (inst/s) -host_op_rate 22372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87684145 # Simulator tick rate (ticks/s) -host_mem_usage 225308 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 27492 # Simulator instruction rate (inst/s) +host_op_rate 27490 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 109632626 # Simulator tick rate (ticks/s) +host_mem_usage 225100 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,75 +19,77 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 766589475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 429290106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1195879582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 766589475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 766589475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 29952 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25031500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 469 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 753384344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 421895232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1175279576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 753384344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 753384344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 753384344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 421895232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1175279576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 469 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 65 # Per bank write bursts +system.physmem.perBankRdBursts::1 29 # Per bank write bursts +system.physmem.perBankRdBursts::2 27 # Per bank write bursts +system.physmem.perBankRdBursts::3 47 # Per bank write bursts +system.physmem.perBankRdBursts::4 41 # Per bank write bursts +system.physmem.perBankRdBursts::5 19 # Per bank write bursts +system.physmem.perBankRdBursts::6 1 # Per bank write bursts +system.physmem.perBankRdBursts::7 3 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 19 # Per bank write bursts +system.physmem.perBankRdBursts::11 25 # Per bank write bursts +system.physmem.perBankRdBursts::12 15 # Per bank write bursts +system.physmem.perBankRdBursts::13 119 # Per bank write bursts +system.physmem.perBankRdBursts::14 46 # Per bank write bursts +system.physmem.perBankRdBursts::15 12 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 25470500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 469 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -150,48 +152,54 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 285.611940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 145.316634 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 484.514157 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 33 49.25% 49.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 8 11.94% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5 7.46% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 7.46% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4 5.97% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 4.48% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.49% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.49% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.49% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.49% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.49% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.49% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation -system.physmem.totQLat 1857500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11820000 # Sum of mem lat for all requests -system.physmem.totBusLat 2345000 # Total cycles spent in databus access -system.physmem.totBankLat 7617500 # Total cycles spent in bank access -system.physmem.avgQLat 3960.55 # Average queueing delay per request -system.physmem.avgBankLat 16242.00 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25202.56 # Average memory access latency -system.physmem.avgRdBW 1195.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1195.88 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.34 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.47 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 402 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.095238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.496730 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 421.391602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 37 44.05% 44.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 14 16.67% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 5.95% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 5.95% 72.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 4.76% 77.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 5 5.95% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.19% 84.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.19% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.38% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.19% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 1.19% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 2 2.38% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.19% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 2 2.38% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 1 1.19% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.19% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 1.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation +system.physmem.totQLat 2272250 # Total ticks spent queuing +system.physmem.totMemAccLat 12262250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7645000 # Total ticks spent accessing banks +system.physmem.avgQLat 4844.88 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16300.64 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26145.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1177.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1177.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.20 # Data bus utilization in percentage +system.physmem.busUtilRead 9.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.48 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 385 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53372.07 # Average gap between requests -system.membus.throughput 1195879582 # Throughput (bytes/s) +system.physmem.avgGap 54308.10 # Average gap between requests +system.physmem.pageHitRate 82.09 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1175279576 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -202,10 +210,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4378000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 4374750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.2 # Layer utilization (%) system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -248,7 +256,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 50093 # number of cpu cycles simulated +system.cpu.numCycles 50971 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). @@ -270,12 +278,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11606 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11614 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 460 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42717 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 43595 # Number of cycles cpu's stages were not processed system.cpu.runCycles 7376 # Number of cycles cpu stages are processed. -system.cpu.activity 14.724612 # Percentage of cycles cpu is active +system.cpu.activity 14.470974 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -287,36 +295,36 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 7.839280 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.976682 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.839280 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127563 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.976682 # CPI: Total CPI of All Threads +system.cpu.ipc 0.125365 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127563 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45169 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.125365 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46047 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.829717 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46200 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.660395 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47078 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.771545 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45932 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.637676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46810 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.306550 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48759 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.163465 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 49637 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.663047 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.617174 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46513 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 8.746150 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.311081 # Cycle average of tags in use system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.311081 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069488 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -329,12 +337,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24600000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24600000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24600000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24600000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24600000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24600000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24550250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24550250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24550250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24550250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24550250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24550250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -347,12 +355,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69295.774648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69295.774648 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69295.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69295.774648 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69155.633803 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69155.633803 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69155.633803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69155.633803 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -373,26 +381,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20800250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20800250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20800250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20800250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20800250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20800250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20718250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20718250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20718250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20718250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20718250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20718250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68875 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68875 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68603.476821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68603.476821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1198434880 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1177790857 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -407,21 +415,21 @@ system.cpu.toL2Bus.data_through_bus 30016 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 512750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 508750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.093004 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.347593 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.745411 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004344 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006076 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -439,17 +447,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20481750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6961500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27443250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4890250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4890250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20481750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11851750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32333500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20481750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11851750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32333500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20399750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27865000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4857750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4857750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20399750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12323000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32722750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20399750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12323000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32722750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -472,17 +480,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68045.681063 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73278.947368 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69301.136364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66989.726027 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66989.726027 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68941.364606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68941.364606 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67773.255814 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78581.578947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70366.161616 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66544.520548 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66544.520548 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69771.321962 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69771.321962 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,17 +510,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16699250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5777500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22476750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16699250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9764250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26463500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16699250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9764250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26463500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16625250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6283250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22908500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3954250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3954250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16625250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10237500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26862750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16625250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10237500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26862750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -524,27 +532,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55479.235880 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60815.789474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56759.469697 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55233.388704 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66139.473684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57849.747475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54167.808219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54167.808219 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.493430 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.493430 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025267 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025267 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -561,14 +569,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7410000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7410000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21312750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21312750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28722750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28722750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28722750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28722750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7909250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7909250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21376500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21376500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29285750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29285750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29285750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29285750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -585,19 +593,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76391.752577 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76391.752577 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60893.571429 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60893.571429 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64256.711409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64256.711409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81538.659794 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81538.659794 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61075.714286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61075.714286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65516.219239 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65516.219239 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.533333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -617,14 +625,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7063000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7063000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4967750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4967750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12030750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12030750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7566750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7566750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4935250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4935250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12502000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12502000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12502000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12502000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -633,14 +641,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74347.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74347.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68051.369863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68051.369863 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67606.164384 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67606.164384 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 31fc74f80..0ff2f61a7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20671000 # Number of ticks simulated -final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21065000 # Number of ticks simulated +final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10783 # Simulator instruction rate (inst/s) -host_op_rate 10783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34979840 # Simulator tick rate (ticks/s) -host_mem_usage 229184 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host +host_inst_rate 31290 # Simulator instruction rate (inst/s) +host_op_rate 31288 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103426086 # Simulator tick rate (ticks/s) +host_mem_usage 226120 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 969087127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 538725751 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1507812878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 969087127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 969087127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 31168 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20638000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 488 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 286 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 950961310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 528649418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1479610729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 950961310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 950961310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 950961310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 528649418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479610729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 488 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 69 # Per bank write bursts +system.physmem.perBankRdBursts::1 34 # Per bank write bursts +system.physmem.perBankRdBursts::2 32 # Per bank write bursts +system.physmem.perBankRdBursts::3 47 # Per bank write bursts +system.physmem.perBankRdBursts::4 43 # Per bank write bursts +system.physmem.perBankRdBursts::5 21 # Per bank write bursts +system.physmem.perBankRdBursts::6 1 # Per bank write bursts +system.physmem.perBankRdBursts::7 3 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 24 # Per bank write bursts +system.physmem.perBankRdBursts::12 14 # Per bank write bursts +system.physmem.perBankRdBursts::13 119 # Per bank write bursts +system.physmem.perBankRdBursts::14 45 # Per bank write bursts +system.physmem.perBankRdBursts::15 12 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 21032000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 488 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,47 +152,54 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation -system.physmem.totQLat 2449250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12424250 # Sum of mem lat for all requests -system.physmem.totBusLat 2440000 # Total cycles spent in databus access -system.physmem.totBankLat 7535000 # Total cycles spent in bank access -system.physmem.avgQLat 5018.95 # Average queueing delay per request -system.physmem.avgBankLat 15440.57 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25459.53 # Average memory access latency -system.physmem.avgRdBW 1507.81 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1507.81 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.78 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.60 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 419 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 85 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.023529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.928934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 483.454089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 37 43.53% 43.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 9.41% 52.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 10 11.76% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7 8.24% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 3.53% 76.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 2.35% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 2.35% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 4.71% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.18% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.18% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 2.35% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.18% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.18% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 3 3.53% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.18% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 1.18% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 85 # Bytes accessed per row activation +system.physmem.totQLat 3258750 # Total ticks spent queuing +system.physmem.totMemAccLat 13288750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7590000 # Total ticks spent accessing banks +system.physmem.avgQLat 6677.77 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15553.28 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27231.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1482.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1482.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.58 # Data bus utilization in percentage +system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 403 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42290.98 # Average gap between requests -system.membus.throughput 1507812878 # Throughput (bytes/s) +system.physmem.avgGap 43098.36 # Average gap between requests +system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1479610729 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -201,39 +210,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4561500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) -system.cpu.branchPred.lookups 2888 # Number of BP lookups -system.cpu.branchPred.condPredicted 1700 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 619000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.cpu.branchPred.lookups 2884 # Number of BP lookups +system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups -system.cpu.branchPred.BTBHits 757 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups +system.cpu.branchPred.BTBHits 756 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.393458 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 418 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.363636 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2082 # DTB read hits +system.cpu.dtb.read_hits 2076 # DTB read hits system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2129 # DTB read accesses +system.cpu.dtb.read_accesses 2123 # DTB read accesses system.cpu.dtb.write_hits 1063 # DTB write hits system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1094 # DTB write accesses -system.cpu.dtb.data_hits 3145 # DTB hits +system.cpu.dtb.data_hits 3139 # DTB hits system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3223 # DTB accesses -system.cpu.itb.fetch_hits 2387 # ITB hits +system.cpu.dtb.data_accesses 3217 # DTB accesses +system.cpu.itb.fetch_hits 2382 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2426 # ITB accesses +system.cpu.itb.fetch_accesses 2421 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -247,178 +256,178 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 41343 # number of cpu cycles simulated +system.cpu.numCycles 42131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8507 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16592 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2888 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1175 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1903 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1523 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16561 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2884 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.100776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.497742 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2382 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.095812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.493603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12103 80.30% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.11% 82.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.55% 83.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 215 1.43% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 257 1.71% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 241 1.60% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.75% 90.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 184 1.22% 91.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1257 8.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12149 80.39% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.10% 82.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.69% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 240 1.59% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 183 1.21% 91.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1256 8.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.069855 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.401325 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9323 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1686 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2770 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.068453 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.393083 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2764 # Number of cycles decode is running system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1220 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 1219 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15336 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15308 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1220 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9534 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 784 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2627 # Number of cycles rename is running +system.cpu.rename.SquashCycles 1219 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 808 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2623 # Number of cycles rename is running system.cpu.rename.UnblockCycles 355 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14625 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 14604 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 313 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10969 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18250 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18241 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 10951 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18225 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18216 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6399 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6381 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 23 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 808 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2766 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12962 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12953 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10771 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6234 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3598 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15073 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.715651 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.357561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.712698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.354769 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10531 69.87% 69.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1674 11.11% 80.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1174 7.79% 88.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 731 4.85% 93.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 498 3.30% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 271 1.80% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 147 0.98% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10572 69.95% 69.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1678 11.10% 81.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1174 7.77% 88.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 728 4.82% 93.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 498 3.30% 96.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 1.79% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 15 13.27% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 60 53.10% 66.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 38 33.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7249 67.20% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2400 22.25% 89.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1133 10.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7236 67.18% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2397 22.25% 89.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1133 10.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10787 # Type of FU issued -system.cpu.iq.rate 0.260915 # Inst issue rate -system.cpu.iq.fu_busy_cnt 113 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010476 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36793 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19230 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10771 # Type of FU issued +system.cpu.iq.rate 0.255655 # Inst issue rate +system.cpu.iq.fu_busy_cnt 112 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010398 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36800 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19167 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9598 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10887 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10870 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1583 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed @@ -427,57 +436,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 131 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1220 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1219 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 264 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13080 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 13071 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2766 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 505 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10087 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 700 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 381 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10067 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 704 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3236 # number of memory reference insts executed -system.cpu.iew.exec_branches 1591 # Number of branches executed +system.cpu.iew.exec_refs 3230 # number of memory reference insts executed +system.cpu.iew.exec_branches 1588 # Number of branches executed system.cpu.iew.exec_stores 1096 # Number of stores executed -system.cpu.iew.exec_rate 0.243983 # Inst execution rate -system.cpu.iew.wb_sent 9767 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9625 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5058 # num instructions producing a value -system.cpu.iew.wb_consumers 6775 # num instructions consuming a value +system.cpu.iew.exec_rate 0.238945 # Inst execution rate +system.cpu.iew.wb_sent 9751 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9608 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5048 # num instructions producing a value +system.cpu.iew.wb_consumers 6764 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.232808 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.746568 # average fanout of values written-back +system.cpu.iew.wb_rate 0.228051 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.746304 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6689 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6680 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13853 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.461200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13894 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.459839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263268 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11035 79.66% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1522 10.99% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 530 3.83% 94.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 235 1.70% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 147 1.06% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.78% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 103 0.74% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.20% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 145 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11073 79.70% 79.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1524 10.97% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 530 3.81% 94.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 235 1.69% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.07% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 110 0.79% 98.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 103 0.74% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.20% 98.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13853 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13894 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -488,26 +497,26 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26435 # The number of ROB reads -system.cpu.rob.rob_writes 27385 # The number of ROB writes -system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26469 # The number of ROB reads +system.cpu.rob.rob_writes 27366 # The number of ROB writes +system.cpu.timesIdled 271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27018 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 6.488230 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.488230 # CPI: Total CPI of All Threads -system.cpu.ipc 0.154125 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.154125 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12801 # number of integer regfile reads -system.cpu.int_regfile_writes 7277 # number of integer regfile writes +system.cpu.cpi 6.611896 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.611896 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151243 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.151243 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12780 # number of integer regfile reads +system.cpu.int_regfile_writes 7264 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1510909003 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1482648944 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -522,55 +531,55 @@ system.cpu.toL2Bus.data_through_bus 31232 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 531250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 278500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 159.548856 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1893 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.028662 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits -system.cpu.icache.overall_hits::total 1898 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 159.548856 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077905 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1893 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1893 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1893 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1893 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1893 # number of overall hits +system.cpu.icache.overall_hits::total 1893 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses system.cpu.icache.overall_misses::total 489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30301750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30301750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30301750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30301750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30301750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30301750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61966.768916 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61966.768916 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61966.768916 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61966.768916 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31381500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31381500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31381500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31381500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31381500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31381500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2382 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2382 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2382 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2382 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2382 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2382 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205290 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.205290 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.205290 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.205290 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.205290 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.205290 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64174.846626 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64174.846626 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64174.846626 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64174.846626 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,36 +600,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21363250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21363250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21363250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21363250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21363250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21363250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67819.841270 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67819.841270 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22109000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22109000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22109000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22109000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22109000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22109000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132242 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.132242 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.132242 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70187.301587 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70187.301587 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.420292 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.632644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.787647 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006696 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -638,17 +647,17 @@ system.cpu.l2cache.demand_misses::total 488 # nu system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21037250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7945250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28982500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5109500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5109500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21037250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13054750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34092000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21037250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13054750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34092000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21783000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29501750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5390750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5390750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21783000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13109500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34892500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21783000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13109500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34892500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) @@ -671,17 +680,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66997.611465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78665.841584 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69837.349398 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69993.150685 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69993.150685 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69860.655738 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69860.655738 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69372.611465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76423.267327 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71088.554217 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73845.890411 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73845.890411 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71501.024590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71501.024590 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -701,17 +710,17 @@ system.cpu.l2cache.demand_mshr_misses::total 488 system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17080250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6700750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23781000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4208000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4208000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17080250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10908750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27989000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17080250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10908750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27989000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17830500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6478250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4491250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4491250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17830500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10969500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17830500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10969500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28800000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses @@ -723,35 +732,35 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54395.700637 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66344.059406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57303.614458 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56785.031847 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64141.089109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58575.301205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61523.972603 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61523.972603 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.351368 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 107.351368 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026209 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits -system.cpu.dcache.overall_hits::total 2236 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits +system.cpu.dcache.overall_hits::total 2230 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -760,43 +769,43 @@ system.cpu.dcache.demand_misses::cpu.data 529 # n system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses system.cpu.dcache.overall_misses::total 529 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11600250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11600250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21979228 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21979228 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33579478 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33579478 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33579478 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33579478 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1900 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1900 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11435000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11435000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23196228 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23196228 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34631228 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34631228 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34631228 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34631228 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2765 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2765 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2765 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2765 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089474 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.089474 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.089757 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.191320 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.191320 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.191320 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.191320 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68236.764706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68236.764706 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61223.476323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61223.476323 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63477.274102 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63477.274102 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1567 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.191736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.191736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.191736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67264.705882 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67264.705882 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64613.448468 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64613.448468 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65465.459357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65465.459357 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1486 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.484848 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.030303 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -816,30 +825,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8053750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8053750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13239250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13239250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13239250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13239250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053158 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053158 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7827250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7827250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13294000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13294000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79740.099010 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79740.099010 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71034.246575 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71034.246575 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77497.524752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77497.524752 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74886.986301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74886.986301 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 2906fdf0c..5e19e4b84 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11933500 # Number of ticks simulated -final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11990500 # Number of ticks simulated +final_tick 11990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3639 # Simulator instruction rate (inst/s) -host_op_rate 3638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18189727 # Simulator tick rate (ticks/s) -host_mem_usage 227880 # Number of bytes of host memory used -host_seconds 0.66 # Real time elapsed on the host +host_inst_rate 47015 # Simulator instruction rate (inst/s) +host_op_rate 46988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 235942636 # Simulator tick rate (ticks/s) +host_mem_usage 225832 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1008254075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455859555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1464113630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1008254075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1008254075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 273 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 273 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 17472 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 11844000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 273 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.bw_read::cpu.inst 1003461073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 453692507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1457153580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1003461073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1003461073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1003461073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 453692507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1457153580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 273 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 17472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 17472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 0 # Per bank write bursts +system.physmem.perBankRdBursts::1 1 # Per bank write bursts +system.physmem.perBankRdBursts::2 2 # Per bank write bursts +system.physmem.perBankRdBursts::3 24 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 24 # Per bank write bursts +system.physmem.perBankRdBursts::7 37 # Per bank write bursts +system.physmem.perBankRdBursts::8 61 # Per bank write bursts +system.physmem.perBankRdBursts::9 2 # Per bank write bursts +system.physmem.perBankRdBursts::10 14 # Per bank write bursts +system.physmem.perBankRdBursts::11 9 # Per bank write bursts +system.physmem.perBankRdBursts::12 17 # Per bank write bursts +system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::14 12 # Per bank write bursts +system.physmem.perBankRdBursts::15 1 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 11901000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 273 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,43 +152,51 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 277.333333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.700631 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 448.761258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 20 60.61% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 1 3.03% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 2 6.06% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 1 3.03% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 6.06% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 3.03% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 6.06% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 6.06% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation -system.physmem.totQLat 1190000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6735000 # Sum of mem lat for all requests -system.physmem.totBusLat 1365000 # Total cycles spent in databus access -system.physmem.totBankLat 4180000 # Total cycles spent in bank access -system.physmem.avgQLat 4358.97 # Average queueing delay per request -system.physmem.avgBankLat 15311.36 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24670.33 # Average memory access latency -system.physmem.avgRdBW 1464.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1464.11 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.44 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.56 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 240 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 42 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 339.809524 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.784505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 471.889985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 23 54.76% 54.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 1 2.38% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 3 7.14% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 1 2.38% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 4.76% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 4.76% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 2.38% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 4.76% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 2.38% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1 2.38% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 2.38% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 2.38% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 2.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42 # Bytes accessed per row activation +system.physmem.totQLat 1695750 # Total ticks spent queuing +system.physmem.totMemAccLat 7213250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers +system.physmem.totBankLat 4152500 # Total ticks spent accessing banks +system.physmem.avgQLat 6211.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15210.62 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26422.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1457.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1457.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.38 # Data bus utilization in percentage +system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.60 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 231 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43384.62 # Average gap between requests -system.membus.throughput 1464113630 # Throughput (bytes/s) +system.physmem.avgGap 43593.41 # Average gap between requests +system.physmem.pageHitRate 84.62 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.18 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1457153580 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 249 # Transaction distribution system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution @@ -199,10 +209,10 @@ system.membus.data_through_bus 17472 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.4 # Layer utilization (%) -system.cpu.branchPred.lookups 1175 # Number of BP lookups -system.cpu.branchPred.condPredicted 618 # Number of conditional branches predicted +system.membus.respLayer1.occupancy 2551500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.3 # Layer utilization (%) +system.cpu.branchPred.lookups 1176 # Number of BP lookups +system.cpu.branchPred.condPredicted 619 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups system.cpu.branchPred.BTBHits 253 # Number of BTB hits @@ -218,18 +228,18 @@ system.cpu.dtb.read_hits 707 # DT system.cpu.dtb.read_misses 31 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations system.cpu.dtb.read_accesses 738 # DTB read accesses -system.cpu.dtb.write_hits 371 # DTB write hits +system.cpu.dtb.write_hits 368 # DTB write hits system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 391 # DTB write accesses -system.cpu.dtb.data_hits 1078 # DTB hits +system.cpu.dtb.write_accesses 388 # DTB write accesses +system.cpu.dtb.data_hits 1075 # DTB hits system.cpu.dtb.data_misses 51 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1129 # DTB accesses -system.cpu.itb.fetch_hits 1067 # ITB hits +system.cpu.dtb.data_accesses 1126 # DTB accesses +system.cpu.itb.fetch_hits 1065 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1097 # ITB accesses +system.cpu.itb.fetch_accesses 1095 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -243,96 +253,96 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23868 # number of cpu cycles simulated +system.cpu.numCycles 23982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4327 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7029 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1175 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 4347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1212 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1118 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 189 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.900807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.307084 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.908161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.314945 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6591 84.47% 84.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.68% 85.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 115 1.47% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.22% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 179 2.29% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 74 0.95% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.82% 91.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.83% 92.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 567 7.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6511 84.34% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.69% 85.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 115 1.49% 86.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.23% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 2.28% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 76 0.98% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.83% 91.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.84% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049229 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.294495 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5563 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 577 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1156 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 7720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049037 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.292344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5485 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 579 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1153 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 498 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6218 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 498 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5662 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5584 # Number of cycles rename is idle system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1065 # Number of cycles rename is running +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1062 # Number of cycles rename is running system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5911 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 5897 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4285 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6686 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6679 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 4276 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6670 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6663 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2517 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2508 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 955 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 468 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4973 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4960 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4046 # Number of instructions issued +system.cpu.iq.iqInstsIssued 4040 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2348 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1391 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2335 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1384 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7803 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.518519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.233664 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.523316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.238697 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6178 79.17% 79.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 567 7.27% 86.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 400 5.13% 91.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.37% 94.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 199 2.55% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 121 1.55% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 47 0.60% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6098 78.99% 78.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 566 7.33% 86.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 399 5.17% 91.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 262 3.39% 94.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 199 2.58% 97.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 121 1.57% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7720 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available @@ -368,69 +378,69 @@ system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2864 70.79% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 783 19.35% 90.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 398 9.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2861 70.82% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 783 19.38% 90.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 395 9.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4046 # Type of FU issued -system.cpu.iq.rate 0.169516 # Inst issue rate +system.cpu.iq.FU_type_0::total 4040 # Type of FU issued +system.cpu.iq.rate 0.168460 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010875 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15980 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7325 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010891 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15885 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7299 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3649 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4083 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4077 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 540 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 177 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 174 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 498 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5317 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 5302 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 955 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 468 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -438,43 +448,43 @@ system.cpu.iew.memOrderViolationEvents 4 # Nu system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 214 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 3849 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 739 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 191 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1130 # number of memory reference insts executed -system.cpu.iew.exec_branches 644 # Number of branches executed -system.cpu.iew.exec_stores 391 # Number of stores executed -system.cpu.iew.exec_rate 0.161513 # Inst execution rate -system.cpu.iew.wb_sent 3741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3661 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1709 # num instructions producing a value -system.cpu.iew.wb_consumers 2209 # num instructions consuming a value +system.cpu.iew.exec_nop 336 # number of nop insts executed +system.cpu.iew.exec_refs 1127 # number of memory reference insts executed +system.cpu.iew.exec_branches 643 # Number of branches executed +system.cpu.iew.exec_stores 388 # Number of stores executed +system.cpu.iew.exec_rate 0.160495 # Inst execution rate +system.cpu.iew.wb_sent 3735 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3655 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1708 # num instructions producing a value +system.cpu.iew.wb_consumers 2206 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.153385 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.773653 # average fanout of values written-back +system.cpu.iew.wb_rate 0.152406 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.774252 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2732 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2720 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7305 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.352635 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.192667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 7226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.356490 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.198597 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6436 88.10% 88.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204 2.79% 90.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 308 4.22% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 114 1.56% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 0.99% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 51 0.70% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.44% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 25 0.34% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 63 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6357 87.97% 87.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204 2.82% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 308 4.26% 95.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 114 1.58% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.00% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 51 0.71% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.44% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 25 0.35% 99.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7305 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7226 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,23 +497,23 @@ system.cpu.commit.int_insts 2367 # Nu system.cpu.commit.function_calls 71 # Number of function calls committed. system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12303 # The number of ROB reads -system.cpu.rob.rob_writes 11127 # The number of ROB writes -system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16065 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 12212 # The number of ROB reads +system.cpu.rob.rob_writes 11099 # The number of ROB writes +system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16262 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 9.999162 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.999162 # CPI: Total CPI of All Threads -system.cpu.ipc 0.100008 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.100008 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4674 # number of integer regfile reads -system.cpu.int_regfile_writes 2826 # number of integer regfile writes +system.cpu.cpi 10.046921 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.046921 # CPI: Total CPI of All Threads +system.cpu.ipc 0.099533 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.099533 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4665 # number of integer regfile reads +system.cpu.int_regfile_writes 2823 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1464113630 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1457153580 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -518,55 +528,55 @@ system.cpu.toL2Bus.data_through_bus 17472 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 318000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 316000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 133000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 93.236237 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 816 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 816 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 816 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 816 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 816 # number of overall hits -system.cpu.icache.overall_hits::total 816 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 251 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 251 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 251 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 251 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 251 # number of overall misses -system.cpu.icache.overall_misses::total 251 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16843749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16843749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16843749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16843749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16843749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16843749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235239 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.235239 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.235239 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.235239 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.235239 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.235239 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67106.569721 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67106.569721 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67106.569721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67106.569721 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 93.236237 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.045526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.045526 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 815 # number of overall hits +system.cpu.icache.overall_hits::total 815 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17655999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17655999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17655999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17655999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17655999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17655999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1065 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1065 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1065 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234742 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.234742 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70623.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70623.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70623.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70623.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70623.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70623.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -575,48 +585,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 56 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12795749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12795749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12795749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12795749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12795749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12795749 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176195 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.176195 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.176195 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68062.494681 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68062.494681 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13162749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13162749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13162749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70014.622340 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70014.622340 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70014.622340 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70014.622340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70014.622340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70014.622340 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 122.122128 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002799 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000860 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.433851 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.688277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002851 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003727 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -628,17 +638,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12607000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4547250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17154250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1720750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1720750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12607000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6268000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18875000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12607000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6268000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18875000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4692750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17666750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1665750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1665750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6358500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19332500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6358500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19332500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -661,17 +671,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67058.510638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74545.081967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68892.570281 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71697.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71697.916667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69139.194139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69139.194139 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69010.638298 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76930.327869 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70950.803213 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69406.250000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69406.250000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.638298 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74805.882353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70815.018315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.638298 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74805.882353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70815.018315 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,17 +701,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10234500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3797750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14032250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1425250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1425250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10234500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15457500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10234500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15457500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10604500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3946250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14550750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1371750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1371750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10604500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10604500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5318000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15922500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -713,27 +723,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54438.829787 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62258.196721 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56354.417671 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59385.416667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59385.416667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56406.914894 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64692.622951 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58436.746988 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57156.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57156.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56406.914894 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62564.705882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58324.175824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56406.914894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62564.705882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58324.175824 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 45.667407 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.667407 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011149 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011149 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits @@ -750,14 +760,14 @@ system.cpu.dcache.demand_misses::cpu.data 194 # n system.cpu.dcache.demand_misses::total 194 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 194 # number of overall misses system.cpu.dcache.overall_misses::total 194 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7467750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7467750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5336000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5336000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12803750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12803750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12803750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12803750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7226000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7226000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5211250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5211250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12437250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12437250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12437250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12437250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -774,14 +784,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.203782 system.cpu.dcache.demand_miss_rate::total 0.203782 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.203782 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.203782 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66086.283186 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66086.283186 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65876.543210 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65876.543210 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65998.711340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65998.711340 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63946.902655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63946.902655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64336.419753 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64336.419753 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64109.536082 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64109.536082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64109.536082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64109.536082 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -806,14 +816,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4608250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4608250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1746250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1746250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6354500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6354500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6354500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6354500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4753750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4753750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1691250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1691250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6445000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6445000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6445000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6445000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092705 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092705 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -822,14 +832,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089286 system.cpu.dcache.demand_mshr_miss_rate::total 0.089286 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.089286 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75545.081967 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75545.081967 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72760.416667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72760.416667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77930.327869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77930.327869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75823.529412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75823.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75823.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75823.529412 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ca5a55de6..6f535bcb9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16494000 # Number of ticks simulated -final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16981000 # Number of ticks simulated +final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19652 # Simulator instruction rate (inst/s) -host_op_rate 24522 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70593484 # Simulator tick rate (ticks/s) -host_mem_usage 246136 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 41552 # Simulator instruction rate (inst/s) +host_op_rate 51840 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153628168 # Simulator tick rate (ticks/s) +host_mem_usage 240508 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 25152 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16436500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 393 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.num_reads::total 392 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 46 # Per bank write bursts +system.physmem.perBankRdBursts::2 20 # Per bank write bursts +system.physmem.perBankRdBursts::3 42 # Per bank write bursts +system.physmem.perBankRdBursts::4 17 # Per bank write bursts +system.physmem.perBankRdBursts::5 34 # Per bank write bursts +system.physmem.perBankRdBursts::6 35 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 28 # Per bank write bursts +system.physmem.perBankRdBursts::11 42 # Per bank write bursts +system.physmem.perBankRdBursts::12 9 # Per bank write bursts +system.physmem.perBankRdBursts::13 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 16923500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -150,68 +152,76 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2047500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests -system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5445000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.92 # Average queueing delay per request -system.physmem.avgBankLat 13854.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24064.89 # Average memory access latency -system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.91 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 348 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation +system.physmem.totQLat 3153000 # Total ticks spent queuing +system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5403750 # Total ticks spent accessing banks +system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.54 # Data bus utilization in percentage +system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41823.16 # Average gap between requests -system.membus.throughput 1524918152 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 352 # Transaction distribution -system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.physmem.avgGap 43172.19 # Average gap between requests +system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1473647017 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.3 # Layer utilization (%) -system.cpu.branchPred.lookups 2479 # Number of BP lookups -system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu.branchPred.lookups 2481 # Number of BP lookups +system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits @@ -302,179 +312,179 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 32989 # number of cpu cycles simulated +system.cpu.numCycles 33963 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2426 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2221 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2227 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8917 # Type of FU issued -system.cpu.iq.rate 0.270302 # Inst issue rate -system.cpu.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.262668 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled @@ -482,55 +492,55 @@ system.cpu.iew.lsq.thread0.cacheBlocked 3 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_refs 3299 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.258268 # Inst execution rate -system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8067 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3881 # num instructions producing a value -system.cpu.iew.wb_consumers 7779 # num instructions consuming a value +system.cpu.iew.exec_rate 0.250950 # Inst execution rate +system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3883 # num instructions producing a value +system.cpu.iew.wb_consumers 7788 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -541,93 +551,93 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23271 # The number of ROB reads -system.cpu.rob.rob_writes 23399 # The number of ROB writes -system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23234 # The number of ROB reads +system.cpu.rob.rob_writes 23415 # The number of ROB writes +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39193 # number of integer regfile reads -system.cpu.int_regfile_writes 7983 # number of integer regfile writes +system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2975 # number of misc regfile reads +system.cpu.misc_regfile_reads 2977 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits -system.cpu.icache.overall_hits::total 1583 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles +system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits +system.cpu.icache.overall_hits::total 1584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.icache.overall_misses::total 363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -637,42 +647,42 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 73 system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -682,61 +692,61 @@ system.cpu.l2cache.demand_hits::total 40 # nu system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits system.cpu.l2cache.overall_hits::total 40 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses +system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 398 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 397 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,124 +761,124 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits -system.cpu.dcache.overall_hits::total 2369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits +system.cpu.dcache.overall_hits::total 2373 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses +system.cpu.dcache.overall_misses::total 496 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -877,16 +887,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -895,30 +905,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index add5a91d0..1007daea2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16494000 # Number of ticks simulated -final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16981000 # Number of ticks simulated +final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22159 # Simulator instruction rate (inst/s) -host_op_rate 27650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79599293 # Simulator tick rate (ticks/s) -host_mem_usage 246136 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 59313 # Simulator instruction rate (inst/s) +host_op_rate 73997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 219275591 # Simulator tick rate (ticks/s) +host_mem_usage 240508 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 25152 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16436500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 393 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.num_reads::total 392 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 46 # Per bank write bursts +system.physmem.perBankRdBursts::2 20 # Per bank write bursts +system.physmem.perBankRdBursts::3 42 # Per bank write bursts +system.physmem.perBankRdBursts::4 17 # Per bank write bursts +system.physmem.perBankRdBursts::5 34 # Per bank write bursts +system.physmem.perBankRdBursts::6 35 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 28 # Per bank write bursts +system.physmem.perBankRdBursts::11 42 # Per bank write bursts +system.physmem.perBankRdBursts::12 9 # Per bank write bursts +system.physmem.perBankRdBursts::13 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 16923500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -150,68 +152,76 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2047500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests -system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5445000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.92 # Average queueing delay per request -system.physmem.avgBankLat 13854.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24064.89 # Average memory access latency -system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.91 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 348 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation +system.physmem.totQLat 3153000 # Total ticks spent queuing +system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5403750 # Total ticks spent accessing banks +system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.54 # Data bus utilization in percentage +system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41823.16 # Average gap between requests -system.membus.throughput 1524918152 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 352 # Transaction distribution -system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.physmem.avgGap 43172.19 # Average gap between requests +system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1473647017 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.3 # Layer utilization (%) -system.cpu.branchPred.lookups 2479 # Number of BP lookups -system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu.branchPred.lookups 2481 # Number of BP lookups +system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -257,179 +267,179 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32989 # number of cpu cycles simulated +system.cpu.numCycles 33963 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2426 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2221 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2227 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8917 # Type of FU issued -system.cpu.iq.rate 0.270302 # Inst issue rate -system.cpu.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.262668 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled @@ -437,55 +447,55 @@ system.cpu.iew.lsq.thread0.cacheBlocked 3 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_refs 3299 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.258268 # Inst execution rate -system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8067 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3881 # num instructions producing a value -system.cpu.iew.wb_consumers 7779 # num instructions consuming a value +system.cpu.iew.exec_rate 0.250950 # Inst execution rate +system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3883 # num instructions producing a value +system.cpu.iew.wb_consumers 7788 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -496,93 +506,93 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23271 # The number of ROB reads -system.cpu.rob.rob_writes 23399 # The number of ROB writes -system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23234 # The number of ROB reads +system.cpu.rob.rob_writes 23415 # The number of ROB writes +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39193 # number of integer regfile reads -system.cpu.int_regfile_writes 7983 # number of integer regfile writes +system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2975 # number of misc regfile reads +system.cpu.misc_regfile_reads 2977 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits -system.cpu.icache.overall_hits::total 1583 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles +system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits +system.cpu.icache.overall_hits::total 1584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.icache.overall_misses::total 363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -592,42 +602,42 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 73 system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -637,61 +647,61 @@ system.cpu.l2cache.demand_hits::total 40 # nu system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits system.cpu.l2cache.overall_hits::total 40 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -706,124 +716,124 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # 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Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits -system.cpu.dcache.overall_hits::total 2369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits +system.cpu.dcache.overall_hits::total 2373 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses +system.cpu.dcache.overall_misses::total 496 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -832,16 +842,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -850,30 +860,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index aeb0e2e25..3c2a96518 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24587000 # Number of ticks simulated -final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24975000 # Number of ticks simulated +final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52979 # Simulator instruction rate (inst/s) -host_op_rate 52966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 223940501 # Simulator tick rate (ticks/s) -host_mem_usage 224928 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 84511 # Simulator instruction rate (inst/s) +host_op_rate 84494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 362882134 # Simulator tick rate (ticks/s) +host_mem_usage 254488 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 825151503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359214219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1184365722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 825151503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 825151503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 455 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 455 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 29120 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 75 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24519000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 455 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 812332332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 353633634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1165965966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 812332332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812332332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 812332332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 353633634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1165965966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 455 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 29120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 29120 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 0 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 8 # Per bank write bursts +system.physmem.perBankRdBursts::5 3 # Per bank write bursts +system.physmem.perBankRdBursts::6 12 # Per bank write bursts +system.physmem.perBankRdBursts::7 51 # Per bank write bursts +system.physmem.perBankRdBursts::8 59 # Per bank write bursts +system.physmem.perBankRdBursts::9 75 # Per bank write bursts +system.physmem.perBankRdBursts::10 36 # Per bank write bursts +system.physmem.perBankRdBursts::11 19 # Per bank write bursts +system.physmem.perBankRdBursts::12 52 # Per bank write bursts +system.physmem.perBankRdBursts::13 28 # Per bank write bursts +system.physmem.perBankRdBursts::14 77 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24894000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 455 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,48 +152,52 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 94 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.234043 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.011055 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 299.928179 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 34 36.17% 36.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 16 17.02% 53.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 9.57% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 9 9.57% 72.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4 4.26% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 9 9.57% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.06% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 2.13% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 2 2.13% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 2.13% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 2.13% 95.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.06% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.06% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation -system.physmem.totQLat 2305250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12775250 # Sum of mem lat for all requests -system.physmem.totBusLat 2275000 # Total cycles spent in databus access -system.physmem.totBankLat 8195000 # Total cycles spent in bank access -system.physmem.avgQLat 5066.48 # Average queueing delay per request -system.physmem.avgBankLat 18010.99 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28077.47 # Average memory access latency -system.physmem.avgRdBW 1184.37 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1184.37 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.25 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.52 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 361 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.831776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.727359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 292.380874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 36 33.64% 33.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 20 18.69% 52.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 15 14.02% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 8.41% 74.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 3.74% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 8 7.48% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 0.93% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 3.74% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 1.87% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.87% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 1.87% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 0.93% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.93% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.93% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 0.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 107 # Bytes accessed per row activation +system.physmem.totQLat 3167500 # Total ticks spent queuing +system.physmem.totMemAccLat 13555000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8112500 # Total ticks spent accessing banks +system.physmem.avgQLat 6961.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 17829.67 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29791.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.11 # Data bus utilization in percentage +system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.54 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53887.91 # Average gap between requests -system.membus.throughput 1184365722 # Throughput (bytes/s) +system.physmem.avgGap 54712.09 # Average gap between requests +system.physmem.pageHitRate 76.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1165965966 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -202,17 +208,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29120 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4266000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.4 # Layer utilization (%) -system.cpu.branchPred.lookups 1157 # Number of BP lookups +system.membus.respLayer1.occupancy 4260750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.1 # Layer utilization (%) +system.cpu.branchPred.lookups 1156 # Number of BP lookups system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 880 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 879 # Number of BTB lookups system.cpu.branchPred.BTBHits 339 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.522727 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 38.566553 # BTB Hit Percentage system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -234,14 +240,14 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 49175 # number of cpu cycles simulated +system.cpu.numCycles 49951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5089 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 724 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5088 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8485 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8484 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File @@ -256,12 +262,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9487 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43792 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 463 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44568 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.946619 # Percentage of cycles cpu is active +system.cpu.activity 10.776561 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -273,36 +279,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 8.458032 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.591503 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.458032 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118231 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.591503 # CPI: Total CPI of All Threads +system.cpu.ipc 0.116394 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.118231 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45525 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.422471 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46361 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.722420 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46410 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.622776 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47937 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.116394 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46303 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 7.303157 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 47185 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 5.537427 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.517539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47060 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2891 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 5.787672 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.636983 # Cycle average of tags in use system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.636983 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073553 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073553 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -315,12 +321,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25010250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25010250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25010250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25010250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25010250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25010250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25425500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25425500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25425500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25425500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25425500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -333,12 +339,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71457.857143 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71457.857143 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71457.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71457.857143 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72644.285714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72644.285714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72644.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72644.285714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,26 +365,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22679000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22679000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23091000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23091000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71094.043887 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71094.043887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72385.579937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72385.579937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1189571725 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -393,21 +399,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 543000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 538500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 225750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 208.420638 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.318425 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.102213 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004648 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006360 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -425,17 +431,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22333500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6742000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29075500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3650000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3650000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22333500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32725500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22333500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10392000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32725500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22745500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6874750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29620250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3847000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3847000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22745500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10721750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33467250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22745500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10721750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33467250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -458,17 +464,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70452.681388 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77494.252874 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71969.059406 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71568.627451 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71568.627451 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71924.175824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71924.175824 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71752.365931 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79020.114943 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73317.450495 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75431.372549 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75431.372549 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73554.395604 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73554.395604 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,17 +494,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18342000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5661000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24003000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18342000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8667000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27009000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18342000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8667000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27009000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18763000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5795250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24558250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18763000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8999750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27762750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18763000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8999750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27762750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -510,27 +516,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57861.198738 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59413.366337 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59189.274448 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66612.068966 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60787.747525 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.339752 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.339752 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022056 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022056 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits @@ -547,14 +553,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses system.cpu.dcache.overall_misses::total 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7523000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7523000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21590750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21590750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29113750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29113750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29113750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29113750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7659250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7659250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21762250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21762250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29421500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29421500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29421500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29421500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -571,14 +577,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77556.701031 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77556.701031 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61163.597734 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61163.597734 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64697.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64697.222222 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78961.340206 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78961.340206 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61649.433428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61649.433428 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65381.111111 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65381.111111 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -603,14 +609,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3704000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3704000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10539500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10539500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10539500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10539500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6968250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6968250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3901000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3901000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10869250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10869250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10869250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10869250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -619,14 +625,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78568.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78568.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80094.827586 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80094.827586 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76490.196078 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76490.196078 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 423a70e1a..1c2de0612 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21805500 # Number of ticks simulated -final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21898500 # Number of ticks simulated +final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31004 # Simulator instruction rate (inst/s) -host_op_rate 31001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131093072 # Simulator tick rate (ticks/s) -host_mem_usage 229800 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 64871 # Simulator instruction rate (inst/s) +host_op_rate 64859 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 275425114 # Simulator tick rate (ticks/s) +host_mem_usage 255508 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory system.physmem.num_reads::total 477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 983238174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 416775584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1400013758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 983238174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 983238174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 477 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 477 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30528 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 63 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 21726000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 477 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 979062493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 415005594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1394068087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 979062493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 979062493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 979062493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 415005594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1394068087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 477 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 30 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 1 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 7 # Per bank write bursts +system.physmem.perBankRdBursts::5 3 # Per bank write bursts +system.physmem.perBankRdBursts::6 13 # Per bank write bursts +system.physmem.perBankRdBursts::7 54 # Per bank write bursts +system.physmem.perBankRdBursts::8 63 # Per bank write bursts +system.physmem.perBankRdBursts::9 77 # Per bank write bursts +system.physmem.perBankRdBursts::10 44 # Per bank write bursts +system.physmem.perBankRdBursts::11 20 # Per bank write bursts +system.physmem.perBankRdBursts::12 51 # Per bank write bursts +system.physmem.perBankRdBursts::13 29 # Per bank write bursts +system.physmem.perBankRdBursts::14 77 # Per bank write bursts +system.physmem.perBankRdBursts::15 8 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 21819000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 477 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,47 +152,52 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.708738 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.390708 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.503517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 2.91% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3 2.91% 88.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 2353250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13414500 # Sum of mem lat for all requests -system.physmem.totBusLat 2385000 # Total cycles spent in databus access -system.physmem.totBankLat 8676250 # Total cycles spent in bank access -system.physmem.avgQLat 4933.44 # Average queueing delay per request -system.physmem.avgBankLat 18189.20 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28122.64 # Average memory access latency -system.physmem.avgRdBW 1400.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1400.01 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.94 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.62 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 374 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.508475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.858901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 317.434070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 46 38.98% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 20 16.95% 55.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 19 16.10% 72.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 8 6.78% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 7 5.93% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.54% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 3.39% 90.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 1.69% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 1.69% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 0.85% 94.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 0.85% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 0.85% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.69% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 0.85% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 118 # Bytes accessed per row activation +system.physmem.totQLat 2620250 # Total ticks spent queuing +system.physmem.totMemAccLat 13667750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8662500 # Total ticks spent accessing banks +system.physmem.avgQLat 5493.19 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18160.38 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28653.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1394.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1394.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.89 # Data bus utilization in percentage +system.physmem.busUtilRead 10.89 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 359 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45547.17 # Average gap between requests -system.membus.throughput 1400013758 # Throughput (bytes/s) +system.physmem.avgGap 45742.14 # Average gap between requests +system.physmem.pageHitRate 75.26 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1394068087 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 426 # Transaction distribution system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -201,17 +208,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4480000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.5 # Layer utilization (%) -system.cpu.branchPred.lookups 2187 # Number of BP lookups +system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.4 # Layer utilization (%) +system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1664 # Number of BTB lookups -system.cpu.branchPred.BTBHits 502 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups +system.cpu.branchPred.BTBHits 492 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.168269 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -233,94 +240,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43612 # number of cpu cycles simulated +system.cpu.numCycles 43798 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8859 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13212 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2187 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3230 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1384 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1326 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8822 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1344 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1985 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.912746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.223376 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.913456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.225567 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11245 77.69% 77.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1331 9.20% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 131 0.91% 88.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.11% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.82% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 150 1.04% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.09% 93.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 933 6.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11219 77.74% 77.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1317 9.13% 86.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 104 0.72% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 131 0.91% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 115 0.80% 91.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 150 1.04% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 933 6.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050147 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.302944 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8926 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1578 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3043 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3026 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 875 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12329 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 875 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9108 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 901 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2916 # Number of cycles rename is running +system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2899 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11899 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7186 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14116 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13887 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3788 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2460 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8306 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3428 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2082 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14475 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.573817 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.241522 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14432 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.574626 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.242806 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10881 75.17% 75.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1431 9.89% 85.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 893 6.17% 91.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 3.82% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.46% 97.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 225 1.55% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.61% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10849 75.17% 75.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1422 9.85% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 891 6.17% 91.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 3.83% 95.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 355 2.46% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.57% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 89 0.62% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14432 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available @@ -356,68 +363,68 @@ system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4943 59.51% 59.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2250 27.09% 86.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 13.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8306 # Type of FU issued -system.cpu.iq.rate 0.190452 # Inst issue rate +system.cpu.iq.FU_type_0::total 8293 # Type of FU issued +system.cpu.iq.rate 0.189347 # Inst issue rate system.cpu.iq.fu_busy_cnt 160 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019263 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31282 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12675 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7463 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31213 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8464 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1297 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 875 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10763 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2460 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall @@ -426,43 +433,43 @@ system.cpu.iew.memOrderViolationEvents 12 # Nu system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7925 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1525 # number of nop insts executed -system.cpu.iew.exec_refs 3189 # number of memory reference insts executed -system.cpu.iew.exec_branches 1354 # Number of branches executed +system.cpu.iew.exec_nop 1512 # number of nop insts executed +system.cpu.iew.exec_refs 3186 # number of memory reference insts executed +system.cpu.iew.exec_branches 1344 # Number of branches executed system.cpu.iew.exec_stores 1079 # Number of stores executed -system.cpu.iew.exec_rate 0.181716 # Inst execution rate -system.cpu.iew.wb_sent 7555 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7465 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.180648 # Inst execution rate +system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7455 # cumulative count of insts written-back system.cpu.iew.wb_producers 2921 # num instructions producing a value system.cpu.iew.wb_consumers 4197 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.171168 # insts written-back per cycle +system.cpu.iew.wb_rate 0.170213 # insts written-back per cycle system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4943 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13600 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.427426 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.207995 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13564 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.428561 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.209396 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11198 82.34% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 999 7.35% 89.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 630 4.63% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 315 2.32% 96.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 149 1.10% 97.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11162 82.29% 82.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 7.37% 89.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 630 4.64% 94.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 315 2.32% 96.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 149 1.10% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 94 0.69% 98.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13600 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13564 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,23 +482,23 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24237 # The number of ROB reads -system.cpu.rob.rob_writes 22398 # The number of ROB writes +system.cpu.rob.rob_reads 24172 # The number of ROB reads +system.cpu.rob.rob_writes 22333 # The number of ROB writes system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29137 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 29366 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 8.458495 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.458495 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118224 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.118224 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10746 # number of integer regfile reads -system.cpu.int_regfile_writes 5233 # number of integer regfile writes +system.cpu.cpi 8.494569 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.494569 # CPI: Total CPI of All Threads +system.cpu.ipc 0.117722 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.117722 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10743 # number of integer regfile reads +system.cpu.int_regfile_writes 5234 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1408818876 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1402835811 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -506,55 +513,55 @@ system.cpu.toL2Bus.data_through_bus 30720 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 573500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 227500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.632436 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1531 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1531 # number of overall hits -system.cpu.icache.overall_hits::total 1531 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses -system.cpu.icache.overall_misses::total 454 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31019250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31019250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31019250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31019250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31019250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31019250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1985 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1985 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1985 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1985 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228715 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228715 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228715 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228715 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228715 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228715 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68324.339207 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68324.339207 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68324.339207 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68324.339207 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 161.632436 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078922 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078922 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits +system.cpu.icache.overall_hits::total 1514 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses +system.cpu.icache.overall_misses::total 451 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -563,48 +570,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 47 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23858000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23858000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23858000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23858000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23858000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23858000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170277 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.170277 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.170277 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70585.798817 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70585.798817 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -622,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23490000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7101750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30591750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3862250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3862250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23490000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10964000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34454000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23490000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10964000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34454000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) @@ -655,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70119.402985 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78041.208791 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71811.619718 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75730.392157 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75730.392157 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72230.607966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72230.607966 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71147.014925 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72443.661972 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72694.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72694.444444 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,17 +692,17 @@ system.cpu.l2cache.demand_mshr_misses::total 477 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19249000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5981750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25230750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3228750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3228750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19249000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9210500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28459500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19249000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9210500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28459500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19597750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5909750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25507500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19597750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9093000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28690750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19597750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9093000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28690750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses @@ -707,27 +714,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57459.701493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65733.516484 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59227.112676 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63308.823529 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63308.823529 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58500.746269 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64942.307692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59876.760563 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62416.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62416.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 91.712882 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.712882 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022391 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits @@ -744,14 +751,14 @@ system.cpu.dcache.demand_misses::cpu.data 510 # n system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10243000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10243000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22828749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22828749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33071749 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33071749 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33071749 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33071749 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10190250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10190250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22575249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22575249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32765499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32765499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32765499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32765499 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -768,19 +775,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69209.459459 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69209.459459 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63062.842541 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63062.842541 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64846.566667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64846.566667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68853.040541 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68853.040541 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62362.566298 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62362.566298 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64246.076471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64246.076471 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.727273 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -800,14 +807,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7196250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7196250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3914249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3914249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11110499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11110499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11110499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11110499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3866249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3866249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10987499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10987499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10987499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10987499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -816,14 +823,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79079.670330 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79079.670330 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76749.980392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76749.980392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78255.494505 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78255.494505 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75808.803922 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75808.803922 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index bf93774ff..800440e86 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18469500 # Number of ticks simulated -final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18905500 # Number of ticks simulated +final_tick 18905500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33738 # Simulator instruction rate (inst/s) -host_op_rate 33735 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107564291 # Simulator tick rate (ticks/s) -host_mem_usage 225768 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 83485 # Simulator instruction rate (inst/s) +host_op_rate 83467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272386071 # Simulator tick rate (ticks/s) +host_mem_usage 250488 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1195484447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 349982403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1545466851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1195484447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1195484447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 446 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 446 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28544 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18341000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 446 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 1167914099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 341911084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1509825183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1167914099 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1167914099 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1167914099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 341911084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1509825183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 446 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 70 # Per bank write bursts +system.physmem.perBankRdBursts::1 42 # Per bank write bursts +system.physmem.perBankRdBursts::2 54 # Per bank write bursts +system.physmem.perBankRdBursts::3 59 # Per bank write bursts +system.physmem.perBankRdBursts::4 53 # Per bank write bursts +system.physmem.perBankRdBursts::5 61 # Per bank write bursts +system.physmem.perBankRdBursts::6 52 # Per bank write bursts +system.physmem.perBankRdBursts::7 13 # Per bank write bursts +system.physmem.perBankRdBursts::8 8 # Per bank write bursts +system.physmem.perBankRdBursts::9 28 # Per bank write bursts +system.physmem.perBankRdBursts::10 2 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 4 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 18777000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 446 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -150,48 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation -system.physmem.totQLat 1996500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10991500 # Sum of mem lat for all requests -system.physmem.totBusLat 2230000 # Total cycles spent in databus access -system.physmem.totBankLat 6765000 # Total cycles spent in bank access -system.physmem.avgQLat 4476.46 # Average queueing delay per request -system.physmem.avgBankLat 15168.16 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24644.62 # Average memory access latency -system.physmem.avgRdBW 1545.47 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1545.47 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.07 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.60 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 380 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.846154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.491272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 472.454851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 36 46.15% 46.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 10.26% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 8 10.26% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 5.13% 71.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 2.56% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 3.85% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.28% 79.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.56% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 2.56% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.56% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.28% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.28% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 2.56% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1 1.28% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 1.28% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.28% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.28% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 2 2.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation +system.physmem.totQLat 3018500 # Total ticks spent queuing +system.physmem.totMemAccLat 11958500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6710000 # Total ticks spent accessing banks +system.physmem.avgQLat 6767.94 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15044.84 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26812.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1509.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1509.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.80 # Data bus utilization in percentage +system.physmem.busUtilRead 11.80 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 368 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41123.32 # Average gap between requests -system.membus.throughput 1545466851 # Throughput (bytes/s) +system.physmem.avgGap 42100.90 # Average gap between requests +system.physmem.pageHitRate 82.51 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1509825183 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -202,10 +211,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 566000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) system.cpu.branchPred.lookups 2238 # Number of BP lookups system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect @@ -234,10 +243,10 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 36940 # number of cpu cycles simulated +system.cpu.numCycles 37812 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7468 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7436 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken @@ -245,27 +254,27 @@ system.cpu.fetch.Cycles 2263 # Nu system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.114583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.531247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.117612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.534017 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9545 80.84% 80.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 1.51% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.49% 83.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.20% 85.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.92% 86.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 133 1.13% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.18% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.93% 91.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1040 8.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9513 80.78% 80.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 1.51% 82.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.49% 83.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.21% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.93% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.13% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.18% 90.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060585 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.356280 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7545 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 11776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059188 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.348064 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7513 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2098 # Number of cycles decode is running system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking @@ -275,7 +284,7 @@ system.cpu.decode.BranchMispred 154 # Nu system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7731 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1987 # Number of cycles rename is running @@ -298,66 +307,66 @@ system.cpu.memDep0.conflictingLoads 52 # Nu system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8904 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4250 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3486 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.753980 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.756114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.487258 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8446 71.53% 71.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1102 9.33% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 787 6.66% 87.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 501 4.24% 91.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 457 3.87% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 305 2.58% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8416 71.47% 71.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.70% 87.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 501 4.25% 91.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.87% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11776 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 73 42.20% 46.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 92 53.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5478 61.52% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued @@ -384,21 +393,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1628 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8903 # Type of FU issued -system.cpu.iq.rate 0.241012 # Inst issue rate -system.cpu.iq.fu_busy_cnt 171 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29964 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8904 # Type of FU issued +system.cpu.iq.rate 0.235481 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019429 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29936 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14577 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8131 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9043 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -425,43 +434,43 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 8503 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3201 # number of memory reference insts executed +system.cpu.iew.exec_refs 3202 # number of memory reference insts executed system.cpu.iew.exec_branches 1351 # Number of branches executed -system.cpu.iew.exec_stores 1523 # Number of stores executed -system.cpu.iew.exec_rate 0.230157 # Inst execution rate -system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8157 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4221 # num instructions producing a value -system.cpu.iew.wb_consumers 6683 # num instructions consuming a value +system.cpu.iew.exec_stores 1524 # Number of stores executed +system.cpu.iew.exec_rate 0.224876 # Inst execution rate +system.cpu.iew.wb_sent 8273 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8158 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4220 # num instructions producing a value +system.cpu.iew.wb_consumers 6682 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.220818 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631603 # average fanout of values written-back +system.cpu.iew.wb_rate 0.215752 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631547 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11099 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.323963 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11067 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.523358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.324283 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8724 78.60% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1004 9.05% 87.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 606 5.46% 93.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 271 2.44% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.97% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 70 0.63% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.41% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8688 78.50% 78.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1007 9.10% 87.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 608 5.49% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 271 2.45% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.54% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.98% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11067 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,22 +483,22 @@ system.cpu.commit.int_insts 5698 # Nu system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21366 # The number of ROB reads +system.cpu.rob.rob_reads 21334 # The number of ROB reads system.cpu.rob.rob_writes 21446 # The number of ROB writes system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25132 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 26036 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 6.377762 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.377762 # CPI: Total CPI of All Threads -system.cpu.ipc 0.156795 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.156795 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13474 # number of integer regfile reads +system.cpu.cpi 6.528315 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.528315 # CPI: Total CPI of All Threads +system.cpu.ipc 0.153179 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.153179 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13476 # number of integer regfile reads system.cpu.int_regfile_writes 7049 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1569723057 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1533521991 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -504,19 +513,19 @@ system.cpu.toL2Bus.data_through_bus 28992 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 590750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 587000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 169.362417 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.362417 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082696 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082696 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits @@ -529,12 +538,12 @@ system.cpu.icache.demand_misses::cpu.inst 442 # n system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses system.cpu.icache.overall_misses::total 442 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28917500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28917500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28917500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28917500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28917500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28917500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30183750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30183750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30183750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30183750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30183750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30183750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses @@ -547,12 +556,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.243660 system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65424.208145 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65424.208145 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65424.208145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65424.208145 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68289.027149 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68289.027149 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68289.027149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68289.027149 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -573,36 +582,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351 system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23457750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23457750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23457750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23457750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23457750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23457750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24475000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24475000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66831.196581 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66831.196581 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.344729 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.344729 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.747174 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.225208 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521966 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006096 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -623,17 +632,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23046250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4132250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27178500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3637250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3637250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23046250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7769500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30815750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23046250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7769500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30815750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24063500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28138000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3590250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3590250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24063500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7664750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31728250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24063500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7664750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31728250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -656,17 +665,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66800.724638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76523.148148 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68116.541353 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77388.297872 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77388.297872 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69093.609865 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69093.609865 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69749.275362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70521.303258 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76388.297872 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76388.297872 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71139.573991 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71139.573991 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -686,17 +695,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18694250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3059750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3059750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18694250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6525500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25219750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18694250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6525500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25219750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23130500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6423750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26143750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6423750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26143750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -708,51 +717,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54186.231884 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64180.555556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55538.847118 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65101.063830 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65101.063830 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57159.420290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57971.177945 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64111.702128 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64111.702128 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.784946 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.784946 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015572 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2192 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2192 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2192 # number of overall hits -system.cpu.dcache.overall_hits::total 2192 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits +system.cpu.dcache.overall_hits::total 2188 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 431 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 431 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 431 # number of overall misses -system.cpu.dcache.overall_misses::total 431 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7388000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7388000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19896996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19896996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27284996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27284996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27284996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27284996 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses +system.cpu.dcache.overall_misses::total 435 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7365250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7365250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19851746 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19851746 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27216996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27216996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27216996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27216996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -763,20 +772,20 @@ system.cpu.dcache.overall_accesses::cpu.data 2623 system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164316 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164316 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164316 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164316 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71038.461538 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71038.461538 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60847.082569 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60847.082569 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63306.255220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63306.255220 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70819.711538 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70819.711538 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59975.063444 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59975.063444 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62567.806897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62567.806897 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -787,12 +796,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -801,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4197750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4197750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3687248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3687248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7884998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7884998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7884998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7884998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3640248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3640248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7780248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7780248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7780248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7780248 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -817,14 +826,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76322.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76322.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78452.085106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78452.085106 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 68c96c714..b34a38ab7 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20802500 # Number of ticks simulated -final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20892500 # Number of ticks simulated +final_tick 20892500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86492 # Simulator instruction rate (inst/s) -host_op_rate 86452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 337526822 # Simulator tick rate (ticks/s) -host_mem_usage 231936 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 70791 # Simulator instruction rate (inst/s) +host_op_rate 70777 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 277537926 # Simulator tick rate (ticks/s) +host_mem_usage 260788 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 889123903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 412258142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1301382045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 889123903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 889123903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 423 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 27072 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 78 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20733000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 423 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 252 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 885293766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 410482230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1295775996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 885293766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 885293766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 885293766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 410482230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1295775996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24 # Per bank write bursts +system.physmem.perBankRdBursts::1 7 # Per bank write bursts +system.physmem.perBankRdBursts::2 1 # Per bank write bursts +system.physmem.perBankRdBursts::3 8 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 78 # Per bank write bursts +system.physmem.perBankRdBursts::6 80 # Per bank write bursts +system.physmem.perBankRdBursts::7 62 # Per bank write bursts +system.physmem.perBankRdBursts::8 35 # Per bank write bursts +system.physmem.perBankRdBursts::9 18 # Per bank write bursts +system.physmem.perBankRdBursts::10 10 # Per bank write bursts +system.physmem.perBankRdBursts::11 52 # Per bank write bursts +system.physmem.perBankRdBursts::12 12 # Per bank write bursts +system.physmem.perBankRdBursts::13 21 # Per bank write bursts +system.physmem.perBankRdBursts::14 7 # Per bank write bursts +system.physmem.perBankRdBursts::15 8 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 20823000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 423 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -150,48 +152,53 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.892308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 170.513476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 484.792485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 29 44.62% 44.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 8 12.31% 56.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 2 3.08% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 6.15% 66.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 1 1.54% 67.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 5 7.69% 75.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2 3.08% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 3.08% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 4 6.15% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 3 4.62% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 1.54% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 1 1.54% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation -system.physmem.totQLat 2859500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11464500 # Sum of mem lat for all requests -system.physmem.totBusLat 2115000 # Total cycles spent in databus access -system.physmem.totBankLat 6490000 # Total cycles spent in bank access -system.physmem.avgQLat 6760.05 # Average queueing delay per request -system.physmem.avgBankLat 15342.79 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27102.84 # Average memory access latency -system.physmem.avgRdBW 1301.38 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1301.38 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.17 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.55 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 358 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 80 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.623207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.187934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 31 38.75% 38.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 11 13.75% 52.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 4 5.00% 57.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 6 7.50% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 1 1.25% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 6 7.50% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 5.00% 78.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 3 3.75% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 6 7.50% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 2.50% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.25% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.25% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 1.25% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.25% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 1 1.25% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 80 # Bytes accessed per row activation +system.physmem.totQLat 3229250 # Total ticks spent queuing +system.physmem.totMemAccLat 11834250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6490000 # Total ticks spent accessing banks +system.physmem.avgQLat 7634.16 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15342.79 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27976.95 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1295.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1295.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.12 # Data bus utilization in percentage +system.physmem.busUtilRead 10.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.57 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 343 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49014.18 # Average gap between requests -system.membus.throughput 1301382045 # Throughput (bytes/s) +system.physmem.avgGap 49226.95 # Average gap between requests +system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1295775996 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution @@ -204,8 +211,8 @@ system.membus.data_through_bus 27072 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3938750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3930250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.8 # Layer utilization (%) system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -216,7 +223,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41606 # number of cpu cycles simulated +system.cpu.numCycles 41786 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -238,12 +245,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9660 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9664 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35361 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35541 # Number of cycles cpu's stages were not processed system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. -system.cpu.activity 15.009854 # Percentage of cycles cpu is active +system.cpu.activity 14.945197 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -255,36 +262,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.810400 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.844190 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.810400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128034 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.844190 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127483 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.128034 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 36966 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127483 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37146 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.152238 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38411 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.104198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38591 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.679181 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38573 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.646102 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38753 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.289814 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40631 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.258412 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40811 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.343412 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.333317 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38629 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.555162 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.907558 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.907558 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069779 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069779 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits @@ -297,12 +304,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25692750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25692750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25692750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25692750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25692750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25692750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25613500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25613500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25613500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25613500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25613500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25613500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -315,12 +322,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70198.770492 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70198.770492 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70198.770492 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70198.770492 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69982.240437 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69982.240437 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69982.240437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69982.240437 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,26 +348,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20948250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20948250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20948250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20948250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20948250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20948250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20868000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20868000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20868000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20868000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20868000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20868000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71987.113402 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71987.113402 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71711.340206 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71711.340206 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1310611705 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1304965897 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -375,21 +382,21 @@ system.cpu.toL2Bus.data_through_bus 27264 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 217250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 169.400750 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.324573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.076177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004343 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000826 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005170 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -410,17 +417,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20629750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3759250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24389000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5820750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5820750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20629750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9580000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30209750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20629750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9580000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30209750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20549500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3769000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24318500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6227750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6227750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20549500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9996750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30546250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20549500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9996750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30546250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -443,17 +450,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71383.217993 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70929.245283 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71312.865497 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71861.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71861.111111 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71417.848700 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71417.848700 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71105.536332 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71113.207547 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71106.725146 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76885.802469 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76885.802469 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72213.356974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72213.356974 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +480,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17007250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20108500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4823250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4823250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17007250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7924500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24931750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17007250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7924500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24931750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16936000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3114000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20050000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5232250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5232250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16936000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8346250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25282250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16936000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8346250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25282250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -495,27 +502,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58848.615917 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58514.150943 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58796.783626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59546.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59546.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58602.076125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58754.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58625.730994 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64595.679012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64595.679012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 85.407936 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 85.407936 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020852 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020852 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -532,14 +539,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4325500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4325500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26675750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26675750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31001250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31001250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31001250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31001250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4332750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4332750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29231250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29231250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33564000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33564000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33564000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33564000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -556,14 +563,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70909.836066 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70909.836066 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64590.193705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64590.193705 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65403.481013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65403.481013 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71028.688525 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71028.688525 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70777.845036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70777.845036 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70810.126582 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70810.126582 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked @@ -588,14 +595,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3825750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3825750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5904250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5904250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9730000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9730000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9730000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9730000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6311250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6311250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10146750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10146750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10146750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10146750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -604,14 +611,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70847.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70847.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72891.975309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72891.975309 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71027.777778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71027.777778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77916.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77916.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 45776fad9..b42a03bbb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19639500 # Number of ticks simulated -final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19970500 # Number of ticks simulated +final_tick 19970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27608 # Simulator instruction rate (inst/s) -host_op_rate 50013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100764572 # Simulator tick rate (ticks/s) -host_mem_usage 247304 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 37809 # Simulator instruction rate (inst/s) +host_op_rate 68492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140319695 # Simulator tick rate (ticks/s) +host_mem_usage 243588 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 892894422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 462740905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1355635327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 892894422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 892894422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 26624 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19591000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 417 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory +system.physmem.bytes_read::total 26496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 414 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 874890463 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 451866503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1326756967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 874890463 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 874890463 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 874890463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 451866503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1326756967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 415 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 33 # Per bank write bursts +system.physmem.perBankRdBursts::1 1 # Per bank write bursts +system.physmem.perBankRdBursts::2 5 # Per bank write bursts +system.physmem.perBankRdBursts::3 8 # Per bank write bursts +system.physmem.perBankRdBursts::4 50 # Per bank write bursts +system.physmem.perBankRdBursts::5 44 # Per bank write bursts +system.physmem.perBankRdBursts::6 20 # Per bank write bursts +system.physmem.perBankRdBursts::7 36 # Per bank write bursts +system.physmem.perBankRdBursts::8 23 # Per bank write bursts +system.physmem.perBankRdBursts::9 73 # Per bank write bursts +system.physmem.perBankRdBursts::10 63 # Per bank write bursts +system.physmem.perBankRdBursts::11 17 # Per bank write bursts +system.physmem.perBankRdBursts::12 2 # Per bank write bursts +system.physmem.perBankRdBursts::13 17 # Per bank write bursts +system.physmem.perBankRdBursts::14 6 # Per bank write bursts +system.physmem.perBankRdBursts::15 17 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 19922000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 415 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,300 +152,305 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.605669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.610045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 42 47.73% 47.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 13 14.77% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12 13.64% 76.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 4.55% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 6 6.82% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 3.41% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.14% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.14% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.14% 94.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.14% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 2.27% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.14% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88 # Bytes accessed per row activation -system.physmem.totQLat 1395750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11125750 # Sum of mem lat for all requests -system.physmem.totBusLat 2085000 # Total cycles spent in databus access -system.physmem.totBankLat 7645000 # Total cycles spent in bank access -system.physmem.avgQLat 3347.12 # Average queueing delay per request -system.physmem.avgBankLat 18333.33 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26680.46 # Average memory access latency -system.physmem.avgRdBW 1355.64 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1355.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.59 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 329 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 226.174757 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.685606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.474459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 47 45.63% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 17 16.50% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 14 13.59% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 4.85% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 5 4.85% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.91% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 3.88% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.94% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 0.97% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 1.94% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.97% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.97% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation +system.physmem.totQLat 2039250 # Total ticks spent queuing +system.physmem.totMemAccLat 11731750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7617500 # Total ticks spent accessing banks +system.physmem.avgQLat 4913.86 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18355.42 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28269.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1329.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1329.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.39 # Data bus utilization in percentage +system.physmem.busUtilRead 10.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 312 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46980.82 # Average gap between requests -system.membus.throughput 1355635327 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 340 # Transaction distribution -system.membus.trans_dist::ReadResp 339 # Transaction distribution +system.physmem.avgGap 48004.82 # Average gap between requests +system.physmem.pageHitRate 75.18 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1326756967 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 338 # Transaction distribution +system.membus.trans_dist::ReadResp 337 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution system.membus.trans_dist::ReadExResp 77 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26624 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26496 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 505500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3891500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) -system.cpu.branchPred.lookups 3060 # Number of BP lookups -system.cpu.branchPred.condPredicted 3060 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2257 # Number of BTB lookups -system.cpu.branchPred.BTBHits 719 # Number of BTB hits +system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3871500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.4 # Layer utilization (%) +system.cpu.branchPred.lookups 3084 # Number of BP lookups +system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups +system.cpu.branchPred.BTBHits 726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.856447 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 208 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39280 # number of cpu cycles simulated +system.cpu.numCycles 39942 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10420 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14154 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3060 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3932 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5289 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 384 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1977 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.145317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.661061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10287 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5300 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.153353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.669079 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18121 82.55% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 212 0.97% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 149 0.68% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 0.99% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 180 0.82% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 202 0.92% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 278 1.27% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 161 0.73% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2432 11.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18006 82.43% 82.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 216 0.99% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 142 0.65% 84.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.03% 85.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 181 0.83% 85.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 200 0.92% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 275 1.26% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 159 0.73% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2442 11.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077902 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11197 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5173 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3579 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1866 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24141 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1866 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11552 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3842 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 569 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3343 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 780 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22717 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 666 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25267 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55251 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 31469 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077212 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.353863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11079 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3583 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11444 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14204 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2015 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2290 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1582 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17094 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 292 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9804 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14093 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21952 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.655311 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.779446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.654421 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16455 74.96% 74.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1544 7.03% 81.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1078 4.91% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 728 3.32% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 707 3.22% 93.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 584 2.66% 96.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 572 2.61% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 242 1.10% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16359 74.89% 74.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1539 7.05% 81.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1092 5.00% 86.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 724 3.31% 90.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 698 3.20% 93.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 576 2.64% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 581 2.66% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21845 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 143 77.72% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.13% 91.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 8.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13719 80.26% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1979 11.58% 91.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1382 8.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17094 # Type of FU issued -system.cpu.iq.rate 0.435183 # Inst issue rate -system.cpu.iq.fu_busy_cnt 184 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010764 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56608 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30145 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15699 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17027 # Type of FU issued +system.cpu.iq.rate 0.426293 # Inst issue rate +system.cpu.iq.fu_busy_cnt 181 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56362 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17271 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1237 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1866 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3033 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3034 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20334 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 50 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2290 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1582 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 113 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 578 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 691 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16182 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1848 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 912 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3125 # number of memory reference insts executed -system.cpu.iew.exec_branches 1615 # Number of branches executed -system.cpu.iew.exec_stores 1277 # Number of stores executed -system.cpu.iew.exec_rate 0.411965 # Inst execution rate -system.cpu.iew.wb_sent 15923 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15703 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10139 # num instructions producing a value -system.cpu.iew.wb_consumers 15623 # num instructions consuming a value +system.cpu.iew.exec_refs 3127 # number of memory reference insts executed +system.cpu.iew.exec_branches 1623 # Number of branches executed +system.cpu.iew.exec_stores 1273 # Number of stores executed +system.cpu.iew.exec_rate 0.403685 # Inst execution rate +system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15646 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10128 # num instructions producing a value +system.cpu.iew.wb_consumers 15579 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399771 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.648979 # average fanout of values written-back +system.cpu.iew.wb_rate 0.391718 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20086 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485263 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.340827 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 19988 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.344274 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16512 82.21% 82.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1365 6.80% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 596 2.97% 91.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 708 3.52% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.36% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16420 82.15% 82.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1360 6.80% 88.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 589 2.95% 91.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 713 3.57% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 364 1.82% 97.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 19988 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -456,138 +463,138 @@ system.cpu.commit.int_insts 9653 # Nu system.cpu.commit.function_calls 106 # Number of function calls committed. system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40219 # The number of ROB reads -system.cpu.rob.rob_writes 42582 # The number of ROB writes -system.cpu.timesIdled 167 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17328 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40049 # The number of ROB reads +system.cpu.rob.rob_writes 42426 # The number of ROB writes +system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18097 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 7.301115 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.301115 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136965 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136965 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 20780 # number of integer regfile reads -system.cpu.int_regfile_writes 12385 # number of integer regfile writes +system.cpu.cpi 7.424164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.424164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.134695 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.134695 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 20727 # number of integer regfile reads +system.cpu.int_regfile_writes 12358 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8044 # number of cc regfile reads -system.cpu.cc_regfile_writes 4852 # number of cc regfile writes -system.cpu.misc_regfile_reads 7122 # number of misc regfile reads +system.cpu.cc_regfile_reads 8004 # number of cc regfile reads +system.cpu.cc_regfile_writes 4850 # number of cc regfile writes +system.cpu.misc_regfile_reads 7135 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1362152804 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 342 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution +system.cpu.toL2Bus.throughput 1333166420 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 463250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 458500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.946729 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1608 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1608 # number of overall hits -system.cpu.icache.overall_hits::total 1608 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses -system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24439500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24439500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24439500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24439500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24439500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24439500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1977 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1977 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1977 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1977 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186646 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186646 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186646 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186646 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186646 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66231.707317 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66231.707317 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66231.707317 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66231.707317 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 130.946729 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063939 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits +system.cpu.icache.overall_hits::total 1609 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses +system.cpu.icache.overall_misses::total 371 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25087750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25087750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25087750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25087750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25087750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25087750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187374 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.187374 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187374 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67621.967655 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67621.967655 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67621.967655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67621.967655 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 70 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 275 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19054250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19054250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19054250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19054250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19054250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19054250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.139100 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.139100 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76905.303030 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70127.941176 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70922.077922 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70922.077922 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70274.580336 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70274.580336 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.993007 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995204 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70891.941392 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76984.615385 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.609467 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70350.649351 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70350.649351 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71745.783133 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71745.783133 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -660,113 +667,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58342.490842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64700 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59565.088757 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57889.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57889.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082302 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082302 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2546 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2546 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2546 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2546 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081937 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081937 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082321 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082321 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082321 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72255.639098 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72255.639098 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74324.675325 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74324.675325 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73014.285714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73014.285714 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 163 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71272.727273 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71272.727273 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73714.285714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73714.285714 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72172.248804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72172.248804 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,38 +783,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 66 system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5151750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5151750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5538000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5538000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10689750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10689750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10689750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10689750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5494000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5494000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10573000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10573000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10573000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10573000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76891.791045 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76891.791045 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71922.077922 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71922.077922 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76954.545455 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76954.545455 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71350.649351 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71350.649351 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |