diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick/se/00.hello | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick/se/00.hello')
28 files changed, 5257 insertions, 4879 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index c9524dba5..954061e30 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 35022500 # Number of ticks simulated -final_tick 35022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 34993500 # Number of ticks simulated +final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71946 # Simulator instruction rate (inst/s) -host_op_rate 71929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 393524726 # Simulator tick rate (ticks/s) -host_mem_usage 237176 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 162128 # Simulator instruction rate (inst/s) +host_op_rate 162075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 885888965 # Simulator tick rate (ticks/s) +host_mem_usage 292456 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 23296 # Nu system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 974002427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 974002427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665172389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665172389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 974002427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 974002427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 974809607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 974809607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34924000 # Total gap between requests +system.physmem.totGap 34895000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -196,19 +196,19 @@ system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # By system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3887500 # Total ticks spent queuing -system.physmem.totMemAccLat 13881250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3849750 # Total ticks spent queuing +system.physmem.totMemAccLat 13843500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7293.62 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7222.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26043.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 974.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25972.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 974.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.00 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 974.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.61 # Data bus utilization in percentage -system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.62 # Data bus utilization in percentage +system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -216,31 +216,36 @@ system.physmem.readRowHits 435 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65523.45 # Average gap between requests +system.physmem.avgGap 65469.04 # Average gap between requests system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 15500 # Time in different power states -system.physmem.memoryStateTime::REF 1040000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 30393500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 140250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 210375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2082600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1677000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 20164320 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1173750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 25645245 # Total energy per rank (pJ) -system.physmem.averagePower::0 827.295718 # Core power per rank (mW) -system.physmem.averagePower::1 815.785757 # Core power per rank (mW) +system.physmem_0.actEnergy 257040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25985700 # Total energy per rank (pJ) +system.physmem_0.averagePower 827.438306 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1677000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 20164320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1173750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25645245 # Total energy per rank (pJ) +system.physmem_1.averagePower 815.785757 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2149750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28549750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1972 # Number of BP lookups system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect @@ -284,26 +289,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 70045 # number of cpu cycles simulated +system.cpu.numCycles 69987 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.944531 # CPI: cycles per instruction -system.cpu.ipc 0.091370 # IPC: instructions per cycle -system.cpu.tickCycles 12615 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57430 # Total number of cycles that the object has spent stopped +system.cpu.cpi 10.935469 # CPI: cycles per instruction +system.cpu.ipc 0.091446 # IPC: instructions per cycle +system.cpu.tickCycles 12616 # Number of cycles that the object actually ticked +system.cpu.idleCycles 57371 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.047628 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.036694 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 104.047628 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.025402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 104.036694 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.025400 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -328,12 +333,12 @@ system.cpu.dcache.overall_misses::cpu.inst 227 # system.cpu.dcache.overall_misses::total 227 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8679250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8679250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 16382500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16382500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 16382500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16382500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8670250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 16373500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 16373500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) @@ -352,12 +357,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69434 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69434 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72169.603524 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72169.603524 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69362 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,12 +389,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 169 system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5128000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5128000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12259000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12259000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12259000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12259000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5119000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5119000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12250000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12250000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses @@ -400,25 +405,25 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076818 system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70123.287671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72485.207101 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72485.207101 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.126032 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 176.047314 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.126032 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085999 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 176.047314 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085961 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses system.cpu.icache.tags.data_accesses 5649 # Number of data accesses @@ -434,12 +439,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25915750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25915750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25915750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25915750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25915750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25915750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25886500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25886500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25886500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25886500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25886500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25886500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses @@ -452,12 +457,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71002.054795 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71002.054795 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70921.917808 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70921.917808 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70921.917808 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70921.917808 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,37 +477,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25028250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25028250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25028250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25028250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25028250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25028250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24998500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24998500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24998500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24998500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24998500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24998500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68489.041096 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68489.041096 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.857006 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.762820 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.857006 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.762820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007134 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses @@ -520,14 +525,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 533 # system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31686750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31686750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5053000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5053000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 36739750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36739750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36739750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36739750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31657000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31657000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5044000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5044000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36701000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36701000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36701000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36701000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) @@ -544,14 +549,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68819.565217 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.890411 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68857.410882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68857.410882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -568,14 +573,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25921750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25921750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30069250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30069250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30069250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30069250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25891500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25891500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30029500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30029500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -584,14 +589,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56285.869565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution @@ -617,7 +622,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) @@ -642,7 +647,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 533 # Request fanout histogram system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4967250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4968000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index c9776266f..7064bc28f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20537500 # Number of ticks simulated final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69014 # Simulator instruction rate (inst/s) -host_op_rate 69006 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 222388397 # Simulator tick rate (ticks/s) -host_mem_usage 237256 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 92569 # Simulator instruction rate (inst/s) +host_op_rate 92553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 298254404 # Simulator tick rate (ticks/s) +host_mem_usage 293992 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 80.08 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 41913.76 # Average gap between requests system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 22000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15339250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 332640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 127875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 181500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1755000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1365000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10809765 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10569510 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 38250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 249000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13982370 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13714770 # Total energy per rank (pJ) -system.physmem.averagePower::0 881.195525 # Core power per rank (mW) -system.physmem.averagePower::1 864.330865 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 415 # Transaction distribution -system.membus.trans_dist::ReadResp 415 # Transaction distribution -system.membus.trans_dist::ReadExReq 72 # Transaction distribution -system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 487 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 487 # Request fanout histogram -system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1755000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10809765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13982370 # Total energy per rank (pJ) +system.physmem_0.averagePower 881.195525 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1365000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10541295 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 252750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13690305 # Total energy per rank (pJ) +system.physmem_1.averagePower 864.696352 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 637250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14974750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2806 # Number of BP lookups system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -605,34 +587,118 @@ system.cpu.fp_regfile_reads 8 # nu system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits +system.cpu.dcache.overall_hits::total 2314 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses +system.cpu.dcache.overall_misses::total 522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. @@ -854,117 +920,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits -system.cpu.dcache.overall_hits::total 2314 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses -system.cpu.dcache.overall_misses::total 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 415 # Transaction distribution +system.membus.trans_dist::ReadResp 415 # Transaction distribution +system.membus.trans_dist::ReadExReq 72 # Transaction distribution +system.membus.trans_dist::ReadExResp 72 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 487 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 487 # Request fanout histogram +system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 95f3db4f2..aeda1c330 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu sim_ticks 138637 # Number of ticks simulated final_tick 138637 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12523 # Simulator instruction rate (inst/s) -host_op_rate 12523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 271684 # Simulator tick rate (ticks/s) -host_mem_usage 436940 # Number of bytes of host memory used -host_seconds 0.51 # Real time elapsed on the host +host_inst_rate 45640 # Simulator instruction rate (inst/s) +host_op_rate 45635 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 990010 # Simulator tick rate (ticks/s) +host_mem_usage 451208 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -237,29 +237,126 @@ system.mem_ctrls.readRowHitRate 81.03 # Ro system.mem_ctrls.writeRowHitRate 75.41 # Row buffer hit rate for writes system.mem_ctrls.avgGap 79.75 # Average gap between requests system.mem_ctrls.pageHitRate 80.50 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 211 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 4420 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 128005 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 559440 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1103760 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 310800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 613200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5828160 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 8112000 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 362880 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 673920 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 75333024 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 89081424 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 13491600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1431600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 104531424 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 109661424 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 788.190677 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 826.872042 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5828160 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 362880 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 75338496 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 13486800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 104532096 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 788.195744 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 25869 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 4420 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 106214 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 8112000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 673920 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 89081424 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1431600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 109661424 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 826.872042 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1728 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 4420 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 126488 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 138637 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 138637 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -279,8 +376,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 15.410630 -system.ruby.latency_hist::gmean 5.220511 -system.ruby.latency_hist::stdev 29.550250 +system.ruby.latency_hist::gmean 5.220490 +system.ruby.latency_hist::stdev 29.556532 system.ruby.latency_hist | 7278 86.15% 86.15% | 1151 13.62% 99.78% | 3 0.04% 99.81% | 2 0.02% 99.83% | 6 0.07% 99.91% | 8 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 @@ -294,8 +391,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1490 system.ruby.miss_latency_hist::mean 73.365772 -system.ruby.miss_latency_hist::gmean 69.379008 -system.ruby.miss_latency_hist::stdev 29.545012 +system.ruby.miss_latency_hist::gmean 69.377440 +system.ruby.miss_latency_hist::stdev 29.580633 system.ruby.miss_latency_hist | 320 21.48% 21.48% | 1151 77.25% 98.72% | 3 0.20% 98.93% | 2 0.13% 99.06% | 6 0.40% 99.46% | 8 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1490 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits @@ -304,7 +401,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5709 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -314,6 +410,10 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 3.776229 system.ruby.network.routers0.msg_count.Control::0 1490 system.ruby.network.routers0.msg_count.Request_Control::2 1041 @@ -331,9 +431,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6392 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328 -system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 7.332278 system.ruby.network.routers1.msg_count.Control::0 2950 system.ruby.network.routers1.msg_count.Request_Control::2 1041 @@ -387,98 +484,6 @@ system.ruby.network.msg_byte.Response_Data 697032 system.ruby.network.msg_byte.Response_Control 114288 system.ruby.network.msg_byte.Writeback_Data 61776 system.ruby.network.msg_byte.Writeback_Control 6984 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 138637 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 138637 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.369057 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490 @@ -609,9 +614,9 @@ system.ruby.LD.miss_latency_hist::total 583 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 17.899422 -system.ruby.ST.latency_hist::gmean 6.261931 -system.ruby.ST.latency_hist::stdev 30.808929 +system.ruby.ST.latency_hist::mean 17.890173 +system.ruby.ST.latency_hist::gmean 6.261514 +system.ruby.ST.latency_hist::stdev 30.772511 system.ruby.ST.latency_hist | 767 88.67% 88.67% | 95 10.98% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 1 @@ -624,17 +629,17 @@ system.ruby.ST.hit_latency_hist::total 649 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 216 -system.ruby.ST.miss_latency_hist::mean 62.666667 -system.ruby.ST.miss_latency_hist::gmean 57.141141 -system.ruby.ST.miss_latency_hist::stdev 33.628615 +system.ruby.ST.miss_latency_hist::mean 62.629630 +system.ruby.ST.miss_latency_hist::gmean 57.125913 +system.ruby.ST.miss_latency_hist::stdev 33.544027 system.ruby.ST.miss_latency_hist | 118 54.63% 54.63% | 95 43.98% 98.61% | 1 0.46% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 2 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 216 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 11.389844 -system.ruby.IFETCH.latency_hist::gmean 4.264766 -system.ruby.IFETCH.latency_hist::stdev 26.115167 +system.ruby.IFETCH.latency_hist::mean 11.391094 +system.ruby.IFETCH.latency_hist::gmean 4.264782 +system.ruby.IFETCH.latency_hist::stdev 26.130654 system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 673 10.52% 99.80% | 1 0.02% 99.81% | 2 0.03% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -647,11 +652,21 @@ system.ruby.IFETCH.hit_latency_hist::total 5709 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 691 -system.ruby.IFETCH.miss_latency_hist::mean 80.706223 -system.ruby.IFETCH.miss_latency_hist::gmean 78.001693 -system.ruby.IFETCH.miss_latency_hist::stdev 30.507480 +system.ruby.IFETCH.miss_latency_hist::mean 80.717800 +system.ruby.IFETCH.miss_latency_hist::gmean 78.004389 +system.ruby.IFETCH.miss_latency_hist::stdev 30.603968 system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 673 97.40% 98.12% | 1 0.14% 98.26% | 2 0.29% 98.55% | 5 0.72% 99.28% | 5 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 691 +system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% +system.ruby.Directory_Controller.Data 277 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 277 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -716,15 +731,5 @@ system.ruby.L2Cache_Controller.ISS.Mem_Data 570 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 686 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 204 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 799 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% -system.ruby.Directory_Controller.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index a7cf38c09..d5c587675 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000126 # Nu sim_ticks 126195 # Number of ticks simulated final_tick 126195 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 17040 # Simulator instruction rate (inst/s) -host_op_rate 17039 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 336486 # Simulator tick rate (ticks/s) -host_mem_usage 440076 # Number of bytes of host memory used -host_seconds 0.38 # Real time elapsed on the host +host_inst_rate 43805 # Simulator instruction rate (inst/s) +host_op_rate 43801 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864948 # Simulator tick rate (ticks/s) +host_mem_usage 454088 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,36 +230,133 @@ system.mem_ctrls.busUtil 4.32 # Da system.mem_ctrls.busUtilRead 4.00 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.41 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 22.42 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 799 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 76 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 79.19 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 68.47 # Row buffer hit rate for writes system.mem_ctrls.avgGap 91.66 # Average gap between requests system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 232 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 4160 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 120458 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 551880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 306600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 4992000 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 7450560 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 186624 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 663552 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 64157832 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 84064968 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 18622800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1160400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 96954696 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 103087560 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 776.656541 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 825.783908 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 551880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 306600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 186624 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 64142784 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 18636000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 96952848 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 776.641738 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 31414 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 4160 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 90106 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1035720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 575400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7450560 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 84064968 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1160400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 103087560 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 825.783908 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1262 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 119428 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 126195 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 126195 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -272,8 +369,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 13.937855 -system.ruby.latency_hist::gmean 4.957822 -system.ruby.latency_hist::stdev 28.418252 +system.ruby.latency_hist::gmean 4.957827 +system.ruby.latency_hist::stdev 28.413153 system.ruby.latency_hist | 7438 88.04% 88.04% | 992 11.74% 99.79% | 2 0.02% 99.81% | 1 0.01% 99.82% | 11 0.13% 99.95% | 3 0.04% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 @@ -287,8 +384,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1421 system.ruby.miss_latency_hist::mean 68.026742 -system.ruby.miss_latency_hist::gmean 59.451623 -system.ruby.miss_latency_hist::stdev 35.838026 +system.ruby.miss_latency_hist::gmean 59.451968 +system.ruby.miss_latency_hist::stdev 35.813966 system.ruby.miss_latency_hist | 411 28.92% 28.92% | 992 69.81% 98.73% | 2 0.14% 98.87% | 1 0.07% 98.94% | 11 0.77% 99.72% | 3 0.21% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1421 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits @@ -297,7 +394,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.974286 system.ruby.network.routers0.msg_count.Request_Control::0 1421 system.ruby.network.routers0.msg_count.Response_Data::2 1182 @@ -311,9 +411,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736 -system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 8.972820 system.ruby.network.routers1.msg_count.Request_Control::0 1421 system.ruby.network.routers1.msg_count.Request_Control::1 1182 @@ -371,98 +468,6 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624 system.ruby.network.msg_byte.Writeback_Data 324432 system.ruby.network.msg_byte.Writeback_Control 74304 system.ruby.network.msg_byte.Unblock_Control 63576 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 126195 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 126195 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.603629 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239 @@ -553,9 +558,9 @@ system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456 system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 29.355030 -system.ruby.LD.latency_hist::gmean 10.774857 -system.ruby.LD.latency_hist::stdev 36.604149 +system.ruby.LD.latency_hist::mean 29.370245 +system.ruby.LD.latency_hist::gmean 10.775321 +system.ruby.LD.latency_hist::stdev 36.738545 system.ruby.LD.latency_hist | 860 72.70% 72.70% | 320 27.05% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 1 @@ -568,9 +573,9 @@ system.ruby.LD.hit_latency_hist::total 658 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 525 -system.ruby.LD.miss_latency_hist::mean 62.386667 -system.ruby.LD.miss_latency_hist::gmean 53.502649 -system.ruby.LD.miss_latency_hist::stdev 32.511258 +system.ruby.LD.miss_latency_hist::mean 62.420952 +system.ruby.LD.miss_latency_hist::gmean 53.507846 +system.ruby.LD.miss_latency_hist::stdev 32.816863 system.ruby.LD.miss_latency_hist | 202 38.48% 38.48% | 320 60.95% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 2 0.38% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 525 system.ruby.ST.latency_hist::bucket_size 64 @@ -599,9 +604,9 @@ system.ruby.ST.miss_latency_hist::total 250 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 10.378594 -system.ruby.IFETCH.latency_hist::gmean 4.114908 -system.ruby.IFETCH.latency_hist::stdev 25.040800 +system.ruby.IFETCH.latency_hist::mean 10.375781 +system.ruby.IFETCH.latency_hist::gmean 4.114880 +system.ruby.IFETCH.latency_hist::stdev 24.994631 system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 564 8.81% 99.83% | 0 0.00% 99.83% | 1 0.02% 99.84% | 8 0.12% 99.97% | 1 0.02% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -614,11 +619,33 @@ system.ruby.IFETCH.hit_latency_hist::total 5754 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 646 -system.ruby.IFETCH.miss_latency_hist::mean 76.100619 -system.ruby.IFETCH.miss_latency_hist::gmean 68.669414 -system.ruby.IFETCH.miss_latency_hist::stdev 37.537546 +system.ruby.IFETCH.miss_latency_hist::mean 76.072755 +system.ruby.IFETCH.miss_latency_hist::gmean 68.664868 +system.ruby.IFETCH.miss_latency_hist::stdev 37.280241 system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 564 87.31% 98.30% | 0 0.00% 98.30% | 1 0.15% 98.45% | 8 1.24% 99.69% | 1 0.15% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 646 +system.ruby.Directory_Controller.GETX 198 0.00% 0.00% +system.ruby.Directory_Controller.GETS 984 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 466 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -696,27 +723,5 @@ system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 52 0.00% system.ruby.L2Cache_Controller.SS.Unblock 141 0.00% 0.00% system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 46 0.00% 0.00% system.ruby.L2Cache_Controller.MI.Writeback_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.GETX 198 0.00% 0.00% -system.ruby.Directory_Controller.GETS 984 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index abe542f63..23f7e060f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000117 # Nu sim_ticks 116770 # Number of ticks simulated final_tick 116770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 333 # Simulator instruction rate (inst/s) -host_op_rate 333 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6085 # Simulator tick rate (ticks/s) -host_mem_usage 436992 # Number of bytes of host memory used -host_seconds 19.19 # Real time elapsed on the host +host_inst_rate 63656 # Simulator instruction rate (inst/s) +host_op_rate 63646 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1162909 # Simulator tick rate (ticks/s) +host_mem_usage 451252 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -236,29 +236,126 @@ system.mem_ctrls.readRowHitRate 79.80 # Ro system.mem_ctrls.writeRowHitRate 77.31 # Row buffer hit rate for writes system.mem_ctrls.avgGap 83.10 # Average gap between requests system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 105625 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 514080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 937440 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 285600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 520800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5041920 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 6764160 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 269568 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 725760 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 60929352 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 72381564 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 12117000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 2071200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 86277360 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 90520764 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 789.557896 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 828.390947 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 514080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 285600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5041920 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 269568 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 60923196 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 12117000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 86271204 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 789.566591 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 22175 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 85821 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 937440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 520800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 725760 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 72391140 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2062800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 90521940 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 828.401709 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2878 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 102769 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 116770 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 116770 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -271,8 +368,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 12.822206 -system.ruby.latency_hist::gmean 3.506831 -system.ruby.latency_hist::stdev 27.804874 +system.ruby.latency_hist::gmean 3.506830 +system.ruby.latency_hist::stdev 27.805292 system.ruby.latency_hist | 7433 87.99% 87.99% | 995 11.78% 99.76% | 6 0.07% 99.83% | 2 0.02% 99.86% | 8 0.09% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 4 @@ -287,8 +384,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1176 system.ruby.miss_latency_hist::mean 75.774660 -system.ruby.miss_latency_hist::gmean 72.686076 -system.ruby.miss_latency_hist::stdev 29.372665 +system.ruby.miss_latency_hist::gmean 72.686009 +system.ruby.miss_latency_hist::stdev 29.375504 system.ruby.miss_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1176 system.ruby.Directory.incomplete_times 1175 @@ -298,7 +395,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 189 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1194 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.578702 system.ruby.network.routers0.msg_count.Request_Control::1 1383 system.ruby.network.routers0.msg_count.Response_Data::4 1176 @@ -312,9 +412,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14904 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 320 -system.ruby.l2_cntrl0.L2cache.demand_hits 189 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1194 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.210200 system.ruby.network.routers1.msg_count.Request_Control::1 1383 system.ruby.network.routers1.msg_count.Request_Control::2 1194 @@ -372,98 +469,6 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 341712 system.ruby.network.msg_byte.Writeback_Control 23184 system.ruby.network.msg_byte.Persistent_Control 960 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 116770 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 116770 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.338700 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1176 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 207 @@ -585,8 +590,8 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 system.ruby.IFETCH.latency_hist::mean 9.334062 -system.ruby.IFETCH.latency_hist::gmean 2.862492 -system.ruby.IFETCH.latency_hist::stdev 24.015420 +system.ruby.IFETCH.latency_hist::gmean 2.862491 +system.ruby.IFETCH.latency_hist::stdev 24.016058 system.ruby.IFETCH.latency_hist | 5815 90.86% 90.86% | 573 8.95% 99.81% | 4 0.06% 99.87% | 0 0.00% 99.87% | 7 0.11% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 4 @@ -601,8 +606,8 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 585 system.ruby.IFETCH.miss_latency_hist::mean 79.849573 -system.ruby.IFETCH.miss_latency_hist::gmean 77.699187 -system.ruby.IFETCH.miss_latency_hist::stdev 27.986383 +system.ruby.IFETCH.miss_latency_hist::gmean 77.699044 +system.ruby.IFETCH.miss_latency_hist::stdev 27.992378 system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 585 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 @@ -624,8 +629,8 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1176 system.ruby.Directory.miss_mach_latency_hist::mean 75.774660 -system.ruby.Directory.miss_mach_latency_hist::gmean 72.686076 -system.ruby.Directory.miss_mach_latency_hist::stdev 29.372665 +system.ruby.Directory.miss_mach_latency_hist::gmean 72.686009 +system.ruby.Directory.miss_mach_latency_hist::stdev 29.375504 system.ruby.Directory.miss_mach_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1176 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -719,10 +724,37 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 585 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 79.849573 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.699187 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.986383 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.699044 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.992378 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 585 +system.ruby.Directory_Controller.GETX 209 0.00% 0.00% +system.ruby.Directory_Controller.GETS 1013 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 219 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 903 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1176 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 228 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 1008 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 18 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 219 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 903 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 5 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 228 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 9 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 9 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -796,32 +828,5 @@ system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 1122 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETX 1 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 9 0.00% 0.00% -system.ruby.Directory_Controller.GETX 209 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1013 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 219 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 903 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1176 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 228 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 1008 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 18 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 219 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 903 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 5 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 228 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 9 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 9 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 72fcefa3c..4d5f2d93a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000096 # Nu sim_ticks 96381 # Number of ticks simulated final_tick 96381 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32379 # Simulator instruction rate (inst/s) -host_op_rate 32376 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 488288 # Simulator tick rate (ticks/s) -host_mem_usage 436896 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 66831 # Simulator instruction rate (inst/s) +host_op_rate 66821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1007748 # Simulator tick rate (ticks/s) +host_mem_usage 449612 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -186,12 +186,12 @@ system.mem_ctrls.wrQLenPdf::62 0 # Wh system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 194 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 352.659794 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 218.108055 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 333.620332 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 54 27.84% 27.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 26.29% 54.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 19 9.79% 63.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 16 8.25% 72.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 217.534506 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 333.874690 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 55 28.35% 28.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 50 25.77% 54.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 18 9.28% 63.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17 8.76% 72.16% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 12 6.19% 78.35% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::640-767 7 3.61% 81.96% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 7 3.61% 85.57% # Bytes accessed per row activation @@ -231,138 +231,42 @@ system.mem_ctrls.busUtil 5.65 # Da system.mem_ctrls.busUtilRead 5.20 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.45 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.25 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 21.24 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 82 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 80.56 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 70.69 # Row buffer hit rate for writes system.mem_ctrls.avgGap 69.83 # Average gap between requests system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3120 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 90575 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 476280 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 975240 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 264600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 541800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5104320 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 7063680 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 238464 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 663552 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 54836964 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 61829496 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 8112600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1978800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 75135948 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 79155288 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 801.946249 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 844.845750 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 10.408736 -system.ruby.latency_hist::gmean 3.320045 -system.ruby.latency_hist::stdev 22.997500 -system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 1 0.01% 99.87% | 6 0.07% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 2 -system.ruby.hit_latency_hist::max_bucket 19 -system.ruby.hit_latency_hist::samples 7289 -system.ruby.hit_latency_hist::mean 2.306352 -system.ruby.hit_latency_hist::gmean 2.107025 -system.ruby.hit_latency_hist::stdev 1.810102 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 7289 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1159 -system.ruby.miss_latency_hist::mean 61.364970 -system.ruby.miss_latency_hist::gmean 57.951867 -system.ruby.miss_latency_hist::stdev 28.728264 -system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 1 0.09% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1159 -system.ruby.Directory.incomplete_times 1158 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 54887580 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 8068200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 75142164 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 802.012594 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 14237 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 77447 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 975240 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 541800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7063680 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 61908840 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1909200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 79165032 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 844.949750 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2762 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 87824 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 4.652888 -system.ruby.network.routers0.msg_count.Request_Control::2 1159 -system.ruby.network.routers0.msg_count.Response_Data::4 1159 -system.ruby.network.routers0.msg_count.Writeback_Data::5 220 -system.ruby.network.routers0.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers0.msg_count.Writeback_Control::5 923 -system.ruby.network.routers0.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers0.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers0.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 4.652888 -system.ruby.network.routers1.msg_count.Request_Control::2 1159 -system.ruby.network.routers1.msg_count.Response_Data::4 1159 -system.ruby.network.routers1.msg_count.Writeback_Data::5 220 -system.ruby.network.routers1.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers1.msg_count.Writeback_Control::5 923 -system.ruby.network.routers1.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers1.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers1.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers2.percent_links_utilized 4.652888 -system.ruby.network.routers2.msg_count.Request_Control::2 1159 -system.ruby.network.routers2.msg_count.Response_Data::4 1159 -system.ruby.network.routers2.msg_count.Writeback_Data::5 220 -system.ruby.network.routers2.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers2.msg_count.Writeback_Control::5 923 -system.ruby.network.routers2.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers2.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers2.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.msg_count.Request_Control 3477 -system.ruby.network.msg_count.Response_Data 3477 -system.ruby.network.msg_count.Writeback_Data 660 -system.ruby.network.msg_count.Writeback_Control 9627 -system.ruby.network.msg_count.Unblock_Control 3477 -system.ruby.network.msg_byte.Request_Control 27816 -system.ruby.network.msg_byte.Response_Data 250344 -system.ruby.network.msg_byte.Writeback_Data 47520 -system.ruby.network.msg_byte.Writeback_Control 77016 -system.ruby.network.msg_byte.Unblock_Control 27816 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -454,6 +358,107 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 8449 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 8449 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 8448 +system.ruby.latency_hist::mean 10.408736 +system.ruby.latency_hist::gmean 3.320047 +system.ruby.latency_hist::stdev 22.995606 +system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 7 0.08% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 8448 +system.ruby.hit_latency_hist::bucket_size 2 +system.ruby.hit_latency_hist::max_bucket 19 +system.ruby.hit_latency_hist::samples 7289 +system.ruby.hit_latency_hist::mean 2.306352 +system.ruby.hit_latency_hist::gmean 2.107025 +system.ruby.hit_latency_hist::stdev 1.810102 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 7289 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1159 +system.ruby.miss_latency_hist::mean 61.364970 +system.ruby.miss_latency_hist::gmean 57.952099 +system.ruby.miss_latency_hist::stdev 28.717200 +system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1159 +system.ruby.Directory.incomplete_times 1158 +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 4.652888 +system.ruby.network.routers0.msg_count.Request_Control::2 1159 +system.ruby.network.routers0.msg_count.Response_Data::4 1159 +system.ruby.network.routers0.msg_count.Writeback_Data::5 220 +system.ruby.network.routers0.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers0.msg_count.Writeback_Control::5 923 +system.ruby.network.routers0.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers0.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers0.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.routers1.percent_links_utilized 4.652888 +system.ruby.network.routers1.msg_count.Request_Control::2 1159 +system.ruby.network.routers1.msg_count.Response_Data::4 1159 +system.ruby.network.routers1.msg_count.Writeback_Data::5 220 +system.ruby.network.routers1.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers1.msg_count.Writeback_Control::5 923 +system.ruby.network.routers1.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers1.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers1.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.routers2.percent_links_utilized 4.652888 +system.ruby.network.routers2.msg_count.Request_Control::2 1159 +system.ruby.network.routers2.msg_count.Response_Data::4 1159 +system.ruby.network.routers2.msg_count.Writeback_Data::5 220 +system.ruby.network.routers2.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers2.msg_count.Writeback_Control::5 923 +system.ruby.network.routers2.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers2.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers2.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.msg_count.Request_Control 3477 +system.ruby.network.msg_count.Response_Data 3477 +system.ruby.network.msg_count.Writeback_Data 660 +system.ruby.network.msg_count.Writeback_Control 9627 +system.ruby.network.msg_count.Unblock_Control 3477 +system.ruby.network.msg_byte.Request_Control 27816 +system.ruby.network.msg_byte.Response_Data 250344 +system.ruby.network.msg_byte.Writeback_Data 47520 +system.ruby.network.msg_byte.Writeback_Control 77016 +system.ruby.network.msg_byte.Unblock_Control 27816 system.ruby.network.routers0.throttle0.link_utilization 6.004295 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143 @@ -554,9 +559,9 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 system.ruby.IFETCH.latency_hist::mean 7.937812 -system.ruby.IFETCH.latency_hist::gmean 2.788276 -system.ruby.IFETCH.latency_hist::stdev 21.096217 -system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 1 0.02% 99.86% | 4 0.06% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::gmean 2.788278 +system.ruby.IFETCH.latency_hist::stdev 21.093490 +system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 2 system.ruby.IFETCH.hit_latency_hist::max_bucket 19 @@ -570,9 +575,9 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 581 system.ruby.IFETCH.miss_latency_hist::mean 66.177281 -system.ruby.IFETCH.miss_latency_hist::gmean 63.049831 -system.ruby.IFETCH.miss_latency_hist::stdev 34.055805 -system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 1 0.17% 98.45% | 4 0.69% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::gmean 63.050334 +system.ruby.IFETCH.miss_latency_hist::stdev 34.037169 +system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 581 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 @@ -592,9 +597,9 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1159 system.ruby.Directory.miss_mach_latency_hist::mean 61.364970 -system.ruby.Directory.miss_mach_latency_hist::gmean 57.951867 -system.ruby.Directory.miss_mach_latency_hist::stdev 28.728264 -system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 1 0.09% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::gmean 57.952099 +system.ruby.Directory.miss_mach_latency_hist::stdev 28.717200 +system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1159 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -684,10 +689,28 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 581 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.177281 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.049831 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.055805 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 1 0.17% 98.45% | 4 0.69% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.050334 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.037169 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 581 +system.ruby.Directory_Controller.GETX 185 0.00% 0.00% +system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% +system.ruby.Directory_Controller.PUT 1143 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1191 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6411 0.00% 0.00% system.ruby.L1Cache_Controller.Store 892 0.00% 0.00% @@ -729,23 +752,5 @@ system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1143 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00% -system.ruby.Directory_Controller.GETX 185 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% -system.ruby.Directory_Controller.PUT 1143 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 01d67d280..e18c35fff 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000124 # Nu sim_ticks 123564 # Number of ticks simulated final_tick 123564 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 34581 # Simulator instruction rate (inst/s) -host_op_rate 34578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 668563 # Simulator tick rate (ticks/s) -host_mem_usage 436724 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 69668 # Simulator instruction rate (inst/s) +host_op_rate 69633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1346306 # Simulator tick rate (ticks/s) +host_mem_usage 450680 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,106 +238,35 @@ system.mem_ctrls.readRowHitRate 75.06 # Ro system.mem_ctrls.writeRowHitRate 92.52 # Row buffer hit rate for writes system.mem_ctrls.avgGap 35.73 # Average gap between requests system.mem_ctrls.pageHitRate 83.97 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11701 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3900 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 101465 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 771120 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1081080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 428400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 600600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 4879680 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 5466240 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 4281984 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 4323456 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 69482088 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 69027912 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 9282000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 9680400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 96753672 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 97808088 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 826.587089 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 835.595188 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 3456 # delay histogram for all message -system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 3456 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 13.626420 -system.ruby.latency_hist::gmean 5.329740 -system.ruby.latency_hist::stdev 25.242996 -system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6718 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6718 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1730 -system.ruby.miss_latency_hist::mean 54.891329 -system.ruby.miss_latency_hist::gmean 49.648144 -system.ruby.miss_latency_hist::stdev 31.153546 -system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1730 -system.ruby.Directory.incomplete_times 1729 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 771120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 428400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4879680 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4281984 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 69480720 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 9282000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 96752304 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 826.589526 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 15125 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 98100 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1081080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 600600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 5466240 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 4323456 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 69027912 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 9680400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 97808088 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 835.595188 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 15368 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 97798 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.992328 -system.ruby.network.routers0.msg_count.Control::2 1730 -system.ruby.network.routers0.msg_count.Data::2 1726 -system.ruby.network.routers0.msg_count.Response_Data::4 1730 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers0.msg_bytes.Control::2 13840 -system.ruby.network.routers0.msg_bytes.Data::2 124272 -system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers1.percent_links_utilized 6.992328 -system.ruby.network.routers1.msg_count.Control::2 1730 -system.ruby.network.routers1.msg_count.Data::2 1726 -system.ruby.network.routers1.msg_count.Response_Data::4 1730 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers1.msg_bytes.Control::2 13840 -system.ruby.network.routers1.msg_bytes.Data::2 124272 -system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.percent_links_utilized 6.992328 -system.ruby.network.routers2.msg_count.Control::2 1730 -system.ruby.network.routers2.msg_count.Data::2 1726 -system.ruby.network.routers2.msg_count.Response_Data::4 1730 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers2.msg_bytes.Control::2 13840 -system.ruby.network.routers2.msg_bytes.Data::2 124272 -system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.msg_count.Control 5190 -system.ruby.network.msg_count.Data 5178 -system.ruby.network.msg_count.Response_Data 5190 -system.ruby.network.msg_count.Writeback_Control 5178 -system.ruby.network.msg_byte.Control 41520 -system.ruby.network.msg_byte.Data 372816 -system.ruby.network.msg_byte.Response_Data 373680 -system.ruby.network.msg_byte.Writeback_Control 41424 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -429,6 +358,82 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 3456 # delay histogram for all message +system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 3456 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 8449 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 8449 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 8448 +system.ruby.latency_hist::mean 13.626420 +system.ruby.latency_hist::gmean 5.329740 +system.ruby.latency_hist::stdev 25.242996 +system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 8448 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 6718 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 6718 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1730 +system.ruby.miss_latency_hist::mean 54.891329 +system.ruby.miss_latency_hist::gmean 49.648144 +system.ruby.miss_latency_hist::stdev 31.153546 +system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1730 +system.ruby.Directory.incomplete_times 1729 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.992328 +system.ruby.network.routers0.msg_count.Control::2 1730 +system.ruby.network.routers0.msg_count.Data::2 1726 +system.ruby.network.routers0.msg_count.Response_Data::4 1730 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers0.msg_bytes.Control::2 13840 +system.ruby.network.routers0.msg_bytes.Data::2 124272 +system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.routers1.percent_links_utilized 6.992328 +system.ruby.network.routers1.msg_count.Control::2 1730 +system.ruby.network.routers1.msg_count.Data::2 1726 +system.ruby.network.routers1.msg_count.Response_Data::4 1730 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers1.msg_bytes.Control::2 13840 +system.ruby.network.routers1.msg_bytes.Data::2 124272 +system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.routers2.percent_links_utilized 6.992328 +system.ruby.network.routers2.msg_count.Control::2 1730 +system.ruby.network.routers2.msg_count.Data::2 1726 +system.ruby.network.routers2.msg_count.Response_Data::4 1730 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers2.msg_bytes.Control::2 13840 +system.ruby.network.routers2.msg_bytes.Data::2 124272 +system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.msg_count.Control 5190 +system.ruby.network.msg_count.Data 5178 +system.ruby.network.msg_count.Response_Data 5190 +system.ruby.network.msg_count.Writeback_Control 5178 +system.ruby.network.msg_byte.Control 41520 +system.ruby.network.msg_byte.Data 372816 +system.ruby.network.msg_byte.Response_Data 373680 +system.ruby.network.msg_byte.Writeback_Control 41424 system.ruby.network.routers0.throttle0.link_utilization 6.998802 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 @@ -596,6 +601,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730 +system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -612,13 +625,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 0513960dd..8eeabeb60 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18733500 # Number of ticks simulated final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41421 # Simulator instruction rate (inst/s) -host_op_rate 41407 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 299977624 # Simulator tick rate (ticks/s) -host_mem_usage 235900 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 81438 # Simulator instruction rate (inst/s) +host_op_rate 81405 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 589715743 # Simulator tick rate (ticks/s) +host_mem_usage 292180 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # By system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation -system.physmem.totQLat 1958750 # Total ticks spent queuing -system.physmem.totMemAccLat 7733750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1952250 # Total ticks spent queuing +system.physmem.totMemAccLat 7727250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6359.58 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6338.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25109.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25088.47 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 83.44 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 60556.82 # Average gap between requests system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 15500 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15310750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 83160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 219240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 45375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 119625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 795600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1294800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10790100 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10507095 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 34500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 282750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 12765855 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13440630 # Total energy per rank (pJ) -system.physmem.averagePower::0 806.306964 # Core power per rank (mW) -system.physmem.averagePower::1 848.926575 # Core power per rank (mW) +system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12765855 # Total energy per rank (pJ) +system.physmem_0.averagePower 806.306964 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 894750 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1294800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10507095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 282750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13440630 # Total energy per rank (pJ) +system.physmem_1.averagePower 848.926575 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 429000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14897250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 793 # Number of BP lookups system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect @@ -296,14 +301,14 @@ system.cpu.ipc 0.068994 # IP system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.468521 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.478730 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 48.468521 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.011833 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011833 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 48.478730 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.011836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011836 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id @@ -326,14 +331,14 @@ system.cpu.dcache.demand_misses::cpu.inst 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4636500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4636500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3517500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3517500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 8154000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8154000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 8154000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8154000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4644500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4644500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3502000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3502000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 8146500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8146500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 8146500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8146500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses) @@ -350,14 +355,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.130653 system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76008.196721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76008.196721 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81802.325581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81802.325581 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78403.846154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78403.846154 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76139.344262 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81441.860465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78331.730769 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 78331.730769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78331.730769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 78331.730769 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,14 +387,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4302500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4302500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2086500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6389000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4310500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4310500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2079250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2079250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6389750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6389750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses @@ -398,24 +403,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.106784 system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74181.034483 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74181.034483 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74318.965517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77009.259259 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75173.529412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75173.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.426247 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 118.465909 # Cycle average of tags in use system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.426247 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057825 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057825 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 118.465909 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057845 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id @@ -434,12 +439,12 @@ system.cpu.icache.demand_misses::cpu.inst 223 # n system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15431500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15431500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15431500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15431500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15431500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15423500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15423500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15423500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15423500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15423500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15423500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses @@ -452,12 +457,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69199.551570 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69199.551570 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69199.551570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69199.551570 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69163.677130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69163.677130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69163.677130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69163.677130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,34 +477,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14892500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14892500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14892500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14892500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14884500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14884500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14884500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14884500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14884500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14884500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.228953 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.228953 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.228953 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66782.511211 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66782.511211 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66746.636771 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66746.636771 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 146.486275 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 146.534478 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.486275 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.534478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004472 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id @@ -516,12 +521,12 @@ system.cpu.l2cache.overall_misses::cpu.inst 308 # system.cpu.l2cache.overall_misses::total 308 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18913000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2059500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2059500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20972500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20972500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2052250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2052250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20965250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20965250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20965250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20965250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 281 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 27 # number of ReadExReq accesses(hits+misses) @@ -540,12 +545,12 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67306.049822 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76277.777778 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76277.777778 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68092.532468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68092.532468 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76009.259259 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68068.993506 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68068.993506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,12 +569,12 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 308 system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15398500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1725500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1725500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17124000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17124000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1718250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17116750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17116750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -580,12 +585,12 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63907.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63907.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63638.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution @@ -613,7 +618,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 154000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 137000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 136750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution @@ -636,7 +641,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 308 # Request fanout histogram system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2868500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2868750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 15.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index dd62dc740..49b58755c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11765500 # Number of ticks simulated final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35174 # Simulator instruction rate (inst/s) -host_op_rate 35164 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173275234 # Simulator tick rate (ticks/s) -host_mem_usage 235920 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 73154 # Simulator instruction rate (inst/s) +host_op_rate 73124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 360297045 # Simulator tick rate (ticks/s) +host_mem_usage 293708 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 81.99 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 42926.47 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 22000 # Time in different power states -system.physmem.memoryStateTime::REF 260000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 7778000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 68040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 158760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 37125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 86625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 631800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 850200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5478840 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5222340 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 246750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 6746115 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 7073235 # Total energy per rank (pJ) -system.physmem.averagePower::0 838.417275 # Core power per rank (mW) -system.physmem.averagePower::1 879.072239 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 248 # Transaction distribution -system.membus.trans_dist::ReadResp 248 # Transaction distribution -system.membus.trans_dist::ReadExReq 24 # Transaction distribution -system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 272 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 631800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 6746115 # Total energy per rank (pJ) +system.physmem_0.averagePower 838.417275 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206000 # Time in different power states +system.physmem_0.memoryStateTime::REF 260000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7778000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 158760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 86625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 850200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5222340 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 7073235 # Total energy per rank (pJ) +system.physmem_1.averagePower 879.072239 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 397500 # Time in different power states +system.physmem_1.memoryStateTime::REF 260000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7402500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1090 # Number of BP lookups system.cpu.branchPred.condPredicted 548 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 231 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 27.520436 # BTB Hit Percentage system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -603,34 +585,118 @@ system.cpu.int_regfile_writes 2774 # nu system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits +system.cpu.dcache.overall_hits::total 729 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses +system.cpu.dcache.overall_misses::total 198 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 92.065177 # Cycle average of tags in use system.cpu.icache.tags.total_refs 685 # Total number of references to valid blocks. @@ -846,117 +912,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits -system.cpu.dcache.overall_hits::total 729 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses -system.cpu.dcache.overall_misses::total 198 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 248 # Transaction distribution +system.membus.trans_dist::ReadResp 248 # Transaction distribution +system.membus.trans_dist::ReadExReq 24 # Transaction distribution +system.membus.trans_dist::ReadExResp 24 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 272 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 272 # Request fanout histogram +system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index d47845159..84bb9ed03 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu sim_ticks 52301 # Number of ticks simulated final_tick 52301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 11256 # Simulator instruction rate (inst/s) -host_op_rate 11255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 228406 # Simulator tick rate (ticks/s) -host_mem_usage 435628 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 42059 # Simulator instruction rate (inst/s) +host_op_rate 42050 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 853239 # Simulator tick rate (ticks/s) +host_mem_usage 450140 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 79.91 # Ro system.mem_ctrls.writeRowHitRate 30.43 # Row buffer hit rate for writes system.mem_ctrls.avgGap 80.33 # Average gap between requests system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 20 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45410 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 173880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 393120 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 96600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 218400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1971840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2907840 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 31347036 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 31310100 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 688200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 720600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 37328916 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 38767308 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 794.638028 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 825.257749 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 173880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 96600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1971840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 31347036 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 688200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 37328916 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 794.638028 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1179 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 44437 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 393120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 218400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2907840 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 31309416 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 721200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 38767224 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 825.255960 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1048 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 44382 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 52301 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 52301 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -299,7 +396,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2285 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 300 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -309,6 +405,10 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 3.803943 system.ruby.network.routers0.msg_count.Control::0 572 system.ruby.network.routers0.msg_count.Request_Control::2 431 @@ -326,9 +426,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 2176 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632 -system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 7.327776 system.ruby.network.routers1.msg_count.Control::0 1119 system.ruby.network.routers1.msg_count.Request_Control::2 431 @@ -382,98 +479,6 @@ system.ruby.network.msg_byte.Response_Data 263952 system.ruby.network.msg_byte.Response_Control 41760 system.ruby.network.msg_byte.Writeback_Data 23112 system.ruby.network.msg_byte.Writeback_Control 1896 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 52301 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 52301 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.452095 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 @@ -647,6 +652,16 @@ system.ruby.IFETCH.miss_latency_hist::gmean 75.006009 system.ruby.IFETCH.miss_latency_hist::stdev 25.337433 system.ruby.IFETCH.miss_latency_hist | 9 3.00% 3.00% | 0 0.00% 3.00% | 276 92.00% 95.00% | 10 3.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 1 0.33% 99.00% | 1 0.33% 99.33% | 1 0.33% 99.67% | 1 0.33% 100.00% system.ruby.IFETCH.miss_latency_hist::total 300 +system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% +system.ruby.Directory_Controller.Data 103 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 103 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 436 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 547 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 103 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 436 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 547 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 103 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -711,15 +726,5 @@ system.ruby.L2Cache_Controller.ISS.Mem_Data 192 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 291 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 64 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 272 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 103 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 103 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 2e81c65b5..b603fabdb 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000048 # Nu sim_ticks 48283 # Number of ticks simulated final_tick 48283 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12943 # Simulator instruction rate (inst/s) -host_op_rate 12941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 242448 # Simulator tick rate (ticks/s) -host_mem_usage 437744 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 45603 # Simulator instruction rate (inst/s) +host_op_rate 45593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 854052 # Simulator tick rate (ticks/s) +host_mem_usage 451760 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 77.66 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 88.76 # Average gap between requests system.mem_ctrls.pageHitRate 72.85 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 76 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45412 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 173880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 446040 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 96600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 247800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1884480 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2808000 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 31539240 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 30693132 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 520800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1263000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 37266360 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 38675220 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 793.272596 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 823.262378 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 173880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 96600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1884480 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 31537872 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 520800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 37264992 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 793.277248 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 968 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 44716 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 446040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 247800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2808000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 30693132 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1263000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 38675220 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 823.262378 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2007 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 43481 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 48283 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 48283 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -292,7 +389,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 79 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 465 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.874739 system.ruby.network.routers0.msg_count.Request_Control::0 544 system.ruby.network.routers0.msg_count.Response_Data::2 465 @@ -306,9 +406,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5688 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512 -system.ruby.l2_cntrl0.L2cache.demand_hits 79 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 465 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 8.967442 system.ruby.network.routers1.msg_count.Request_Control::0 544 system.ruby.network.routers1.msg_count.Request_Control::1 465 @@ -366,98 +463,6 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 17064 system.ruby.network.msg_byte.Writeback_Data 120960 system.ruby.network.msg_byte.Writeback_Control 27840 system.ruby.network.msg_byte.Unblock_Control 24688 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 48283 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 48283 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.589959 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 465 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 79 @@ -614,6 +619,29 @@ system.ruby.IFETCH.miss_latency_hist::gmean 69.413198 system.ruby.IFETCH.miss_latency_hist::stdev 30.681798 system.ruby.IFETCH.miss_latency_hist | 26 9.63% 9.63% | 239 88.52% 98.15% | 2 0.74% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 270 +system.ruby.Directory_Controller.GETX 80 0.00% 0.00% +system.ruby.Directory_Controller.GETS 385 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 262 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 122 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 465 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 123 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 122 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 123 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -691,28 +719,5 @@ system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 12 0.00% system.ruby.L2Cache_Controller.SS.Unblock 51 0.00% 0.00% system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 16 0.00% 0.00% system.ruby.L2Cache_Controller.MI.Writeback_Ack 78 0.00% 0.00% -system.ruby.Directory_Controller.GETX 80 0.00% 0.00% -system.ruby.Directory_Controller.GETS 385 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 122 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 465 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 123 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 122 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 123 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 69664e25a..166a3264e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000044 # Nu sim_ticks 43869 # Number of ticks simulated final_tick 43869 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 107 # Simulator instruction rate (inst/s) -host_op_rate 107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1826 # Simulator tick rate (ticks/s) -host_mem_usage 435688 # Number of bytes of host memory used -host_seconds 24.02 # Real time elapsed on the host +host_inst_rate 63661 # Simulator instruction rate (inst/s) +host_op_rate 63637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1082971 # Simulator tick rate (ticks/s) +host_mem_usage 449944 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 78.40 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 82.31 # Average gap between requests system.mem_ctrls.pageHitRate 73.40 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 37882 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 158760 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 355320 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 88200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 197400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1697280 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2483520 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 25360668 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 26385300 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 1267800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 369000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 31115508 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 32499228 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 793.965501 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 829.273488 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1697280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 25360668 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1267800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 31115508 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 793.965501 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1987 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 35917 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 355320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 197400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2483520 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 26385300 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 369000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 32499228 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 829.273488 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 583 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 37415 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 43869 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 43869 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -294,7 +391,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.531811 system.ruby.network.routers0.msg_count.Request_Control::1 518 system.ruby.network.routers0.msg_count.Response_Data::4 448 @@ -308,9 +408,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 64 -system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.129340 system.ruby.network.routers1.msg_count.Request_Control::1 518 system.ruby.network.routers1.msg_count.Request_Control::2 454 @@ -368,98 +465,6 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 126576 system.ruby.network.msg_byte.Writeback_Control 8760 system.ruby.network.msg_byte.Persistent_Control 192 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 43869 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 43869 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.319246 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 @@ -718,6 +723,32 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.741160 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.366891 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 1 0.40% 98.79% | 3 1.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 247 +system.ruby.Directory_Controller.GETX 61 0.00% 0.00% +system.ruby.Directory_Controller.GETS 398 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 334 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 448 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 84 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 446 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -786,31 +817,5 @@ system.ruby.L2Cache_Controller.M.L1_GETS 52 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 415 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.GETX 61 0.00% 0.00% -system.ruby.Directory_Controller.GETS 398 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 448 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 446 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 391ee4c59..2c1a5d0e0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu sim_ticks 36255 # Number of ticks simulated final_tick 36255 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16369 # Simulator instruction rate (inst/s) -host_op_rate 16367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 230240 # Simulator tick rate (ticks/s) -host_mem_usage 435584 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 60442 # Simulator instruction rate (inst/s) +host_op_rate 60421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 849780 # Simulator tick rate (ticks/s) +host_mem_usage 449324 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 80.27 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 69.32 # Average gap between requests system.mem_ctrls.pageHitRate 75.06 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 30367 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 143640 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 309960 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 79800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 172200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1634880 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2446080 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 20833956 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 21069936 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 567000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 360000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 25293516 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 26558304 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 805.423386 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 845.698128 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 143640 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 79800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1634880 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 20833956 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 567000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 25293516 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 805.423386 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 847 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 29531 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 172200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2446080 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 21069936 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 360000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 26558304 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 845.698128 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1450 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 29876 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 36255 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 36255 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -288,7 +385,9 @@ system.ruby.miss_latency_hist::stdev 26.697338 system.ruby.miss_latency_hist | 59 13.38% 13.38% | 290 65.76% 79.14% | 87 19.73% 98.87% | 1 0.23% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 1 0.23% 99.32% | 3 0.68% 100.00% system.ruby.miss_latency_hist::total 441 system.ruby.Directory.incomplete_times 440 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -298,7 +397,7 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 4.670390 system.ruby.network.routers0.msg_count.Request_Control::2 441 system.ruby.network.routers0.msg_count.Response_Data::4 441 @@ -314,9 +413,6 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.670390 system.ruby.network.routers1.msg_count.Request_Control::2 441 system.ruby.network.routers1.msg_count.Response_Data::4 441 @@ -357,97 +453,6 @@ system.ruby.network.msg_byte.Response_Data 95256 system.ruby.network.msg_byte.Writeback_Data 17496 system.ruby.network.msg_byte.Writeback_Control 28656 system.ruby.network.msg_byte.Unblock_Control 10560 -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 36255 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 36255 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.059854 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 @@ -682,6 +687,25 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 62.229629 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 23.299188 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 199 80.24% 80.24% | 46 18.55% 98.79% | 1 0.40% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 2 0.81% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 248 +system.ruby.Directory_Controller.GETX 51 0.00% 0.00% +system.ruby.Directory_Controller.GETS 409 0.00% 0.00% +system.ruby.Directory_Controller.PUT 425 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 441 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 81 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 425 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 47 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 394 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 440 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 441 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00% system.ruby.L1Cache_Controller.Load 422 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2591 0.00% 0.00% system.ruby.L1Cache_Controller.Store 298 0.00% 0.00% @@ -723,24 +747,5 @@ system.ruby.L1Cache_Controller.MI.Store 4 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 425 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 45 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 24 0.00% 0.00% -system.ruby.Directory_Controller.GETX 51 0.00% 0.00% -system.ruby.Directory_Controller.GETS 409 0.00% 0.00% -system.ruby.Directory_Controller.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 47 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 394 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 58855671d..19e3fb417 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000048 # Nu sim_ticks 47840 # Number of ticks simulated final_tick 47840 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 31483 # Simulator instruction rate (inst/s) -host_op_rate 31473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 584131 # Simulator tick rate (ticks/s) -host_mem_usage 435420 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 35814 # Simulator instruction rate (inst/s) +host_op_rate 35808 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 664620 # Simulator tick rate (ticks/s) +host_mem_usage 449364 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,106 +238,35 @@ system.mem_ctrls.readRowHitRate 74.87 # Ro system.mem_ctrls.writeRowHitRate 87.91 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.30 # Average gap between requests system.mem_ctrls.pageHitRate 81.48 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 140 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45290 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 249480 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 574560 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 138600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 319200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 2009280 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2758080 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 1575936 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 2208384 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 30369600 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 31087116 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 1545600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 916200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 38939856 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 40914900 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 828.930858 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 870.974540 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 1248 # delay histogram for all message -system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1248 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 3295 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 3295 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 13.523376 -system.ruby.latency_hist::gmean 5.183572 -system.ruby.latency_hist::stdev 25.409311 -system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 3294 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 2668 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2668 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 626 -system.ruby.miss_latency_hist::mean 58.373802 -system.ruby.miss_latency_hist::gmean 53.319163 -system.ruby.miss_latency_hist::stdev 30.235728 -system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 626 -system.ruby.Directory.incomplete_times 625 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 249480 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 138600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2009280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1575936 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 30369600 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1545600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 38939856 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 828.930858 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 2928 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 43008 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 574560 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 319200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2758080 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2208384 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 31087116 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 916200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 40914900 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 870.974540 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1359 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 44071 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.521739 -system.ruby.network.routers0.msg_count.Control::2 626 -system.ruby.network.routers0.msg_count.Data::2 622 -system.ruby.network.routers0.msg_count.Response_Data::4 626 -system.ruby.network.routers0.msg_count.Writeback_Control::3 622 -system.ruby.network.routers0.msg_bytes.Control::2 5008 -system.ruby.network.routers0.msg_bytes.Data::2 44784 -system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers1.percent_links_utilized 6.521739 -system.ruby.network.routers1.msg_count.Control::2 626 -system.ruby.network.routers1.msg_count.Data::2 622 -system.ruby.network.routers1.msg_count.Response_Data::4 626 -system.ruby.network.routers1.msg_count.Writeback_Control::3 622 -system.ruby.network.routers1.msg_bytes.Control::2 5008 -system.ruby.network.routers1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.percent_links_utilized 6.521739 -system.ruby.network.routers2.msg_count.Control::2 626 -system.ruby.network.routers2.msg_count.Data::2 622 -system.ruby.network.routers2.msg_count.Response_Data::4 626 -system.ruby.network.routers2.msg_count.Writeback_Control::3 622 -system.ruby.network.routers2.msg_bytes.Control::2 5008 -system.ruby.network.routers2.msg_bytes.Data::2 44784 -system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.msg_count.Control 1878 -system.ruby.network.msg_count.Data 1866 -system.ruby.network.msg_count.Response_Data 1878 -system.ruby.network.msg_count.Writeback_Control 1866 -system.ruby.network.msg_byte.Control 15024 -system.ruby.network.msg_byte.Data 134352 -system.ruby.network.msg_byte.Response_Data 135216 -system.ruby.network.msg_byte.Writeback_Control 14928 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -429,6 +358,82 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 1248 # delay histogram for all message +system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1248 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 3295 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 3295 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 3294 +system.ruby.latency_hist::mean 13.523376 +system.ruby.latency_hist::gmean 5.183572 +system.ruby.latency_hist::stdev 25.409311 +system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 3294 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 2668 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 2668 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 626 +system.ruby.miss_latency_hist::mean 58.373802 +system.ruby.miss_latency_hist::gmean 53.319163 +system.ruby.miss_latency_hist::stdev 30.235728 +system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 626 +system.ruby.Directory.incomplete_times 625 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.521739 +system.ruby.network.routers0.msg_count.Control::2 626 +system.ruby.network.routers0.msg_count.Data::2 622 +system.ruby.network.routers0.msg_count.Response_Data::4 626 +system.ruby.network.routers0.msg_count.Writeback_Control::3 622 +system.ruby.network.routers0.msg_bytes.Control::2 5008 +system.ruby.network.routers0.msg_bytes.Data::2 44784 +system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.routers1.percent_links_utilized 6.521739 +system.ruby.network.routers1.msg_count.Control::2 626 +system.ruby.network.routers1.msg_count.Data::2 622 +system.ruby.network.routers1.msg_count.Response_Data::4 626 +system.ruby.network.routers1.msg_count.Writeback_Control::3 622 +system.ruby.network.routers1.msg_bytes.Control::2 5008 +system.ruby.network.routers1.msg_bytes.Data::2 44784 +system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.routers2.percent_links_utilized 6.521739 +system.ruby.network.routers2.msg_count.Control::2 626 +system.ruby.network.routers2.msg_count.Data::2 622 +system.ruby.network.routers2.msg_count.Response_Data::4 626 +system.ruby.network.routers2.msg_count.Writeback_Control::3 622 +system.ruby.network.routers2.msg_bytes.Control::2 5008 +system.ruby.network.routers2.msg_bytes.Data::2 44784 +system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.msg_count.Control 1878 +system.ruby.network.msg_count.Data 1866 +system.ruby.network.msg_count.Response_Data 1878 +system.ruby.network.msg_count.Writeback_Control 1866 +system.ruby.network.msg_byte.Control 15024 +system.ruby.network.msg_byte.Data 134352 +system.ruby.network.msg_byte.Response_Data 135216 +system.ruby.network.msg_byte.Writeback_Control 14928 system.ruby.network.routers0.throttle0.link_utilization 6.538462 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 @@ -596,6 +601,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.999958 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.587258 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 234 78.79% 78.79% | 49 16.50% 95.29% | 3 1.01% 96.30% | 2 0.67% 96.97% | 7 2.36% 99.33% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297 +system.ruby.Directory_Controller.GETX 626 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -612,13 +625,5 @@ system.ruby.L1Cache_Controller.M.Replacement 622 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 542 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 84 0.00% 0.00% -system.ruby.Directory_Controller.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 1f9a90b5a..58622e09f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27981000 # Number of ticks simulated final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65720 # Simulator instruction rate (inst/s) -host_op_rate 76928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 399296424 # Simulator tick rate (ticks/s) -host_mem_usage 250660 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 95550 # Simulator instruction rate (inst/s) +host_op_rate 111835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 580422337 # Simulator tick rate (ticks/s) +host_mem_usage 309164 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -217,29 +217,34 @@ system.physmem.readRowHitRate 83.14 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 66260.10 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 12000 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22840500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 16099650 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 15972255 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 48750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 160500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 20220195 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 18570765 # Total energy per rank (pJ) -system.physmem.averagePower::0 856.107753 # Core power per rank (mW) -system.physmem.averagePower::1 786.272135 # Core power per rank (mW) +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ) +system.physmem_0.averagePower 856.107753 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ) +system.physmem_1.averagePower 786.272135 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1926 # Number of BP lookups system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect @@ -250,6 +255,14 @@ system.cpu.branchPred.BTBHitPct 20.426065 # BT system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -271,6 +284,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -292,6 +313,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -313,6 +342,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 62f6dcd2b..bac015830 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16223000 # Number of ticks simulated final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26356 # Simulator instruction rate (inst/s) -host_op_rate 30865 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93111675 # Simulator tick rate (ticks/s) -host_mem_usage 251576 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 54860 # Simulator instruction rate (inst/s) +host_op_rate 64243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 193800024 # Simulator tick rate (ticks/s) +host_mem_usage 308908 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -221,53 +221,34 @@ system.physmem.readRowHitRate 83.38 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 40695.21 # Average gap between requests system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 317520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 151200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 173250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 82500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2238600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 795600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10477170 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 309000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 14571510 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 12832590 # Total energy per rank (pJ) -system.physmem.averagePower::0 920.354334 # Core power per rank (mW) -system.physmem.averagePower::1 810.522027 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 355 # Transaction distribution -system.membus.trans_dist::ReadResp 355 # Transaction distribution -system.membus.trans_dist::ReadExReq 42 # Transaction distribution -system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 397 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ) +system.physmem_0.averagePower 920.354334 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ) +system.physmem_1.averagePower 810.522027 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2638 # Number of BP lookups system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect @@ -277,6 +258,15 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -298,6 +288,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -319,6 +317,14 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -340,6 +346,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.walks 0 # Table walker walks requested +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -365,6 +379,14 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 5390 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -386,6 +408,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -407,6 +437,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -428,6 +466,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -744,42 +790,136 @@ system.cpu.cc_regfile_reads 28734 # nu system.cpu.cc_regfile_writes 3302 # number of cc regfile writes system.cpu.misc_regfile_reads 3189 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits +system.cpu.dcache.overall_hits::total 2146 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses +system.cpu.dcache.overall_misses::total 521 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. @@ -1010,135 +1150,64 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits -system.cpu.dcache.overall_hits::total 2146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses -system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 355 # Transaction distribution +system.membus.trans_dist::ReadResp 355 # Transaction distribution +system.membus.trans_dist::ReadExReq 42 # Transaction distribution +system.membus.trans_dist::ReadExResp 42 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 397 # Request fanout histogram +system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 6fc5d6de3..9157ec7b3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11859500 # Number of ticks simulated -final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16487000 # Number of ticks simulated +final_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34923 # Simulator instruction rate (inst/s) -host_op_rate 40896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90188816 # Simulator tick rate (ticks/s) -host_mem_usage 248256 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 33036 # Simulator instruction rate (inst/s) +host_op_rate 38686 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118603969 # Simulator tick rate (ticks/s) +host_mem_usage 248576 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory -system.physmem.bytes_read::total 46848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 732 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 733 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory +system.physmem.bytes_read::total 26048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory +system.physmem.num_reads::total 407 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26112 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 143 # Per bank write bursts -system.physmem.perBankRdBursts::1 90 # Per bank write bursts -system.physmem.perBankRdBursts::2 40 # Per bank write bursts -system.physmem.perBankRdBursts::3 73 # Per bank write bursts -system.physmem.perBankRdBursts::4 58 # Per bank write bursts -system.physmem.perBankRdBursts::5 88 # Per bank write bursts -system.physmem.perBankRdBursts::6 52 # Per bank write bursts -system.physmem.perBankRdBursts::7 18 # Per bank write bursts -system.physmem.perBankRdBursts::8 12 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 34 # Per bank write bursts +system.physmem.perBankRdBursts::0 88 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::2 19 # Per bank write bursts +system.physmem.perBankRdBursts::3 45 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 32 # Per bank write bursts +system.physmem.perBankRdBursts::6 37 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 26 # Per bank write bursts system.physmem.perBankRdBursts::11 47 # Per bank write bursts system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 19 # Per bank write bursts +system.physmem.perBankRdBursts::13 7 # Per bank write bursts system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 14 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11846500 # Total gap between requests +system.physmem.totGap 16473500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 733 # Read request sizes (log2) +system.physmem.readPktSize::6 408 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,98 +190,88 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation -system.physmem.totQLat 17284989 # Total ticks spent queuing -system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 3192729 # Total ticks spent queuing +system.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2040000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 30.90 # Data bus utilization in percentage -system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads +system.physmem.busUtil 12.37 # Data bus utilization in percentage +system.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 662 # Number of row buffer hits during reads +system.physmem.readRowHits 342 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 16161.66 # Average gap between requests -system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 6500 # Time in different power states -system.physmem.memoryStateTime::REF 260000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 7800750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 249480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 90720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 136125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 49500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3088800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1037400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5483970 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5436945 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 63000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 9488685 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 7186125 # Total energy per rank (pJ) -system.physmem.averagePower::0 1178.169797 # Core power per rank (mW) -system.physmem.averagePower::1 892.270681 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 704 # Transaction distribution -system.membus.trans_dist::ReadResp 702 # Transaction distribution -system.membus.trans_dist::ReadExReq 29 # Transaction distribution -system.membus.trans_dist::ReadExResp 29 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 733 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 733 # Request fanout histogram -system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 6.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 55.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2560 # Number of BP lookups -system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups -system.cpu.branchPred.BTBHits 497 # Number of BTB hits +system.physmem.avgGap 40376.23 # Average gap between requests +system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) +system.physmem_0.averagePower 918.403600 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) +system.physmem_1.averagePower 817.101847 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 2361 # Number of BP lookups +system.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups +system.cpu.branchPred.BTBHits 473 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -303,6 +293,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -324,6 +322,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -345,6 +351,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -367,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 23720 # number of cpu cycles simulated +system.cpu.numCycles 32975 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1063 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11322 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3848 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5106 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4105 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5035 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4080 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 320 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 7157 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -452,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7242 # Type of FU issued -system.cpu.iq.rate 0.305312 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 7157 # Type of FU issued +system.cpu.iq.rate 0.217043 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1432 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2449 # number of memory reference insts executed -system.cpu.iew.exec_branches 1283 # Number of branches executed -system.cpu.iew.exec_stores 1021 # Number of stores executed -system.cpu.iew.exec_rate 0.287858 # Inst execution rate -system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6654 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3045 # num instructions producing a value -system.cpu.iew.wb_consumers 5519 # num instructions consuming a value +system.cpu.iew.exec_refs 2417 # number of memory reference insts executed +system.cpu.iew.exec_branches 1277 # Number of branches executed +system.cpu.iew.exec_stores 1017 # Number of stores executed +system.cpu.iew.exec_rate 0.205034 # Inst execution rate +system.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6587 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2990 # num instructions producing a value +system.cpu.iew.wb_consumers 5391 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back +system.cpu.iew.wb_rate 0.199757 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -640,449 +654,469 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24066 # The number of ROB reads -system.cpu.rob.rob_writes 16750 # The number of ROB writes -system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22003 # The number of ROB reads +system.cpu.rob.rob_writes 16441 # The number of ROB writes +system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads -system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6787 # number of integer regfile reads -system.cpu.int_regfile_writes 3839 # number of integer regfile writes +system.cpu.cpi 7.182531 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads +system.cpu.ipc 0.139227 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6737 # number of integer regfile reads +system.cpu.int_regfile_writes 3765 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24301 # number of cc regfile reads -system.cpu.cc_regfile_writes 2919 # number of cc regfile writes -system.cpu.misc_regfile_reads 2642 # number of misc regfile reads +system.cpu.cc_regfile_reads 24010 # number of cc regfile reads +system.cpu.cc_regfile_writes 2910 # number of cc regfile writes +system.cpu.misc_regfile_reads 2599 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1026 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 47 # number of replacements -system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1 # number of replacements +system.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4676 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1876 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1876 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1876 # number of overall hits +system.cpu.dcache.overall_hits::total 1876 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 178 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 178 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 369 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses +system.cpu.dcache.overall_misses::total 369 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15700992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) 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50483.101124 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42550.113821 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42550.113821 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was 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LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 226 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 226 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 226 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20230500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14211250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6019250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22041201 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.725000 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 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ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.309019 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1894 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.244755 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.309019 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1873 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1873 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1873 # number of overall hits -system.cpu.dcache.overall_hits::total 1873 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 194 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 194 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 198 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 198 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses -system.cpu.dcache.overall_misses::total 392 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 67 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 378 # Transaction distribution +system.membus.trans_dist::ReadResp 376 # Transaction distribution +system.membus.trans_dist::ReadExReq 30 # Transaction distribution +system.membus.trans_dist::ReadExResp 30 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 408 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 408 # Request fanout histogram +system.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 23.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 398374723..72322cbec 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 582910 # Simulator instruction rate (inst/s) -host_op_rate 681582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 341032781 # Simulator tick rate (ticks/s) -host_mem_usage 293692 # Number of bytes of host memory used +host_inst_rate 396323 # Simulator instruction rate (inst/s) +host_op_rate 463654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 232084410 # Simulator tick rate (ticks/s) +host_mem_usage 298640 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -35,35 +35,15 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 5596 # Transaction distribution -system.membus.trans_dist::ReadResp 5607 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -85,6 +65,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -106,6 +94,14 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -127,6 +123,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.walks 0 # Table walker walks requested +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -152,6 +156,14 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 0 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -173,6 +185,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -194,6 +214,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -215,6 +243,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -296,5 +332,33 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index d2d36b722..b8c713e42 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 685428 # Simulator instruction rate (inst/s) -host_op_rate 801222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 400788339 # Simulator tick rate (ticks/s) -host_mem_usage 292412 # Number of bytes of host memory used +host_inst_rate 370272 # Simulator instruction rate (inst/s) +host_op_rate 433210 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216878622 # Simulator tick rate (ticks/s) +host_mem_usage 297624 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -35,35 +35,15 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 5596 # Transaction distribution -system.membus.trans_dist::ReadResp 5607 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -85,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -106,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -127,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -209,5 +213,33 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 83a7fcb5f..872a056d2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu sim_ticks 25815000 # Number of ticks simulated final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 367819 # Simulator instruction rate (inst/s) -host_op_rate 428893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2075494452 # Simulator tick rate (ticks/s) -host_mem_usage 302164 # Number of bytes of host memory used +host_inst_rate 376930 # Simulator instruction rate (inst/s) +host_op_rate 439541 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2127142386 # Simulator tick rate (ticks/s) +host_mem_usage 307352 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 557815224 # In system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 307 # Transaction distribution -system.membus.trans_dist::ReadResp 307 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 350 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,118 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits +system.cpu.dcache.overall_hits::total 1764 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses +system.cpu.dcache.overall_misses::total 141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. @@ -416,118 +537,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits -system.cpu.dcache.overall_hits::total 1764 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -560,5 +569,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 361500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 307 # Transaction distribution +system.membus.trans_dist::ReadResp 307 # Transaction distribution +system.membus.trans_dist::ReadExReq 43 # Transaction distribution +system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 350 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 350 # Request fanout histogram +system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1593f969f..a18a67ef2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24417000 # Number of ticks simulated -final_tick 24417000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24407000 # Number of ticks simulated +final_tick 24407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26948 # Simulator instruction rate (inst/s) -host_op_rate 26945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116974890 # Simulator tick rate (ticks/s) -host_mem_usage 277212 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 92117 # Simulator instruction rate (inst/s) +host_op_rate 92097 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 399597243 # Simulator tick rate (ticks/s) +host_mem_usage 289532 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 450 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 820412008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359094074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1179506082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 820412008 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 820412008 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 820412008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359094074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1179506082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 820748146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 359241201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1179989347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 820748146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 820748146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 820748146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 359241201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1179989347 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 450 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 450 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24336000 # Total gap between requests +system.physmem.totGap 24326000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 3 2.91% 94.17% # By system.physmem.bytesPerActivate::896-1023 1 0.97% 95.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 4.85% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 4914500 # Total ticks spent queuing -system.physmem.totMemAccLat 13352000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4895500 # Total ticks spent queuing +system.physmem.totMemAccLat 13333000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10921.11 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10878.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29671.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1179.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29628.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1179.99 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1179.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1179.99 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.21 # Data bus utilization in percentage -system.physmem.busUtilRead 9.21 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.22 # Data bus utilization in percentage +system.physmem.busUtilRead 9.22 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,55 +220,36 @@ system.physmem.readRowHits 344 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54080.00 # Average gap between requests +system.physmem.avgGap 54057.78 # Average gap between requests system.physmem.pageHitRate 76.44 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22851000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 181440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 582120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 99000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 317625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 772200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2652000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 14753880 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 16048350 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1235250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 99750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 18567450 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 21225525 # Total energy per rank (pJ) -system.physmem.averagePower::0 785.799080 # Core power per rank (mW) -system.physmem.averagePower::1 898.292335 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 400 # Transaction distribution -system.membus.trans_dist::ReadResp 400 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 900 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28800 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 450 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 450 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 450 # Request fanout histogram -system.membus.reqLayer0.occupancy 545500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4210750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 772200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14753880 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1232250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 18564450 # Total energy per rank (pJ) +system.physmem_0.averagePower 785.838404 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1971000 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20886000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 582120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 317625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2652000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 16041510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 99750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21218685 # Total energy per rank (pJ) +system.physmem_1.averagePower 898.383064 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 96500 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22756000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1124 # Number of BP lookups system.cpu.branchPred.condPredicted 833 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 586 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 38.705882 # BTB Hit Percentage system.cpu.branchPred.usedRAS 84 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -297,7 +279,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 48835 # number of cpu cycles simulated +system.cpu.numCycles 48815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 421 # Number of Branches Predicted As Taken (True). @@ -322,9 +304,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 9295 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43587 # Number of cycles cpu's stages were not processed +system.cpu.idleCycles 43567 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5248 # Number of cycles cpu stages are processed. -system.cpu.activity 10.746391 # Percentage of cycles cpu is active +system.cpu.activity 10.750794 # Percentage of cycles cpu is active system.cpu.comLoads 1132 # Number of Load instructions committed system.cpu.comStores 901 # Number of Store instructions committed system.cpu.comBranches 883 # Number of Branches instructions committed @@ -336,36 +318,148 @@ system.cpu.committedInsts 5624 # Nu system.cpu.committedOps 5624 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5624 # Number of Instructions committed (Total) -system.cpu.cpi 8.683321 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.679765 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.683321 # CPI: Total CPI of All Threads -system.cpu.ipc 0.115163 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.679765 # CPI: Total CPI of All Threads +system.cpu.ipc 0.115210 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.115163 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45291 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.115210 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45271 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3544 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.257090 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46099 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 7.260064 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46079 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2736 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.602539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46145 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 5.604835 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46125 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2690 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.508344 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47641 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 5.510601 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47621 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1194 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.444968 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46041 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.445969 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46021 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2794 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.721306 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 5.723651 # Percentage of cycles stage was utilized (processing insts). +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 89.114959 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1596 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.649635 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 89.114959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 561 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 561 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1596 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1596 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1596 # number of overall hits +system.cpu.dcache.overall_hits::total 1596 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 340 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 340 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7368000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7368000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20579000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20579000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085689 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085689 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377358 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.377358 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.214953 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.214953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.214953 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.214953 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60526.470588 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60526.470588 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63951.945080 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63951.945080 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63951.945080 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63951.945080 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6703250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6703250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3771500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3771500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10474750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10474750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10474750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10474750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75430 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75430 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76458.029197 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76458.029197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76458.029197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76458.029197 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 147.900639 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 147.861470 # Cycle average of tags in use system.cpu.icache.tags.total_refs 418 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 315 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.326984 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.900639 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072217 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 147.861470 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072198 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072198 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id @@ -384,12 +478,12 @@ system.cpu.icache.demand_misses::cpu.inst 344 # n system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25151000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25151000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25151000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25151000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25151000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25151000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25136000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25136000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25136000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25136000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25136000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25136000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 762 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 762 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 762 # number of demand (read+write) accesses @@ -402,12 +496,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.451444 system.cpu.icache.demand_miss_rate::total 0.451444 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.451444 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.451444 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73113.372093 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73113.372093 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73113.372093 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73113.372093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73113.372093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73113.372093 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73069.767442 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73069.767442 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73069.767442 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73069.767442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73069.767442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73069.767442 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -428,64 +522,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22975000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22975000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22960000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22960000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.413386 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.413386 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.413386 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72936.507937 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72936.507937 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72936.507937 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72936.507937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72936.507937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72936.507937 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72888.888889 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72888.888889 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72888.888889 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72888.888889 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72888.888889 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72888.888889 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 532000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 224750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 204.797884 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 204.748410 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 149.365797 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.432088 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004558 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001692 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006250 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 149.325774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55.422636 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004557 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006248 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id @@ -509,17 +575,17 @@ system.cpu.l2cache.demand_misses::total 450 # nu system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 450 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22634000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22619000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6609750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29243750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3723500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3723500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22634000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10333250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32967250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22634000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10333250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32967250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29228750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3718500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3718500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22619000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10328250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32947250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22619000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10328250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32947250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) @@ -542,17 +608,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995575 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993651 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995575 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72313.099042 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72265.175719 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75974.137931 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73109.375000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74470 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74470 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72313.099042 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75425.182482 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73260.555556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72313.099042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75425.182482 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73260.555556 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73071.875000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74370 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74370 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72265.175719 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75388.686131 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73216.111111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72265.175719 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75388.686131 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73216.111111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,17 +638,17 @@ system.cpu.l2cache.demand_mshr_misses::total 450 system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18704000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18689500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5530750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24234750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3093000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3093000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18704000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8623750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27327750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18704000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8623750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27327750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24220250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3088000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3088000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18689500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8618750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27308250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18689500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8618750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27308250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses @@ -594,129 +660,68 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995575 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995575 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59757.188498 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59710.862620 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63571.839080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60586.875000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61860 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61860 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59757.188498 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62947.080292 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60728.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59757.188498 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62947.080292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60728.333333 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60550.625000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61760 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61760 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59710.862620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62910.583942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59710.862620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62910.583942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60685 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.129655 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1596 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.649635 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.129655 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 561 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 561 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1596 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1596 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1596 # number of overall hits -system.cpu.dcache.overall_hits::total 1596 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 340 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 340 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7368000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7368000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20584000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27952000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27952000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27952000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085689 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085689 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377358 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.377358 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.214953 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.214953 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.214953 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.214953 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60541.176471 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60541.176471 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63963.386728 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63963.386728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63963.386728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63963.386728 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10479750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10479750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10479750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10479750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75530 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75530 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.525547 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.525547 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.525547 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.525547 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 532000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 224750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 400 # Transaction distribution +system.membus.trans_dist::ReadResp 400 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 900 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28800 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 450 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 450 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 450 # Request fanout histogram +system.membus.reqLayer0.occupancy 545500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4210250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 61d4efb5a..ca0260a61 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21163500 # Number of ticks simulated final_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24711 # Simulator instruction rate (inst/s) -host_op_rate 24708 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 104867636 # Simulator tick rate (ticks/s) -host_mem_usage 278232 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 81533 # Simulator instruction rate (inst/s) +host_op_rate 81515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 345921870 # Simulator tick rate (ticks/s) +host_mem_usage 292088 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 75.58 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 44762.21 # Average gap between requests system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 136080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 536760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 74250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 292875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 569400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2285400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 9955620 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10734525 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 766500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 83250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 12518970 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14949930 # Total energy per rank (pJ) -system.physmem.averagePower::0 790.713406 # Core power per rank (mW) -system.physmem.averagePower::1 944.255803 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 421 # Transaction distribution -system.membus.trans_dist::ReadResp 421 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 471 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 136080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 74250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 569400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9948780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 772500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12518130 # Total energy per rank (pJ) +system.physmem_0.averagePower 790.660351 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2505250 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14081250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 536760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 292875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2285400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14949930 # Total energy per rank (pJ) +system.physmem_1.averagePower 944.255803 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 97000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2146 # Number of BP lookups system.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage system.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -589,34 +571,118 @@ system.cpu.int_regfile_writes 5247 # nu system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 164 # number of misc regfile reads -system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits +system.cpu.dcache.overall_hits::total 2445 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses +system.cpu.dcache.overall_misses::total 515 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. @@ -838,117 +904,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits -system.cpu.dcache.overall_hits::total 2445 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses -system.cpu.dcache.overall_misses::total 515 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 421 # Transaction distribution +system.membus.trans_dist::ReadResp 421 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 471 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 471 # Request fanout histogram +system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 3a696e5a2..8476aa73a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000116 # Number of seconds simulated -sim_ticks 115508 # Number of ticks simulated -final_tick 115508 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000115 # Number of seconds simulated +sim_ticks 115467 # Number of ticks simulated +final_tick 115467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 2198 # Simulator instruction rate (inst/s) -host_op_rate 2198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45146 # Simulator tick rate (ticks/s) -host_mem_usage 435400 # Number of bytes of host memory used -host_seconds 2.56 # Real time elapsed on the host +host_inst_rate 66709 # Simulator instruction rate (inst/s) +host_op_rate 66698 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1369179 # Simulator tick rate (ticks/s) +host_mem_usage 449556 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,41 +21,41 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 814489040 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 814489040 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 812272743 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 812272743 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1626761783 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1626761783 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 814778248 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 814778248 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 812561165 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 812561165 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1627339413 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1627339413 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1470 # Number of read requests accepted system.mem_ctrls.writeReqs 1466 # Number of write requests accepted system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 59264 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 34816 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 60672 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 59456 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 34624 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 60800 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 544 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 493 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 491 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 34 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 86 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 65 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 244 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 102 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 43 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 100 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 248 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 103 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 173 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 35 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 36 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts @@ -64,16 +64,16 @@ system.mem_ctrls.perBankWrBursts::5 3 # Pe system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 76 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 244 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 249 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 103 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 110 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 194 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 114 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 182 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 16 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 115437 # Total gap between requests +system.mem_ctrls.totGap 115396 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 926 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 929 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,12 +135,12 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 12 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 16 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 13 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 17 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 64 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 62 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see @@ -184,162 +184,91 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 349 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 341.455587 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 225.575393 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 311.156448 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 80 22.92% 22.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 99 28.37% 51.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 59 16.91% 68.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 25 7.16% 75.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 22 6.30% 81.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 2.58% 84.24% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 12 3.44% 87.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 6 1.72% 89.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 37 10.60% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 349 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 362 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 330.077348 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 218.964738 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 303.831296 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 84 23.20% 23.20% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 104 28.73% 51.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 58 16.02% 67.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 36 9.94% 77.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 19 5.25% 83.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 10 2.76% 85.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 2.49% 88.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.38% 89.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 37 10.22% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 362 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.070175 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.908868 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.750712 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 24 42.11% 45.61% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.105263 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.953786 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.697116 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 1.75% 1.75% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 45.61% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 89.47% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::18-19 5 8.77% 98.25% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.631579 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.601010 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.045937 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 39 68.42% 68.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 5 8.77% 77.19% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 9 15.79% 92.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.637263 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.023533 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 37 64.91% 64.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 6 10.53% 75.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 11 19.30% 94.74% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 3.51% 98.25% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12468 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 30062 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4630 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.46 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 12340 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 29991 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4645 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.28 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.46 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 513.07 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 525.26 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 814.49 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 812.27 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.28 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 514.92 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 526.56 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 814.78 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 812.56 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.11 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.01 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.10 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.14 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.02 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.51 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 626 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 891 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 67.60 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.57 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 39.32 # Average gap between requests -system.mem_ctrls.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 12 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 105626 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 453600 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 2033640 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 252000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 1129800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1547520 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 9409920 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 1213056 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 8107776 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 51518196 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 74359692 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 20367000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 330600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 82471212 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 102491268 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 754.788512 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 938.014973 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2936 # delay histogram for all message -system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2936 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 7659 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 7659 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 7658 -system.ruby.latency_hist::mean 14.083312 -system.ruby.latency_hist::gmean 5.240199 -system.ruby.latency_hist::stdev 27.247033 -system.ruby.latency_hist | 7337 95.81% 95.81% | 269 3.51% 99.32% | 34 0.44% 99.76% | 10 0.13% 99.90% | 4 0.05% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 7658 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6188 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6188 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1470 -system.ruby.miss_latency_hist::mean 60.738776 -system.ruby.miss_latency_hist::gmean 54.828482 -system.ruby.miss_latency_hist::stdev 34.263958 -system.ruby.miss_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1470 -system.ruby.Directory.incomplete_times 1469 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses +system.mem_ctrls.avgWrQLen 25.24 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 618 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 892 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 66.52 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.49 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 39.30 # Average gap between requests +system.mem_ctrls.pageHitRate 79.31 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1684800 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1327104 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 54116712 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 18087600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 83206296 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 761.516108 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 29701 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 76066 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 2079000 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1155000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 9372480 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 74259144 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 418800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 102397992 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 937.161297 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 278 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 105360 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.354538 -system.ruby.network.routers0.msg_count.Control::2 1470 -system.ruby.network.routers0.msg_count.Data::2 1466 -system.ruby.network.routers0.msg_count.Response_Data::4 1470 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers0.msg_bytes.Control::2 11760 -system.ruby.network.routers0.msg_bytes.Data::2 105552 -system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers1.percent_links_utilized 6.354538 -system.ruby.network.routers1.msg_count.Control::2 1470 -system.ruby.network.routers1.msg_count.Data::2 1466 -system.ruby.network.routers1.msg_count.Response_Data::4 1470 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers1.msg_bytes.Control::2 11760 -system.ruby.network.routers1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.percent_links_utilized 6.354538 -system.ruby.network.routers2.msg_count.Control::2 1470 -system.ruby.network.routers2.msg_count.Data::2 1466 -system.ruby.network.routers2.msg_count.Response_Data::4 1470 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers2.msg_bytes.Control::2 11760 -system.ruby.network.routers2.msg_bytes.Data::2 105552 -system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.msg_count.Control 4410 -system.ruby.network.msg_count.Data 4398 -system.ruby.network.msg_count.Response_Data 4410 -system.ruby.network.msg_count.Writeback_Control 4398 -system.ruby.network.msg_byte.Control 35280 -system.ruby.network.msg_byte.Data 316656 -system.ruby.network.msg_byte.Response_Data 317520 -system.ruby.network.msg_byte.Writeback_Control 35184 system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -359,7 +288,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 115508 # number of cpu cycles simulated +system.cpu.numCycles 115467 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -378,7 +307,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 115508 # Number of busy cycles +system.cpu.num_busy_cycles 115467 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -417,32 +346,108 @@ system.cpu.op_class::MemWrite 902 16.04% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction -system.ruby.network.routers0.throttle0.link_utilization 6.361464 +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 2936 # delay histogram for all message +system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 2936 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 7659 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 7659 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 7658 +system.ruby.latency_hist::mean 14.077958 +system.ruby.latency_hist::gmean 5.242569 +system.ruby.latency_hist::stdev 26.858459 +system.ruby.latency_hist | 7322 95.61% 95.61% | 283 3.70% 99.31% | 37 0.48% 99.79% | 6 0.08% 99.87% | 9 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 7658 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 6188 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 6188 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1470 +system.ruby.miss_latency_hist::mean 60.710884 +system.ruby.miss_latency_hist::gmean 54.957755 +system.ruby.miss_latency_hist::stdev 32.665540 +system.ruby.miss_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1470 +system.ruby.Directory.incomplete_times 1469 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.356795 +system.ruby.network.routers0.msg_count.Control::2 1470 +system.ruby.network.routers0.msg_count.Data::2 1466 +system.ruby.network.routers0.msg_count.Response_Data::4 1470 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers0.msg_bytes.Control::2 11760 +system.ruby.network.routers0.msg_bytes.Data::2 105552 +system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers1.percent_links_utilized 6.356795 +system.ruby.network.routers1.msg_count.Control::2 1470 +system.ruby.network.routers1.msg_count.Data::2 1466 +system.ruby.network.routers1.msg_count.Response_Data::4 1470 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers1.msg_bytes.Control::2 11760 +system.ruby.network.routers1.msg_bytes.Data::2 105552 +system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers2.percent_links_utilized 6.356795 +system.ruby.network.routers2.msg_count.Control::2 1470 +system.ruby.network.routers2.msg_count.Data::2 1466 +system.ruby.network.routers2.msg_count.Response_Data::4 1470 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers2.msg_bytes.Control::2 11760 +system.ruby.network.routers2.msg_bytes.Data::2 105552 +system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.msg_count.Control 4410 +system.ruby.network.msg_count.Data 4398 +system.ruby.network.msg_count.Response_Data 4410 +system.ruby.network.msg_count.Writeback_Control 4398 +system.ruby.network.msg_byte.Control 35280 +system.ruby.network.msg_byte.Data 316656 +system.ruby.network.msg_byte.Response_Data 317520 +system.ruby.network.msg_byte.Writeback_Control 35184 +system.ruby.network.routers0.throttle0.link_utilization 6.363723 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers0.throttle1.link_utilization 6.347612 +system.ruby.network.routers0.throttle1.link_utilization 6.349866 system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle0.link_utilization 6.347612 +system.ruby.network.routers1.throttle0.link_utilization 6.349866 system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle1.link_utilization 6.361464 +system.ruby.network.routers1.throttle1.link_utilization 6.363723 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle0.link_utilization 6.361464 +system.ruby.network.routers2.throttle0.link_utilization 6.363723 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle1.link_utilization 6.347612 +system.ruby.network.routers2.throttle1.link_utilization 6.349866 system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 @@ -457,13 +462,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 64 -system.ruby.LD.latency_hist::max_bucket 639 +system.ruby.LD.latency_hist::bucket_size 32 +system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 1132 -system.ruby.LD.latency_hist::mean 35.522968 -system.ruby.LD.latency_hist::gmean 16.130611 -system.ruby.LD.latency_hist::stdev 37.257775 -system.ruby.LD.latency_hist | 989 87.37% 87.37% | 116 10.25% 97.61% | 20 1.77% 99.38% | 4 0.35% 99.73% | 2 0.18% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 35.492049 +system.ruby.LD.latency_hist::gmean 16.147834 +system.ruby.LD.latency_hist::stdev 37.303839 +system.ruby.LD.latency_hist | 465 41.08% 41.08% | 518 45.76% 86.84% | 124 10.95% 97.79% | 3 0.27% 98.06% | 3 0.27% 98.32% | 12 1.06% 99.38% | 2 0.18% 99.56% | 0 0.00% 99.56% | 3 0.27% 99.82% | 2 0.18% 100.00% system.ruby.LD.latency_hist::total 1132 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -472,21 +477,21 @@ system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 465 -system.ruby.LD.miss_latency_hist::bucket_size 64 -system.ruby.LD.miss_latency_hist::max_bucket 639 +system.ruby.LD.miss_latency_hist::bucket_size 32 +system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 667 -system.ruby.LD.miss_latency_hist::mean 58.196402 -system.ruby.LD.miss_latency_hist::gmean 52.112336 -system.ruby.LD.miss_latency_hist::stdev 33.226027 -system.ruby.LD.miss_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 58.143928 +system.ruby.LD.miss_latency_hist::gmean 52.206801 +system.ruby.LD.miss_latency_hist::stdev 33.349415 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% system.ruby.LD.miss_latency_hist::total 667 -system.ruby.ST.latency_hist::bucket_size 64 -system.ruby.ST.latency_hist::max_bucket 639 +system.ruby.ST.latency_hist::bucket_size 32 +system.ruby.ST.latency_hist::max_bucket 319 system.ruby.ST.latency_hist::samples 901 -system.ruby.ST.latency_hist::mean 15.558269 -system.ruby.ST.latency_hist::gmean 5.883337 -system.ruby.ST.latency_hist::stdev 27.738104 -system.ruby.ST.latency_hist | 860 95.45% 95.45% | 33 3.66% 99.11% | 6 0.67% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 14.748058 +system.ruby.ST.latency_hist::gmean 5.824702 +system.ruby.ST.latency_hist::stdev 24.783906 +system.ruby.ST.latency_hist | 684 75.92% 75.92% | 183 20.31% 96.23% | 29 3.22% 99.45% | 0 0.00% 99.45% | 2 0.22% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 901 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -495,21 +500,21 @@ system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist::total 684 -system.ruby.ST.miss_latency_hist::bucket_size 64 -system.ruby.ST.miss_latency_hist::max_bucket 639 +system.ruby.ST.miss_latency_hist::bucket_size 32 +system.ruby.ST.miss_latency_hist::max_bucket 319 system.ruby.ST.miss_latency_hist::samples 217 -system.ruby.ST.miss_latency_hist::mean 55.142857 -system.ruby.ST.miss_latency_hist::gmean 49.160125 -system.ruby.ST.miss_latency_hist::stdev 33.648687 -system.ruby.ST.miss_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 51.778802 +system.ruby.ST.miss_latency_hist::gmean 47.157588 +system.ruby.ST.miss_latency_hist::stdev 27.288529 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 217 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 5625 -system.ruby.IFETCH.latency_hist::mean 9.532444 -system.ruby.IFETCH.latency_hist::gmean 4.102291 -system.ruby.IFETCH.latency_hist::stdev 22.246367 -system.ruby.IFETCH.latency_hist | 5488 97.56% 97.56% | 120 2.13% 99.70% | 8 0.14% 99.84% | 5 0.09% 99.93% | 2 0.04% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.661156 +system.ruby.IFETCH.latency_hist::gmean 4.110524 +system.ruby.IFETCH.latency_hist::stdev 22.183687 +system.ruby.IFETCH.latency_hist | 5472 97.28% 97.28% | 127 2.26% 99.54% | 18 0.32% 99.86% | 4 0.07% 99.93% | 3 0.05% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 5625 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -521,18 +526,18 @@ system.ruby.IFETCH.hit_latency_hist::total 5039 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 586 -system.ruby.IFETCH.miss_latency_hist::mean 65.704778 -system.ruby.IFETCH.miss_latency_hist::gmean 60.488386 -system.ruby.IFETCH.miss_latency_hist::stdev 35.064530 -system.ruby.IFETCH.miss_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 66.940273 +system.ruby.IFETCH.miss_latency_hist::gmean 61.663848 +system.ruby.IFETCH.miss_latency_hist::stdev 32.593558 +system.ruby.IFETCH.miss_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 586 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1470 -system.ruby.Directory.miss_mach_latency_hist::mean 60.738776 -system.ruby.Directory.miss_mach_latency_hist::gmean 54.828482 -system.ruby.Directory.miss_mach_latency_hist::stdev 34.263958 -system.ruby.Directory.miss_mach_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 60.710884 +system.ruby.Directory.miss_mach_latency_hist::gmean 54.957755 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.665540 +system.ruby.Directory.miss_mach_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1470 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -560,30 +565,38 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.196402 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.112336 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.226027 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.143928 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.206801 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.349415 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.142857 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 49.160125 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.648687 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.778802 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.157588 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.288529 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.704778 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 60.488386 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.064530 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.940273 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.663848 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.593558 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 +system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00% system.ruby.L1Cache_Controller.Store 901 0.00% 0.00% @@ -600,13 +613,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index b652069ee..e81ca8aaa 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18857500 # Number of ticks simulated final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71546 # Simulator instruction rate (inst/s) -host_op_rate 71536 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232873039 # Simulator tick rate (ticks/s) -host_mem_usage 233800 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 101158 # Simulator instruction rate (inst/s) +host_op_rate 101133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 329193143 # Simulator tick rate (ticks/s) +host_mem_usage 288984 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 80.18 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 42171.17 # Average gap between requests system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 476280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 68040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 259875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 37125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2644200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 288600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 8055810 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2433000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 15222495 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 11899695 # Total energy per rank (pJ) -system.physmem.averagePower::0 961.471341 # Core power per rank (mW) -system.physmem.averagePower::1 751.599242 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 397 # Transaction distribution -system.membus.trans_dist::ReadResp 397 # Transaction distribution -system.membus.trans_dist::ReadExReq 47 # Transaction distribution -system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 444 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 476280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 259875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2644200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 15222495 # Total energy per rank (pJ) +system.physmem_0.averagePower 961.471341 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8055810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2433000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11899695 # Total energy per rank (pJ) +system.physmem_1.averagePower 751.599242 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4725250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 11341250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2332 # Number of BP lookups system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -589,34 +571,118 @@ system.cpu.int_regfile_reads 13744 # nu system.cpu.int_regfile_writes 7176 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits +system.cpu.dcache.overall_hits::total 2261 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses +system.cpu.dcache.overall_misses::total 452 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. @@ -841,117 +907,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits -system.cpu.dcache.overall_hits::total 2261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses -system.cpu.dcache.overall_misses::total 452 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 397 # Transaction distribution +system.membus.trans_dist::ReadResp 397 # Transaction distribution +system.membus.trans_dist::ReadExReq 47 # Transaction distribution +system.membus.trans_dist::ReadExResp 47 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 444 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 444 # Request fanout histogram +system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 951c5abaa..33e0e9c43 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20927500 # Number of ticks simulated final_tick 20927500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61359 # Simulator instruction rate (inst/s) -host_op_rate 61351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 240990471 # Simulator tick rate (ticks/s) -host_mem_usage 234980 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 82286 # Simulator instruction rate (inst/s) +host_op_rate 82268 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 323129777 # Simulator tick rate (ticks/s) +host_mem_usage 289972 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,53 +220,34 @@ system.physmem.readRowHitRate 80.14 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 49309.69 # Average gap between requests system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 13500 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15312750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 196560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 107250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1497600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1107600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10702035 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10576350 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 111750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 222000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13784220 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13226880 # Total energy per rank (pJ) -system.physmem.averagePower::0 870.628138 # Core power per rank (mW) -system.physmem.averagePower::1 835.425865 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 342 # Transaction distribution -system.membus.trans_dist::ReadResp 342 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 423 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 423 # Request fanout histogram -system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1497600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10702035 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 111750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13784220 # Total energy per rank (pJ) +system.physmem_0.averagePower 870.628138 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 116500 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15209750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 196560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 107250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1107600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10576350 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 222000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13226880 # Total energy per rank (pJ) +system.physmem_1.averagePower 835.425865 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 328000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14998250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -276,6 +257,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 41856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -337,6 +319,118 @@ system.cpu.stage3.utilization 2.329415 # Pe system.cpu.stage4.idleCycles 38699 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 7.542527 # Percentage of cycles stage was utilized (processing insts). +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits +system.cpu.dcache.overall_hits::total 914 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses +system.cpu.dcache.overall_misses::total 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 142.708262 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. @@ -427,34 +521,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 70926.116838 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 169.161112 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. @@ -589,117 +655,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57807.958478 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits -system.cpu.dcache.overall_hits::total 914 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 342 # Transaction distribution +system.membus.trans_dist::ReadResp 342 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 423 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 423 # Request fanout histogram +system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 0a40cf084..51b100b5f 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000096 # Number of seconds simulated -sim_ticks 95992 # Number of ticks simulated -final_tick 95992 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 95989 # Number of ticks simulated +final_tick 95989 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 28429 # Simulator instruction rate (inst/s) -host_op_rate 28426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 512186 # Simulator tick rate (ticks/s) -host_mem_usage 435856 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 73101 # Simulator instruction rate (inst/s) +host_op_rate 73087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1316740 # Simulator tick rate (ticks/s) +host_mem_usage 448980 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,12 +21,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 859404950 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 859404950 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 856738062 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 856738062 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716143012 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1716143012 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 859431810 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 859431810 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 856764838 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 856764838 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716196648 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1716196648 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1289 # Number of read requests accepted system.mem_ctrls.writeReqs 1285 # Number of write requests accepted system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue @@ -73,7 +73,7 @@ system.mem_ctrls.perBankWrBursts::14 18 # Pe system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 95928 # Total gap between requests +system.mem_ctrls.totGap 95925 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -217,16 +217,16 @@ system.mem_ctrls.wrPerTurnAround::17 1 2.33% 83.72% # Wr system.mem_ctrls.wrPerTurnAround::18 2 4.65% 88.37% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::19 5 11.63% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 43 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8746 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 22027 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 8743 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 22024 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 3495 # Total ticks spent in databus transfers system.mem_ctrls.avgQLat 12.51 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 31.51 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 466.04 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 472.04 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 859.40 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 856.74 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgRdBW 466.05 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 472.05 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 859.43 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 856.76 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 7.33 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 3.64 # Data bus utilization in percentage for reads @@ -239,29 +239,94 @@ system.mem_ctrls.readRowHitRate 70.96 # Ro system.mem_ctrls.writeRowHitRate 92.86 # Row buffer hit rate for writes system.mem_ctrls.avgGap 37.27 # Average gap between requests system.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 3037 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3120 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 87552 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 672840 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 373800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5229120 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 3257280 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 4271616 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 2716416 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 59194044 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 56254896 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 4292400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 6870600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 80701020 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 76248552 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 861.316185 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 813.795315 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1035720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 575400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4271616 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 59194044 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 4292400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 80701020 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 861.316185 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 6799 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 83841 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 672840 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 373800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 3257280 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2716416 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 56250108 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 6873000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 76246164 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 813.795884 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 11133 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 79453 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 95989 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5327 # Number of instructions committed +system.cpu.committedOps 5327 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 146 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls +system.cpu.num_int_insts 4505 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 10598 # number of times the integer registers were read +system.cpu.num_int_register_writes 4845 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 1401 # number of memory refs +system.cpu.num_load_insts 723 # Number of load instructions +system.cpu.num_store_insts 678 # Number of store instructions +system.cpu.num_idle_cycles 0.999990 # Number of idle cycles +system.cpu.num_busy_cycles 95988.000010 # Number of busy cycles +system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000010 # Percentage of idle cycles +system.cpu.Branches 1121 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction +system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5370 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -278,9 +343,9 @@ system.ruby.outstanding_req_hist::total 6759 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 6758 -system.ruby.latency_hist::mean 13.204202 -system.ruby.latency_hist::gmean 5.149414 -system.ruby.latency_hist::stdev 25.350800 +system.ruby.latency_hist::mean 13.203759 +system.ruby.latency_hist::gmean 5.149407 +system.ruby.latency_hist::stdev 25.345890 system.ruby.latency_hist | 6535 96.70% 96.70% | 182 2.69% 99.39% | 30 0.44% 99.84% | 2 0.03% 99.87% | 8 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 6758 system.ruby.hit_latency_hist::bucket_size 1 @@ -293,18 +358,17 @@ system.ruby.hit_latency_hist::total 5469 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1289 -system.ruby.miss_latency_hist::mean 56.498836 -system.ruby.miss_latency_hist::gmean 50.965885 -system.ruby.miss_latency_hist::stdev 32.457285 +system.ruby.miss_latency_hist::mean 56.496509 +system.ruby.miss_latency_hist::gmean 50.965481 +system.ruby.miss_latency_hist::stdev 32.440273 system.ruby.miss_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1289 system.ruby.Directory.incomplete_times 1288 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.703684 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.703893 system.ruby.network.routers0.msg_count.Control::2 1289 system.ruby.network.routers0.msg_count.Data::2 1285 system.ruby.network.routers0.msg_count.Response_Data::4 1289 @@ -313,7 +377,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers1.percent_links_utilized 6.703684 +system.ruby.network.routers1.percent_links_utilized 6.703893 system.ruby.network.routers1.msg_count.Control::2 1289 system.ruby.network.routers1.msg_count.Data::2 1285 system.ruby.network.routers1.msg_count.Response_Data::4 1289 @@ -322,7 +386,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.percent_links_utilized 6.703684 +system.ruby.network.routers2.percent_links_utilized 6.703893 system.ruby.network.routers2.msg_count.Control::2 1289 system.ruby.network.routers2.msg_count.Data::2 1285 system.ruby.network.routers2.msg_count.Response_Data::4 1289 @@ -339,91 +403,32 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 -system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 95992 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4845 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.999990 # Number of idle cycles -system.cpu.num_busy_cycles 95991.000010 # Number of busy cycles -system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000010 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.ruby.network.routers0.throttle0.link_utilization 6.712018 +system.ruby.network.routers0.throttle0.link_utilization 6.712227 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers0.throttle1.link_utilization 6.695350 +system.ruby.network.routers0.throttle1.link_utilization 6.695559 system.ruby.network.routers0.throttle1.msg_count.Control::2 1289 system.ruby.network.routers0.throttle1.msg_count.Data::2 1285 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle0.link_utilization 6.695350 +system.ruby.network.routers1.throttle0.link_utilization 6.695559 system.ruby.network.routers1.throttle0.msg_count.Control::2 1289 system.ruby.network.routers1.throttle0.msg_count.Data::2 1285 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle1.link_utilization 6.712018 +system.ruby.network.routers1.throttle1.link_utilization 6.712227 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle0.link_utilization 6.712018 +system.ruby.network.routers2.throttle0.link_utilization 6.712227 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle1.link_utilization 6.695350 +system.ruby.network.routers2.throttle1.link_utilization 6.695559 system.ruby.network.routers2.throttle1.msg_count.Control::2 1289 system.ruby.network.routers2.throttle1.msg_count.Data::2 1285 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 @@ -441,9 +446,9 @@ system.ruby.delayVCHist.vnet_2::total 1285 # de system.ruby.LD.latency_hist::bucket_size 32 system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 715 -system.ruby.LD.latency_hist::mean 30.928671 -system.ruby.LD.latency_hist::gmean 13.876476 -system.ruby.LD.latency_hist::stdev 34.808507 +system.ruby.LD.latency_hist::mean 30.924476 +system.ruby.LD.latency_hist::gmean 13.876278 +system.ruby.LD.latency_hist::stdev 34.776798 system.ruby.LD.latency_hist | 320 44.76% 44.76% | 330 46.15% 90.91% | 50 6.99% 97.90% | 2 0.28% 98.18% | 3 0.42% 98.60% | 6 0.84% 99.44% | 1 0.14% 99.58% | 0 0.00% 99.58% | 2 0.28% 99.86% | 1 0.14% 100.00% system.ruby.LD.latency_hist::total 715 system.ruby.LD.hit_latency_hist::bucket_size 1 @@ -456,9 +461,9 @@ system.ruby.LD.hit_latency_hist::total 320 system.ruby.LD.miss_latency_hist::bucket_size 32 system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 395 -system.ruby.LD.miss_latency_hist::mean 53.554430 -system.ruby.LD.miss_latency_hist::gmean 47.988958 -system.ruby.LD.miss_latency_hist::stdev 32.387704 +system.ruby.LD.miss_latency_hist::mean 53.546835 +system.ruby.LD.miss_latency_hist::gmean 47.987716 +system.ruby.LD.miss_latency_hist::stdev 32.331244 system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% system.ruby.LD.miss_latency_hist::total 395 system.ruby.ST.latency_hist::bucket_size 32 @@ -510,9 +515,9 @@ system.ruby.IFETCH.miss_latency_hist::total 715 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1289 -system.ruby.Directory.miss_mach_latency_hist::mean 56.498836 -system.ruby.Directory.miss_mach_latency_hist::gmean 50.965885 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.457285 +system.ruby.Directory.miss_mach_latency_hist::mean 56.496509 +system.ruby.Directory.miss_mach_latency_hist::gmean 50.965481 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.440273 system.ruby.Directory.miss_mach_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1289 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -544,9 +549,9 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.554430 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.988958 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.387704 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.546835 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.987716 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.331244 system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 @@ -565,6 +570,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 51.762329 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.218674 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715 +system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00% system.ruby.L1Cache_Controller.Load 715 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 5370 0.00% 0.00% system.ruby.L1Cache_Controller.Store 673 0.00% 0.00% @@ -581,13 +594,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1285 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1285 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1110 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 179 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 83799ecfd..3b4d7b677 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19678000 # Number of ticks simulated final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30596 # Simulator instruction rate (inst/s) -host_op_rate 55428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111894824 # Simulator tick rate (ticks/s) -host_mem_usage 253080 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 46918 # Simulator instruction rate (inst/s) +host_op_rate 84992 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171550123 # Simulator tick rate (ticks/s) +host_mem_usage 309548 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,55 +220,34 @@ system.physmem.readRowHitRate 74.10 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 47073.14 # Average gap between requests system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15318250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 219240 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 446040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 119625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 243375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1084200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1567800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10796085 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10703745 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 112500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13267770 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14090580 # Total energy per rank (pJ) -system.physmem.averagePower::0 837.810088 # Core power per rank (mW) -system.physmem.averagePower::1 889.767464 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 339 # Transaction distribution -system.membus.trans_dist::ReadResp 338 # Transaction distribution -system.membus.trans_dist::ReadExReq 78 # Transaction distribution -system.membus.trans_dist::ReadExResp 78 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 417 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1084200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13267770 # Total energy per rank (pJ) +system.physmem_0.averagePower 837.810088 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15318250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 446040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 243375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10701180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 112500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14088015 # Total energy per rank (pJ) +system.physmem_1.averagePower 889.816201 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 882750 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15230750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 3423 # Number of BP lookups system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect @@ -278,6 +257,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 39357 # number of cpu cycles simulated @@ -572,36 +552,116 @@ system.cpu.cc_regfile_reads 8069 # nu system.cpu.cc_regfile_writes 5036 # number of cc regfile writes system.cpu.misc_regfile_reads 7491 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits +system.cpu.dcache.overall_hits::total 2400 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses +system.cpu.dcache.overall_misses::total 214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. @@ -823,115 +883,60 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits -system.cpu.dcache.overall_hits::total 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses -system.cpu.dcache.overall_misses::total 214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 339 # Transaction distribution +system.membus.trans_dist::ReadResp 338 # Transaction distribution +system.membus.trans_dist::ReadExReq 78 # Transaction distribution +system.membus.trans_dist::ReadExResp 78 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 417 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 417 # Request fanout histogram +system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index f27f9e229..6ad7b9146 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu sim_ticks 107237 # Number of ticks simulated final_tick 107237 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14917 # Simulator instruction rate (inst/s) -host_op_rate 27022 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 297251 # Simulator tick rate (ticks/s) -host_mem_usage 452416 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host +host_inst_rate 59170 # Simulator instruction rate (inst/s) +host_op_rate 107175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1178869 # Simulator tick rate (ticks/s) +host_mem_usage 466480 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,29 +238,97 @@ system.mem_ctrls.readRowHitRate 64.11 # Ro system.mem_ctrls.writeRowHitRate 90.98 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.96 # Average gap between requests system.mem_ctrls.pageHitRate 77.75 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 6647 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 91465 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 695520 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1270080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 386400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 705600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 3219840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 4605120 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2623104 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 3784320 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 57894444 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 62913636 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 10102200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 5699400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 81532788 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 85589436 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 803.452847 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 843.428487 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 3219840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 57895812 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10101000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 81532956 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 803.454502 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 16443 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 81669 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1270080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 705600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 4605120 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 3784320 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 62916372 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5697000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 85589772 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 843.431798 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9164 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 89065 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.apic_clk_domain.clock 16 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 107237 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5381 # Number of instructions committed +system.cpu.committedOps 9748 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 209 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls +system.cpu.num_int_insts 9654 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 18335 # number of times the integer registers were read +system.cpu.num_int_register_writes 7527 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written +system.cpu.num_mem_refs 1988 # number of memory refs +system.cpu.num_load_insts 1053 # Number of load instructions +system.cpu.num_store_insts 935 # Number of store instructions +system.cpu.num_idle_cycles 0.999991 # Number of idle cycles +system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles +system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000009 # Percentage of idle cycles +system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -278,8 +346,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8852 system.ruby.latency_hist::mean 11.114437 -system.ruby.latency_hist::gmean 4.638311 -system.ruby.latency_hist::stdev 22.978637 +system.ruby.latency_hist::gmean 4.638310 +system.ruby.latency_hist::stdev 22.979355 system.ruby.latency_hist | 8594 97.09% 97.09% | 215 2.43% 99.51% | 29 0.33% 99.84% | 6 0.07% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8852 system.ruby.hit_latency_hist::bucket_size 1 @@ -293,16 +361,15 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1377 system.ruby.miss_latency_hist::mean 55.163399 -system.ruby.miss_latency_hist::gmean 49.389613 -system.ruby.miss_latency_hist::stdev 33.121212 +system.ruby.miss_latency_hist::gmean 49.389540 +system.ruby.miss_latency_hist::stdev 33.124416 system.ruby.miss_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1377 system.ruby.Directory.incomplete_times 1376 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 6.411034 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 @@ -338,68 +405,6 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.cpu.apic_clk_domain.clock 16 # Clock period in ticks -system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 107237 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.999991 # Number of idle cycles -system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles -system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000009 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.418494 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 @@ -490,8 +495,8 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6864 system.ruby.IFETCH.latency_hist::mean 8.263112 -system.ruby.IFETCH.latency_hist::gmean 3.900454 -system.ruby.IFETCH.latency_hist::stdev 20.208626 +system.ruby.IFETCH.latency_hist::gmean 3.900453 +system.ruby.IFETCH.latency_hist::stdev 20.209679 system.ruby.IFETCH.latency_hist | 6731 98.06% 98.06% | 102 1.49% 99.55% | 22 0.32% 99.87% | 3 0.04% 99.91% | 5 0.07% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6864 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -505,8 +510,8 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 623 system.ruby.IFETCH.miss_latency_hist::mean 60.987159 -system.ruby.IFETCH.miss_latency_hist::gmean 54.083768 -system.ruby.IFETCH.miss_latency_hist::stdev 37.997755 +system.ruby.IFETCH.miss_latency_hist::gmean 54.083593 +system.ruby.IFETCH.miss_latency_hist::stdev 38.003932 system.ruby.IFETCH.miss_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 623 system.ruby.RMW_Read.latency_hist::bucket_size 4 @@ -536,8 +541,8 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1377 system.ruby.Directory.miss_mach_latency_hist::mean 55.163399 -system.ruby.Directory.miss_mach_latency_hist::gmean 49.389613 -system.ruby.Directory.miss_mach_latency_hist::stdev 33.121212 +system.ruby.Directory.miss_mach_latency_hist::gmean 49.389540 +system.ruby.Directory.miss_mach_latency_hist::stdev 33.124416 system.ruby.Directory.miss_mach_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1377 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -586,8 +591,8 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 60.987159 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083768 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 37.997755 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083593 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 38.003932 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 @@ -598,6 +603,14 @@ system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 34.000000 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 +system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% system.ruby.L1Cache_Controller.Store 943 0.00% 0.00% @@ -614,13 +627,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% ---------- End Simulation Statistics ---------- |