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authorAni Udipi <ani.udipi@arm.com>2013-01-31 07:49:14 -0500
committerAni Udipi <ani.udipi@arm.com>2013-01-31 07:49:14 -0500
commiteaa37e611f07a41d97a078bf2588bfe745d83751 (patch)
treea3f8db3defdc6c3af0e7a0670fb9e7d7139d3f00 /tests/quick/se/00.hello
parentb7153e2a64bdb88cebe96e59b24d5597a3a42205 (diff)
downloadgem5-eaa37e611f07a41d97a078bf2588bfe745d83751.tar.xz
mem: Add tTAW and tFAW to the SimpleDRAM model
This patch adds two additional scheduling constraints to the DRAM controller model, to constrain the activation rate. The two metrics are determine the size of the activation window in terms of the number of activates and the minimum time required for that number of activates. This maps to current DDRx, LPDDRx and WIOx standards that have either tFAW (4 activate window) or tTAW (2 activate window) scheduling constraints.
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