stats: Cumulative stats update

This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.

1 files changed, 54 insertions, 87 deletions

diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 099eda912..d195e9d48 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000024                       # Nu
 sim_ticks                                    24404000                       # Number of ticks simulated
 final_tick                                   24404000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  52847                       # Simulator instruction rate (inst/s)
-host_op_rate                                    52845                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              101181200                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228064                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
+host_inst_rate                                    780                       # Simulator instruction rate (inst/s)
+host_op_rate                                      780                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1494307                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227936                       # Number of bytes of host memory used
+host_seconds                                    16.33                       # Real time elapsed on the host
 sim_insts                                       12745                       # Number of instructions simulated
 sim_ops                                         12745                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             39936                       # Number of bytes read from this memory
@@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total         1636453040                       # In
 system.physmem.bw_total::cpu.inst          1636453040                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data           917882314                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total             2554335355                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           974                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                            974                       # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs                           974                       # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs                            0                       # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts                         974                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts                          0                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
 system.physmem.bytesRead                        62336                       # Total number of bytes read from memory
 system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
 system.physmem.bytesConsumedRd                  62336                       # bytesRead derated as per pkt->getSize()
 system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by write Q
 system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
 system.physmem.perBankRdReqs::0                    83                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::1                   153                       # Track reads on a per bank basis
@@ -205,10 +206,10 @@ system.membus.trans_dist::ReadReq                 828                       # Tr
 system.membus.trans_dist::ReadResp                828                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               146                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              146                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side         1948                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                          1948                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side        62336                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                      62336                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1948                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1948                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62336                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               62336                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  62336                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy             1227000                       # Layer occupancy (ticks)
@@ -452,41 +453,7 @@ system.cpu.iq.FU_type_1::MemWrite                1105     10.23%    100.00% # Ty
 system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::total                  10798                       # Type of FU issued
-system.cpu.iq.FU_type::No_OpClass                   4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type::IntAlu                   14327     65.73%     65.75% # Type of FU issued
-system.cpu.iq.FU_type::IntMult                      2      0.01%     65.76% # Type of FU issued
-system.cpu.iq.FU_type::IntDiv                       0      0.00%     65.76% # Type of FU issued
-system.cpu.iq.FU_type::FloatAdd                     4      0.02%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::FloatCmp                     0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::FloatCvt                     0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::FloatMult                    0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::FloatDiv                     0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::FloatSqrt                    0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdAdd                      0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdAddAcc                   0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdAlu                      0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdCmp                      0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdCvt                      0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdMisc                     0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdMult                     0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdMultAcc                  0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdShift                    0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdShiftAcc                 0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdSqrt                     0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAdd                 0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAlu                 0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCmp                 0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCvt                 0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatDiv                 0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMisc                0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMult                0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMultAcc             0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatSqrt                0      0.00%     65.78% # Type of FU issued
-system.cpu.iq.FU_type::MemRead                   5217     23.94%     89.71% # Type of FU issued
-system.cpu.iq.FU_type::MemWrite                  2242     10.29%    100.00% # Type of FU issued
-system.cpu.iq.FU_type::IprAccess                    0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type::InstPrefetch                 0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type::total                    21796                       # Type of FU issued
+system.cpu.iq.FU_type::total                    21796      0.00%      0.00% # Type of FU issued
 system.cpu.iq.rate                           0.446557                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt::0                       89                       # FU busy when requested
 system.cpu.iq.fu_busy_cnt::1                       86                       # FU busy when requested
@@ -662,12 +629,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq            830                       # Tr
 system.cpu.toL2Bus.trans_dist::ReadResp           830                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq          146                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp          146                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side         1252                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side          700                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                     1952                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        40064                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side        22400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size                 62464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1252                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          700                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1952                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40064                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          62464                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus             62464                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         488000                       # Layer occupancy (ticks)
@@ -676,17 +643,17 @@ system.cpu.toL2Bus.respLayer0.occupancy       1029500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          4.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        566500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
-system.cpu.icache.tags.replacements::0                   6                       # number of replacements
-system.cpu.icache.tags.replacements::1                   0                       # number of replacements
-system.cpu.icache.tags.replacements::total               6                       # number of replacements
-system.cpu.icache.tags.tagsinuse                309.632563                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     4375                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    626                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   6.988818                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     309.632563                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.151188                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.151188                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements::0              6                       # number of replacements
+system.cpu.icache.tags.replacements::1              0                       # number of replacements
+system.cpu.icache.tags.replacements::total            6                       # number of replacements
+system.cpu.icache.tags.tagsinuse           309.632563                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                4375                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               626                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.988818                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   309.632563                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.151188                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.151188                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         4375                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            4375                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          4375                       # number of demand (read+write) hits
@@ -762,19 +729,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 75077.070288
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75077.070288                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 75077.070288                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements::0                  0                       # number of replacements
-system.cpu.l2cache.tags.replacements::1                  0                       # number of replacements
-system.cpu.l2cache.tags.replacements::total              0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               428.856997                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   828                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.002415                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    310.126222                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    118.730775                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
+system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
+system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          428.856997                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              828                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002415                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   310.126222                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   118.730775                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009464                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.003623                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.013088                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.013088                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -889,17 +856,17 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61815.705128
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        68000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64037.987680                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements::0                   0                       # number of replacements
-system.cpu.dcache.tags.replacements::1                   0                       # number of replacements
-system.cpu.dcache.tags.replacements::total               0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                211.884963                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     4493                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    350                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  12.837143                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     211.884963                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.051730                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.051730                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements::0              0                       # number of replacements
+system.cpu.dcache.tags.replacements::1              0                       # number of replacements
+system.cpu.dcache.tags.replacements::total            0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           211.884963                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4493                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               350                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.837143                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   211.884963                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.051730                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.051730                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         3469                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            3469                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1024                       # number of WriteReq hits