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author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
commit | f3585c841e964c98911784a187fc4f081a02a0a6 (patch) | |
tree | 2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf /tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing | |
parent | cfc4a999828a5b51f4c514e3a7c47b4eebc450b9 (diff) | |
download | gem5-f3585c841e964c98911784a187fc4f081a02a0a6.tar.xz |
stats: update stats for cache occupancy and clock domain changes
Diffstat (limited to 'tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing')
4 files changed, 40 insertions, 12 deletions
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 708085ca5..39d7de978 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,10 +533,12 @@ eventq_index=0 [system.cpu.isa0] type=AlphaISA eventq_index=0 +system=system [system.cpu.isa1] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -554,6 +560,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -570,6 +577,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -596,7 +604,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -616,7 +624,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index d74926aee..262de0632 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:31 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -11,4 +11,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 24404000 because target called exit() +Exiting @ tick 24229500 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index b48213381..941a3afbf 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.000024 # Nu sim_ticks 24229500 # Number of ticks simulated final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38113 # Simulator instruction rate (inst/s) -host_op_rate 38111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72448291 # Simulator tick rate (ticks/s) -host_mem_usage 273720 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 46987 # Simulator instruction rate (inst/s) +host_op_rate 46985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89318295 # Simulator tick rate (ticks/s) +host_mem_usage 231368 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory system.physmem.bytes_read::total 62400 # Number of bytes read from this memory @@ -218,6 +220,7 @@ system.membus.reqLayer0.occupancy 1237000 # La system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 37.4 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 6676 # Number of BP lookups system.cpu.branchPred.condPredicted 3772 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect @@ -656,6 +659,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 312.493120 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.152585 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.152585 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 620 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 263 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.302734 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11364 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11364 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 4320 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4320 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4320 # number of demand (read+write) hits @@ -744,6 +753,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 120.164328 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009552 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.003667 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.013219 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 829 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 337 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 492 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025299 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -869,6 +884,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 214.018929 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.052251 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.052251 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 11365 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 11365 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 3448 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 3448 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits |