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authorSteve Reinhardt <stever@gmail.com>2013-09-28 15:25:17 -0400
committerSteve Reinhardt <stever@gmail.com>2013-09-28 15:25:17 -0400
commitfbc1feb39ac19379983ca714f4c7fadcd9fdabf6 (patch)
tree59e49142d5930eb044e9fc09d94c5060a810d545 /tests/quick/se/01.hello-2T-smt/ref
parente5c319db43751f45b2bcca1d018fc39d4561ef9c (diff)
downloadgem5-fbc1feb39ac19379983ca714f4c7fadcd9fdabf6.tar.xz
tests: update reference outputs
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
Diffstat (limited to 'tests/quick/se/01.hello-2T-smt/ref')
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini87
-rwxr-xr-xtests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout8
2 files changed, 69 insertions, 26 deletions
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 934dbc782..5d2204eb4 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
@@ -43,7 +49,7 @@ backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
+simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
-globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
-localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=2
@@ -133,10 +138,10 @@ predType=tournament
[system.cpu.dcache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
response_latency=2
size=262144
system=system
+tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
[system.cpu.dtb]
type=AlphaTLB
size=64
@@ -422,10 +436,10 @@ opLat=3
[system.cpu.icache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
response_latency=2
size=131072
system=system
+tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
[system.cpu.interrupts]
type=AlphaInterrupts
@@ -457,10 +480,10 @@ size=48
[system.cpu.l2cache]
type=BaseCache
+children=tags
addr_ranges=0:18446744073709551615
assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -471,16 +494,24 @@ prefetcher=Null
response_latency=20
size=2097152
system=system
+tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
[system.cpu.toL2Bus]
type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -499,7 +530,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -518,7 +549,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -529,10 +560,14 @@ simpoint=0
system=system
uid=100
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
[system.membus]
type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
header_cycles=1
system=system
use_default_range=false
@@ -543,19 +578,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleDRAM
activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
banks_per_rank=8
+burst_length=8
channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
in_addr_map=true
-lines_per_rowbuffer=32
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
tBURST=5000
tCL=13750
tRCD=13750
@@ -566,6 +606,9 @@ tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
-zero=false
port=system.membus.master[0]
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 6461709eb..32cdff876 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:13
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:38
+gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -13,4 +13,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
Hello world!
Hello world!
-Exiting @ tick 24422500 because target called exit()
+Exiting @ tick 24404000 because target called exit()