diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/quick/se/01.hello-2T-smt | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/quick/se/01.hello-2T-smt')
3 files changed, 225 insertions, 288 deletions
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5ef0030d0..14cc5821d 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload0 workload1 +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload0 workload1 BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=2 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index ab4ed6a09..4edc89b33 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 6ec84dd27..292756fa3 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000013 # Nu sim_ticks 13202000 # Number of ticks simulated final_tick 13202000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76140 # Simulator instruction rate (inst/s) -host_tick_rate 78688554 # Simulator tick rate (ticks/s) -host_mem_usage 208616 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 91406 # Simulator instruction rate (inst/s) +host_op_rate 91394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 94452628 # Simulator tick rate (ticks/s) +host_mem_usage 210624 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated +sim_ops 12773 # Number of ops (including micro ops) simulated system.physmem.bytes_read 62144 # Number of bytes read from this memory system.physmem.bytes_inst_read 39936 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -385,6 +387,7 @@ system.cpu.iew.wb_penalized_rate::0 0 # fr system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions +system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions system.cpu.commit.commitSquashedInsts 9596 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 953 # The number of times a branch was mispredicted @@ -405,9 +408,12 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 20176 # Number of insts commited each cycle -system.cpu.commit.count::0 6403 # Number of instructions committed -system.cpu.commit.count::1 6404 # Number of instructions committed -system.cpu.commit.count::total 12807 # Number of instructions committed +system.cpu.commit.committedInsts::0 6403 # Number of instructions committed +system.cpu.commit.committedInsts::1 6404 # Number of instructions committed +system.cpu.commit.committedInsts::total 12807 # Number of instructions committed +system.cpu.commit.committedOps::0 6403 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::1 6404 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::total 12807 # Number of ops (including micro ops) committed system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed @@ -442,6 +448,8 @@ system.cpu.timesIdled 233 # Nu system.cpu.idleCycles 6204 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6386 # Number of Instructions Simulated system.cpu.committedInsts::1 6387 # Number of Instructions Simulated +system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated system.cpu.cpi::0 4.134826 # CPI: Cycles Per Instruction system.cpu.cpi::1 4.134179 # CPI: Cycles Per Instruction @@ -463,36 +471,39 @@ system.cpu.icache.total_refs 3236 # To system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.169329 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 314.165301 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.153401 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 3236 # number of ReadReq hits -system.cpu.icache.demand_hits 3236 # number of demand (read+write) hits -system.cpu.icache.overall_hits 3236 # number of overall hits -system.cpu.icache.ReadReq_misses 855 # number of ReadReq misses -system.cpu.icache.demand_misses 855 # number of demand (read+write) misses -system.cpu.icache.overall_misses 855 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::0 30710500 # number of ReadReq miss cycles +system.cpu.icache.occ_blocks::cpu.inst 314.165301 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.153401 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.153401 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 3236 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3236 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3236 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3236 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3236 # number of overall hits +system.cpu.icache.overall_hits::total 3236 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855 # number of overall misses +system.cpu.icache.overall_misses::total 855 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30710500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 30710500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::0 30710500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30710500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 30710500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::0 30710500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30710500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 30710500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4091 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.208995 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.208995 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.208995 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 35918.713450 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35918.713450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 35918.713450 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35918.713450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 35918.713450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35918.713450 # average overall miss latency +system.cpu.icache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.208995 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.208995 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.208995 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35918.713450 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,63 +512,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::0 0 # number of writebacks -system.cpu.icache.writebacks::1 0 # number of writebacks -system.cpu.icache.writebacks::total 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::0 229 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 229 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::0 229 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 229 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::0 229 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 229 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::0 626 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::0 626 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::0 626 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::0 22267000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22267000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 22267000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::0 22267000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22267000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 22267000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::0 22267000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22267000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 22267000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.153019 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153019 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.153019 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153019 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.153019 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.153019 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35570.287540 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::0 35570.287540 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::0 35570.287540 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35570.287540 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements @@ -567,44 +545,49 @@ system.cpu.dcache.total_refs 4323 # To system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 12.458213 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 216.133399 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.052767 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 3303 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 1020 # number of WriteReq hits -system.cpu.dcache.demand_hits 4323 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 4323 # number of overall hits -system.cpu.dcache.ReadReq_misses 308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 710 # number of WriteReq misses -system.cpu.dcache.demand_misses 1018 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1018 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::0 11179500 # number of ReadReq miss cycles +system.cpu.dcache.occ_blocks::cpu.data 216.133399 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.052767 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.052767 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3303 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3303 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4323 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4323 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4323 # number of overall hits +system.cpu.dcache.overall_hits::total 4323 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 308 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 308 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 710 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 710 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1018 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1018 # number of overall misses +system.cpu.dcache.overall_misses::total 1018 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11179500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11179500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::0 24106500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24106500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 24106500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::0 35286000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35286000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 35286000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::0 35286000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35286000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 35286000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 3611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 5341 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 5341 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.085295 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.410405 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.190601 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.190601 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 36297.077922 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36297.077922 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33952.816901 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33952.816901 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 34662.082515 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34662.082515 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 34662.082515 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34662.082515 # average overall miss latency +system.cpu.dcache.ReadReq_accesses::cpu.data 3611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 5341 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5341 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5341 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5341 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085295 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.190601 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.190601 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36297.077922 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33952.816901 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34662.082515 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34662.082515 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,72 +596,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::0 0 # number of writebacks -system.cpu.dcache.writebacks::1 0 # number of writebacks -system.cpu.dcache.writebacks::total 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::0 107 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 107 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::0 564 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 564 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::0 671 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 671 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::0 671 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 671 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::0 201 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::0 347 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 347 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::0 347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::0 7376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7376000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 7376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::0 5298000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5298000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5298000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::0 12674000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12674000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 12674000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::0 12674000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12674000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12674000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.055663 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055663 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.064969 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064969 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.064969 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064969 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36696.517413 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36287.671233 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::0 36524.495677 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::0 36524.495677 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36696.517413 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36287.671233 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements @@ -688,43 +637,64 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 435.235373 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.013282 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 825 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 971 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 971 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::0 28470000 # number of ReadReq miss cycles +system.cpu.l2cache.occ_blocks::cpu.inst 314.499531 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 120.735842 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.009598 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003685 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.013282 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 201 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 825 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 347 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 971 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 347 # number of overall misses +system.cpu.l2cache.overall_misses::total 971 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21475000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6995000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 28470000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::0 5066000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5066000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5066000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::0 33536000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21475000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12061000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 33536000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::0 33536000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21475000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12061000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 33536000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 827 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 973 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 973 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997582 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997945 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997945 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::0 34509.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34509.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34698.630137 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34698.630137 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::0 34537.590113 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34537.590113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::0 34537.590113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34537.590113 # average overall miss latency +system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 827 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 973 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 973 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34415.064103 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34800.995025 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34698.630137 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -733,68 +703,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::0 0 # number of writebacks -system.cpu.l2cache.writebacks::1 0 # number of writebacks -system.cpu.l2cache.writebacks::total 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::0 825 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::0 971 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::0 971 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25887000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19514500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6372500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25887000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4614000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4614000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4614000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::0 30501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10986500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::0 30501000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19514500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10986500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997582 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997582 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::0 0.997945 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997945 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::0 0.997945 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997945 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31378.181818 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31602.739726 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31411.946447 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31411.946447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31273.237179 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31703.980100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31602.739726 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |