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authorAli Saidi <saidi@eecs.umich.edu>2012-06-05 01:23:16 -0400
committerAli Saidi <saidi@eecs.umich.edu>2012-06-05 01:23:16 -0400
commitc49e739352b6d6bd665c78c560602d0cff1e6a1a (patch)
tree5d32efd82f884376573604727d971a80458ed04a /tests/quick/se/01.hello-2T-smt
parente5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff)
downloadgem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/quick/se/01.hello-2T-smt')
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini6
-rwxr-xr-xtests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout6
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt81
3 files changed, 71 insertions, 22 deletions
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 60ac42ca2..01d2e4278 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@@ -526,9 +525,8 @@ system=system
uid=100
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index c897f1e4e..0e67a0bd3 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:36:31
-gem5 started May 8 2012 15:40:54
-gem5 executing on piton
+gem5 compiled Jun 4 2012 11:50:11
+gem5 started Jun 4 2012 14:39:51
+gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 244839beb..972719e56 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds 0.000014 # Nu
sim_ticks 13973500 # Number of ticks simulated
final_tick 13973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 43715 # Simulator instruction rate (inst/s)
-host_op_rate 43711 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47815570 # Simulator tick rate (ticks/s)
-host_mem_usage 215652 # Number of bytes of host memory used
-host_seconds 0.29 # Real time elapsed on the host
+host_inst_rate 68487 # Simulator instruction rate (inst/s)
+host_op_rate 68480 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 74908448 # Simulator tick rate (ticks/s)
+host_mem_usage 215960 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
sim_insts 12773 # Number of instructions simulated
sim_ops 12773 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 62784 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 40192 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 981 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 4493076180 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 2876301571 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 4493076180 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 40192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 22592 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62784 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 40192 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 40192 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 628 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 353 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 981 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2876301571 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1616774609 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4493076180 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2876301571 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2876301571 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2876301571 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1616774609 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4493076180 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -383,7 +390,7 @@ system.cpu.iew.wb_rate::1 0.345356 # in
system.cpu.iew.wb_rate::total 0.694969 # insts written-back per cycle
system.cpu.iew.wb_fanout::0 0.764981 # average fanout of values written-back
system.cpu.iew.wb_fanout::1 0.765796 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 1.530777 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.765387 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
@@ -500,11 +507,17 @@ system.cpu.icache.demand_accesses::total 5262 # nu
system.cpu.icache.overall_accesses::cpu.inst 5262 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5262 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169707 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.169707 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.169707 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.169707 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.169707 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.169707 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35538.633819 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35538.633819 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35538.633819 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35538.633819 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -532,11 +545,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 22442500
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22442500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 22442500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119916 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.119916 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.119916 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.561014 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35566.561014 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35566.561014 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35566.561014 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements::0 0 # number of replacements
system.cpu.dcache.replacements::1 0 # number of replacements
@@ -582,13 +601,21 @@ system.cpu.dcache.demand_accesses::total 5717 # nu
system.cpu.dcache.overall_accesses::cpu.data 5717 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 5717 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078004 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.078004 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.410405 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.178590 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.178590 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.178590 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.178590 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36080.385852 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36080.385852 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31737.323944 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31737.323944 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33060.235064 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 33060.235064 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -622,13 +649,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 12899000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12899000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12899000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051919 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051919 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.061746 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.061746 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36751.207729 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36751.207729 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36243.150685 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36243.150685 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36541.076487 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 36541.076487 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements::0 0 # number of replacements
system.cpu.l2cache.replacements::1 0 # number of replacements
@@ -684,18 +719,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 353
system.cpu.l2cache.overall_accesses::total 984 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995246 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.996420 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995246 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.996951 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995246 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.996951 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34452.229299 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34859.903382 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34553.293413 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34681.506849 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34681.506849 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34572.375127 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34572.375127 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
@@ -728,18 +771,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11181000
system.cpu.l2cache.overall_mshr_miss_latency::total 30840500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996420 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.996951 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.996951 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31304.936306 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31739.130435 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31412.574850 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.191781 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.191781 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31437.818552 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31437.818552 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------