diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:25:11 -0700 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:25:11 -0700 |
commit | 9d8fec0d90c2121a092c04da74e3306069ab5270 (patch) | |
tree | 2424ba161a3ea6e0b2787055169d7ec988bff64c /tests/quick/se/01.hello-2T-smt | |
parent | a04fac976f02377237bb827d46854b669ebc2397 (diff) | |
download | gem5-9d8fec0d90c2121a092c04da74e3306069ab5270.tar.xz |
stats: update stats for mmap() change.
SE O3 runs see an additional reg read per mmap() call.
Diffstat (limited to 'tests/quick/se/01.hello-2T-smt')
3 files changed, 14 insertions, 15 deletions
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini index 5c9532a74..13061b3ec 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini @@ -160,7 +160,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -509,7 +508,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -569,7 +567,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -604,6 +601,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -634,7 +632,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -657,7 +655,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -692,6 +690,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout index c20b17340..39d3a0691 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:00 -gem5 executing on zizzer, pid 33979 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt +gem5 compiled Mar 13 2016 22:43:13 +gem5 started Mar 13 2016 22:49:02 +gem5 executing on phenom, pid 19910 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index bbd43d33a..82bc89dfe 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 24832500 # Number of ticks simulated final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30698 # Simulator instruction rate (inst/s) -host_op_rate 30696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59808518 # Simulator tick rate (ticks/s) -host_mem_usage 233400 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host +host_inst_rate 23208 # Simulator instruction rate (inst/s) +host_op_rate 23207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45219113 # Simulator tick rate (ticks/s) +host_mem_usage 229684 # Number of bytes of host memory used +host_seconds 0.55 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -718,7 +718,7 @@ system.cpu.cpi_total 3.897207 # CP system.cpu.ipc::0 0.128297 # IPC: Instructions Per Cycle system.cpu.ipc::1 0.128297 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.256594 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 26491 # number of integer regfile reads +system.cpu.int_regfile_reads 26493 # number of integer regfile reads system.cpu.int_regfile_writes 14992 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes |