Stats: Update stats for cache timings in cycles

This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.

1 files changed, 7 insertions, 7 deletions

diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 2a32b08b0..c19d33801 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000015                       # Nu
 sim_ticks                                    14818500                       # Number of ticks simulated
 final_tick                                   14818500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71701                       # Simulator instruction rate (inst/s)
-host_op_rate                                    71694                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               83350191                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220256                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_inst_rate                                  95139                       # Simulator instruction rate (inst/s)
+host_op_rate                                    95123                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              110579898                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213740                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                       12745                       # Number of instructions simulated
 sim_ops                                         12745                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             40000                       # Number of bytes read from this memory
@@ -736,11 +736,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 40780.102041
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38918.400000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44057.746479                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 40780.102041                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs        49000                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs           98                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs               12                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  4083.333333                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     8.166667                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed