diff options
| author | Alec Roelke <ar4jc@virginia.edu> | 2017-07-13 18:00:50 -0400 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-14 20:31:05 +0000 |
| commit | cc076757e1471b1080df5c5a0130d96b9c35fb2f (patch) | |
| tree | e78ee49f33ffa977e9ad06f9346e2ae9adc0d395 /tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout | |
| parent | 68b6f9c8a1819fdeee737cf369cc6a499b505a6c (diff) | |
| download | gem5-cc076757e1471b1080df5c5a0130d96b9c35fb2f.tar.xz | |
tests: Upate RISC-V binaries and results
This patch updates the binaries and results for hello and insttest
regressions using the compressed extension.
Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e
Reviewed-on: https://gem5-review.googlesource.com/4042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout')
| -rwxr-xr-x | tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout | 48 |
1 files changed, 40 insertions, 8 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout index e65840d6c..f42d7d8e7 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout @@ -3,13 +3,45 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:31 -gem5 executing on zizzer, pid 34069 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:11:52 +gem5 executing on boldrock, pid 1958 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -lr.w/sc.w: [1;31mFAIL[0m (expected (-1, 0); found (-1, 1)) -Exiting @ tick 796036 because target called exit() +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 1861905 because exiting with last active thread context |