diff options
| author | Alec Roelke <ar4jc@virginia.edu> | 2017-07-13 18:00:50 -0400 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-14 20:31:05 +0000 |
| commit | cc076757e1471b1080df5c5a0130d96b9c35fb2f (patch) | |
| tree | e78ee49f33ffa977e9ad06f9346e2ae9adc0d395 /tests/quick/se/02.insttest/ref/riscv/linux-rv64a | |
| parent | 68b6f9c8a1819fdeee737cf369cc6a499b505a6c (diff) | |
| download | gem5-cc076757e1471b1080df5c5a0130d96b9c35fb2f.tar.xz | |
tests: Upate RISC-V binaries and results
This patch updates the binaries and results for hello and insttest
regressions using the compressed extension.
Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e
Reviewed-on: https://gem5-review.googlesource.com/4042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64a')
25 files changed, 5464 insertions, 2148 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini index ccd0e2b58..6578cac81 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini @@ -116,9 +116,11 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system threadPolicy=RoundRobin tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -745,7 +747,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -754,14 +756,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json index 3a39a409a..55918ca19 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json @@ -297,6 +297,7 @@ "max_loads_all_threads": 0, "executeMemoryIssueLimit": 1, "decodeCycleInput": true, + "syscallRetryLatency": 10000, "max_loads_any_thread": 0, "executeLSQTransfersQueueSize": 2, "p_state_clk_gate_max": 1000000000000, @@ -1058,21 +1059,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -1084,6 +1086,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr index 85a6a33ad..cec1d822a 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr @@ -1,4 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout index 842600b45..907424464 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:29 -gem5 executing on zizzer, pid 34061 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/minor-timing +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:12:00 +gem5 executing on boldrock, pid 2001 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/minor-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. lr.w/sc.w: PASS sc.w, no preceding lr.d: PASS amoswap.w: PASS @@ -46,4 +44,4 @@ amomin.d: PASS amomax.d: PASS amominu.d: PASS amomaxu.d: PASS -Exiting @ tick 167328500 because target called exit() +Exiting @ tick 179565500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt index 5aff2c58c..81fa91a62 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt @@ -1,769 +1,789 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000167 # Number of seconds simulated -sim_ticks 167318000 # Number of ticks simulated -final_tick 167318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 259842 # Simulator instruction rate (inst/s) -host_op_rate 259907 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 381385356 # Simulator tick rate (ticks/s) -host_mem_usage 261864 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host -sim_insts 113991 # Number of instructions simulated -sim_ops 114022 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory -system.physmem.bytes_read::total 69760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 52672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 52672 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 314801755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 102128880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 416930635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314801755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314801755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314801755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 102128880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 416930635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1090 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 69760 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 69760 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 110 # Per bank write bursts -system.physmem.perBankRdBursts::1 4 # Per bank write bursts -system.physmem.perBankRdBursts::2 9 # Per bank write bursts -system.physmem.perBankRdBursts::3 124 # Per bank write bursts -system.physmem.perBankRdBursts::4 62 # Per bank write bursts -system.physmem.perBankRdBursts::5 92 # Per bank write bursts -system.physmem.perBankRdBursts::6 88 # Per bank write bursts -system.physmem.perBankRdBursts::7 18 # Per bank write bursts -system.physmem.perBankRdBursts::8 55 # Per bank write bursts -system.physmem.perBankRdBursts::9 86 # Per bank write bursts -system.physmem.perBankRdBursts::10 90 # Per bank write bursts -system.physmem.perBankRdBursts::11 38 # Per bank write bursts -system.physmem.perBankRdBursts::12 113 # Per bank write bursts -system.physmem.perBankRdBursts::13 94 # Per bank write bursts -system.physmem.perBankRdBursts::14 101 # Per bank write bursts -system.physmem.perBankRdBursts::15 6 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 166987000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1090 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.729469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.587083 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 297.390992 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 56 27.05% 27.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 46 22.22% 49.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39 18.84% 68.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 16 7.73% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14 6.76% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7 3.38% 85.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation -system.physmem.totQLat 15449500 # Total ticks spent queuing -system.physmem.totMemAccLat 35887000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14173.85 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32923.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 416.93 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 416.93 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.26 # Data bus utilization in percentage -system.physmem.busUtilRead 3.26 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 874 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 153199.08 # Average gap between requests -system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9302400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 492960 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 55152630 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 7141920 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 92948520 # Total energy per rank (pJ) -system.physmem_0.averagePower 555.517657 # Core power per rank (mW) -system.physmem_0.totalIdleTime 145123750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states -system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 18593750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 120934750 # Time in different power states -system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 9796590 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 484800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 44771220 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 12438240 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 4464180 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 90201825 # Total energy per rank (pJ) -system.physmem_1.averagePower 539.101715 # Core power per rank (mW) -system.physmem_1.totalIdleTime 144258000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states -system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 13998250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 32388000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 98166000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 31578 # Number of BP lookups -system.cpu.branchPred.condPredicted 20002 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2179 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 27728 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15512 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.943451 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 5649 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3670 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1979 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 43 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 167318000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 334636 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 113991 # Number of instructions committed -system.cpu.committedOps 114022 # Number of ops (including micro ops) committed -system.cpu.discardedOps 5891 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.935635 # CPI: cycles per instruction -system.cpu.ipc 0.340642 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction -system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction -system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.68% # Class of committed instruction -system.cpu.op_class_0::MemRead 23779 20.85% 82.53% # Class of committed instruction -system.cpu.op_class_0::MemWrite 19915 17.47% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 114022 # Class of committed instruction -system.cpu.tickCycles 171594 # Number of cycles that the object actually ticked -system.cpu.idleCycles 163042 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 215.201598 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44063 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 164.414179 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 215.201598 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052539 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052539 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 89312 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 89312 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 24531 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 24531 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44057 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44057 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44057 # number of overall hits -system.cpu.dcache.overall_hits::total 44057 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 459 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses -system.cpu.dcache.overall_misses::total 459 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8632500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39369500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39369500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39369500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39369500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24606 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24606 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 44516 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 44516 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 44516 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 44516 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010311 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010311 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010311 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010311 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115100 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 115100 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85772.331155 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85772.331155 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 185 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 185 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 268 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23917000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23917000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23917000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23917000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009995 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115413.043478 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115413.043478 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80168.341709 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89242.537313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 89242.537313 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 18 # number of replacements -system.cpu.icache.tags.tagsinuse 401.741743 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 49660 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 60.340219 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 401.741743 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.196163 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.196163 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 101789 # Number of tag accesses -system.cpu.icache.tags.data_accesses 101789 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 49660 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49660 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49660 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49660 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49660 # number of overall hits -system.cpu.icache.overall_hits::total 49660 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses -system.cpu.icache.overall_misses::total 823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 69983000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 69983000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 69983000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 69983000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69983000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69983000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50483 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50483 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50483 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50483 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016303 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016303 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016303 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016303 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016303 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016303 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85034.021871 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 85034.021871 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 85034.021871 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 85034.021871 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 85034.021871 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 18 # number of writebacks -system.cpu.icache.writebacks::total 18 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 823 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69160000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69160000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69160000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016303 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016303 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016303 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84034.021871 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84034.021871 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 622.705265 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 19 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.947689 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 214.757576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012450 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006554 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.019003 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1090 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 199 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 199 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 823 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 823 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 68 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 68 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 823 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1090 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 823 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses -system.cpu.l2cache.overall_misses::total 1090 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67925500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 67925500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 67925500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 23501500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 91427000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 67925500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 23501500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 91427000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 823 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 823 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 69 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 69 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 823 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 268 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1091 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 823 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 268 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1091 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.985507 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.985507 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.996269 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.999083 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82534.021871 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82534.021871 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115404.411765 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115404.411765 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83877.981651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82534.021871 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83877.981651 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 823 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 823 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 68 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 68 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1090 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59695500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59695500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59695500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 80527000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59695500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 80527000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.985507 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.999083 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72534.021871 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72534.021871 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105404.411765 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105404.411765 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73877.981651 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 823 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 69 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1664 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 536 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2200 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 70976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1091 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000917 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.030275 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1090 99.91% 99.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.09% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1091 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 572500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1234500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 402000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1090 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 891 # Transaction distribution -system.membus.trans_dist::ReadExReq 199 # Transaction distribution -system.membus.trans_dist::ReadExResp 199 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 891 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2180 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2180 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 69760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 69760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1090 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1090 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1090 # Request fanout histogram -system.membus.reqLayer0.occupancy 1229000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.5 # Layer utilization (%) +sim_seconds 0.000180 +sim_ticks 179565500 +final_tick 179565500 +sim_freq 1000000000000 +host_inst_rate 6153 +host_op_rate 6167 +host_tick_rate 10087955 +host_mem_usage 272768 +host_seconds 17.80 +sim_insts 109528 +sim_ops 109773 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 179565500 +system.physmem.bytes_read::cpu.inst 61184 +system.physmem.bytes_read::cpu.data 29952 +system.physmem.bytes_read::total 91136 +system.physmem.bytes_inst_read::cpu.inst 61184 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+system.membus.trans_dist::ReadExResp 227 +system.membus.trans_dist::ReadSharedReq 1197 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2848 +system.membus.pkt_count::total 2848 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 91136 +system.membus.pkt_size::total 91136 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1424 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1424 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1424 +system.membus.reqLayer0.occupancy 1641000 +system.membus.reqLayer0.utilization 0.9 +system.membus.respLayer1.occupancy 7572000 +system.membus.respLayer1.utilization 4.2 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.ini new file mode 100644 index 000000000..8440890fa --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.ini @@ -0,0 +1,876 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=cout +pgid=100 +pid=100 +ppid=0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 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"eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList12", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCmp", + "opLat": 1, + "name": "opList13", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList13", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCvt", + "opLat": 1, + "name": "opList14", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList14", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatDiv", + "opLat": 1, + "name": "opList15", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList15", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMisc", + "opLat": 1, + "name": "opList16", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList16", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMult", + "opLat": 1, + "name": "opList17", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList17", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMultAcc", + "opLat": 1, + "name": "opList18", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList18", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatSqrt", + "opLat": 1, + "name": "opList19", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList19", + "type": "OpDesc" + } + ], + "name": "FUList5", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList5", + "type": "FUDesc" + }, + { + "count": 0, + "opList": [ + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList1", + "type": "OpDesc" + } + ], + "name": "FUList6", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList6", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList0", + "type": "OpDesc" + }, + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList3", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "wait_for_remote_gdb": false, + "cacheStorePorts": 200, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simerr new file mode 100755 index 000000000..cec1d822a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simerr @@ -0,0 +1,6 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Sockets disabled, not accepting gdb connections +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simout new file mode 100755 index 000000000..d5cbd1985 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simout @@ -0,0 +1,47 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:25:07 +gem5 executing on boldrock, pid 6011 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/o3-timing + +Global frequency set at 1000000000000 ticks per second +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 125677500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/stats.txt new file mode 100644 index 000000000..9d4cfea69 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/stats.txt @@ -0,0 +1,1044 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000126 +sim_ticks 125677500 +final_tick 125677500 +sim_freq 1000000000000 +host_inst_rate 4939 +host_op_rate 4950 +host_tick_rate 5669654 +host_mem_usage 272252 +host_seconds 22.17 +sim_insts 109485 +sim_ops 109730 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 125677500 +system.physmem.bytes_read::cpu.inst 55552 +system.physmem.bytes_read::cpu.data 30016 +system.physmem.bytes_read::total 85568 +system.physmem.bytes_inst_read::cpu.inst 55552 +system.physmem.bytes_inst_read::total 55552 +system.physmem.num_reads::cpu.inst 868 +system.physmem.num_reads::cpu.data 469 +system.physmem.num_reads::total 1337 +system.physmem.bw_read::cpu.inst 442020250 +system.physmem.bw_read::cpu.data 238833522 +system.physmem.bw_read::total 680853773 +system.physmem.bw_inst_read::cpu.inst 442020250 +system.physmem.bw_inst_read::total 442020250 +system.physmem.bw_total::cpu.inst 442020250 +system.physmem.bw_total::cpu.data 238833522 +system.physmem.bw_total::total 680853773 +system.physmem.readReqs 1337 +system.physmem.writeReqs 0 +system.physmem.readBursts 1337 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 85568 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 85568 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 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+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75021.889401 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75021.889401 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80438.247012 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80438.247012 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75021.889401 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78604.477612 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76278.608826 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75021.889401 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78604.477612 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76278.608826 +system.cpu.toL2Bus.snoop_filter.tot_requests 1417 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 125677500 +system.cpu.toL2Bus.trans_dist::ReadResp 1128 +system.cpu.toL2Bus.trans_dist::WritebackClean 70 +system.cpu.toL2Bus.trans_dist::ReadExReq 218 +system.cpu.toL2Bus.trans_dist::ReadExResp 218 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 878 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 251 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1825 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 938 +system.cpu.toL2Bus.pkt_count::total 2763 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60608 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30016 +system.cpu.toL2Bus.pkt_size::total 90624 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 1347 +system.cpu.toL2Bus.snoop_fanout::mean 0 +system.cpu.toL2Bus.snoop_fanout::stdev 0 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1347 100.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 0 +system.cpu.toL2Bus.snoop_fanout::total 1347 +system.cpu.toL2Bus.reqLayer0.occupancy 778500 +system.cpu.toL2Bus.reqLayer0.utilization 0.6 +system.cpu.toL2Bus.respLayer0.occupancy 1315500 +system.cpu.toL2Bus.respLayer0.utilization 1.0 +system.cpu.toL2Bus.respLayer1.occupancy 703500 +system.cpu.toL2Bus.respLayer1.utilization 0.6 +system.membus.snoop_filter.tot_requests 1337 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 125677500 +system.membus.trans_dist::ReadResp 1119 +system.membus.trans_dist::ReadExReq 218 +system.membus.trans_dist::ReadExResp 218 +system.membus.trans_dist::ReadSharedReq 1119 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2674 +system.membus.pkt_count::total 2674 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85568 +system.membus.pkt_size::total 85568 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1337 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1337 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1337 +system.membus.reqLayer0.occupancy 1642500 +system.membus.reqLayer0.utilization 1.3 +system.membus.respLayer1.occupancy 7097750 +system.membus.respLayer1.utilization 5.6 + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini index b4b1de997..553feeb96 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini @@ -88,8 +88,10 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false width=1 workload=system.cpu.workload dcache_port=system.membus.slave[2] @@ -118,7 +120,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -127,14 +129,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json index 3c887fa30..806f4a807 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json @@ -192,6 +192,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -216,21 +217,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -242,6 +244,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr index fd133b12b..780344c78 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr @@ -1,3 +1,5 @@ -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout index 04963ca82..1563c6cb6 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout @@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:29 -gem5 executing on zizzer, pid 34062 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:10:21 +gem5 executing on boldrock, pid 1519 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. lr.w/sc.w: PASS sc.w, no preceding lr.d: PASS amoswap.w: PASS @@ -46,4 +44,4 @@ amomin.d: PASS amomax.d: PASS amominu.d: PASS amomaxu.d: PASS -Exiting @ tick 57010500 because target called exit() +Exiting @ tick 68573500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt index 33126dd04..c2e3486d8 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt @@ -1,156 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000057 # Number of seconds simulated -sim_ticks 57010500 # Number of ticks simulated -final_tick 57010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83371 # Simulator instruction rate (inst/s) -host_op_rate 83392 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41711101 # Simulator tick rate (ticks/s) -host_mem_usage 233576 # Number of bytes of host memory used -host_seconds 1.37 # Real time elapsed on the host -sim_insts 113947 # Number of instructions simulated -sim_ops 113978 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 455964 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156854 # Number of bytes read from this memory -system.physmem.bytes_read::total 612818 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 455964 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 455964 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 111519 # Number of bytes written to this memory -system.physmem.bytes_written::total 111519 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 113991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 23779 # Number of read requests responded to by this memory -system.physmem.num_reads::total 137770 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 19912 # Number of write requests responded to by this memory -system.physmem.num_writes::total 19912 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7997895125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2751317740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10749212864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7997895125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7997895125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1956113348 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1956113348 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7997895125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4707431087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12705326212 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 43 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 57010500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 114022 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 113947 # Number of instructions committed -system.cpu.committedOps 113978 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 113979 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 8601 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 17313 # number of instructions that are conditional controls -system.cpu.num_int_insts 113979 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 152039 # number of times the integer registers were read -system.cpu.num_int_register_writes 76786 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 43694 # number of memory refs -system.cpu.num_load_insts 23779 # Number of load instructions -system.cpu.num_store_insts 19915 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 114022 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 25914 # Number of branches fetched -system.cpu.op_class::No_OpClass 43 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 70180 61.55% 61.59% # Class of executed instruction -system.cpu.op_class::IntMult 105 0.09% 61.68% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.68% # Class of executed instruction -system.cpu.op_class::MemRead 23779 20.85% 82.53% # Class of executed instruction -system.cpu.op_class::MemWrite 19915 17.47% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 114022 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 137768 # Transaction distribution -system.membus.trans_dist::ReadResp 137770 # Transaction distribution -system.membus.trans_dist::WriteReq 19910 # Transaction distribution -system.membus.trans_dist::WriteResp 19910 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 2 # Transaction distribution -system.membus.trans_dist::StoreCondReq 4 # Transaction distribution -system.membus.trans_dist::StoreCondResp 4 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 227982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 87386 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 315368 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 455964 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 268385 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 724349 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 157684 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 157684 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 157684 # Request fanout histogram +sim_seconds 0.000069 +sim_ticks 68573500 +final_tick 68573500 +sim_freq 1000000000000 +host_inst_rate 3619 +host_op_rate 3627 +host_tick_rate 2266534 +host_mem_usage 259192 +host_seconds 30.26 +sim_insts 109485 +sim_ops 109730 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 68573500 +system.physmem.bytes_read::cpu.inst 547612 +system.physmem.bytes_read::cpu.data 174025 +system.physmem.bytes_read::total 721637 +system.physmem.bytes_inst_read::cpu.inst 547612 +system.physmem.bytes_inst_read::total 547612 +system.physmem.bytes_written::cpu.data 113591 +system.physmem.bytes_written::total 113591 +system.physmem.num_reads::cpu.inst 136903 +system.physmem.num_reads::cpu.data 25597 +system.physmem.num_reads::total 162500 +system.physmem.num_writes::cpu.data 16677 +system.physmem.num_writes::total 16677 +system.physmem.bw_read::cpu.inst 7985767097 +system.physmem.bw_read::cpu.data 2537787921 +system.physmem.bw_read::total 10523555018 +system.physmem.bw_inst_read::cpu.inst 7985767097 +system.physmem.bw_inst_read::total 7985767097 +system.physmem.bw_write::cpu.data 1656485377 +system.physmem.bw_write::total 1656485377 +system.physmem.bw_total::cpu.inst 7985767097 +system.physmem.bw_total::cpu.data 4194273298 +system.physmem.bw_total::total 12180040395 +system.pwrStateResidencyTicks::UNDEFINED 68573500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 43 +system.cpu.pwrStateResidencyTicks::ON 68573500 +system.cpu.numCycles 137148 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 109485 +system.cpu.committedOps 109730 +system.cpu.num_int_alu_accesses 109164 +system.cpu.num_fp_alu_accesses 12 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 6221 +system.cpu.num_conditional_control_insts 18218 +system.cpu.num_int_insts 109164 +system.cpu.num_fp_insts 12 +system.cpu.num_vec_insts 0 +system.cpu.num_int_register_reads 137211 +system.cpu.num_int_register_writes 72083 +system.cpu.num_fp_register_reads 12 +system.cpu.num_fp_register_writes 0 +system.cpu.num_vec_register_reads 0 +system.cpu.num_vec_register_writes 0 +system.cpu.num_mem_refs 42276 +system.cpu.num_load_insts 25597 +system.cpu.num_store_insts 16679 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 137148 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 24439 +system.cpu.op_class::No_OpClass 47 0.04% 0.04% +system.cpu.op_class::IntAlu 67339 61.34% 61.39% +system.cpu.op_class::IntMult 107 0.10% 61.48% +system.cpu.op_class::IntDiv 4 0.00% 61.49% +system.cpu.op_class::FloatAdd 0 0.00% 61.49% +system.cpu.op_class::FloatCmp 0 0.00% 61.49% +system.cpu.op_class::FloatCvt 0 0.00% 61.49% +system.cpu.op_class::FloatMult 0 0.00% 61.49% +system.cpu.op_class::FloatMultAcc 0 0.00% 61.49% +system.cpu.op_class::FloatDiv 0 0.00% 61.49% +system.cpu.op_class::FloatMisc 0 0.00% 61.49% +system.cpu.op_class::FloatSqrt 0 0.00% 61.49% +system.cpu.op_class::SimdAdd 0 0.00% 61.49% +system.cpu.op_class::SimdAddAcc 0 0.00% 61.49% +system.cpu.op_class::SimdAlu 0 0.00% 61.49% +system.cpu.op_class::SimdCmp 0 0.00% 61.49% +system.cpu.op_class::SimdCvt 0 0.00% 61.49% +system.cpu.op_class::SimdMisc 0 0.00% 61.49% +system.cpu.op_class::SimdMult 0 0.00% 61.49% +system.cpu.op_class::SimdMultAcc 0 0.00% 61.49% +system.cpu.op_class::SimdShift 0 0.00% 61.49% +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.49% +system.cpu.op_class::SimdSqrt 0 0.00% 61.49% +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.49% +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.49% +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.49% +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.49% +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.49% +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.49% +system.cpu.op_class::SimdFloatMult 0 0.00% 61.49% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.49% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.49% +system.cpu.op_class::MemRead 25597 23.32% 84.81% +system.cpu.op_class::MemWrite 16667 15.18% 99.99% +system.cpu.op_class::FloatMemRead 0 0.00% 99.99% +system.cpu.op_class::FloatMemWrite 12 0.01% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 109773 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 68573500 +system.membus.trans_dist::ReadReq 162224 +system.membus.trans_dist::ReadResp 162500 +system.membus.trans_dist::WriteReq 16401 +system.membus.trans_dist::WriteResp 16401 +system.membus.trans_dist::LoadLockedReq 276 +system.membus.trans_dist::StoreCondReq 276 +system.membus.trans_dist::StoreCondResp 276 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 273806 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 84548 +system.membus.pkt_count::total 358354 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 547612 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 287616 +system.membus.pkt_size::total 835228 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 179177 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 179177 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 179177 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini index 237a0f0d7..140d3de80 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini @@ -85,8 +85,10 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] @@ -122,7 +124,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -131,14 +133,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -266,6 +269,7 @@ voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] type=Directory_Controller children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +addr_ranges=0:268435455:5:0:0:0 buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 @@ -288,16 +292,14 @@ responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory ruby_system=system.ruby system=system to_memory_controller_latency=1 -transitions_per_cycle=4 +transitions_per_cycle=32 version=0 memory=system.mem_ctrls.port [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +addr_ranges=0:268435455:5:0:0:0 eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] type=MessageBuffer @@ -349,6 +351,7 @@ randomization=false [system.ruby.l1_cntrl0] type=L1Cache_Controller children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +addr_ranges=0:18446744073709551615:0:0:0:0 buffer_size=0 cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json index 00786271a..f64c14c1e 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json @@ -115,7 +115,6 @@ "path": "system.ruby.l1_cntrl0.requestFromCache", "type": "MessageBuffer" }, - "cxx_class": "L1Cache_Controller", "forwardToCache": { "ordered": true, "name": "forwardToCache", @@ -168,8 +167,9 @@ "support_data_reqs": true, "is_cpu_sequencer": true }, - "type": "L1Cache_Controller", + "cxx_class": "L1Cache_Controller", "issue_latency": 2, + "type": "L1Cache_Controller", "recycle_latency": 10, "clk_domain": "system.cpu.clk_domain", "version": 0, @@ -241,6 +241,9 @@ }, "ruby_system": "system.ruby", "name": "l1_cntrl0", + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], "p_state_clk_gate_bins": 20, "mandatoryQueue": { "ordered": false, @@ -1447,12 +1450,15 @@ "path": "system.ruby.dir_cntrl0.responseFromDir", "type": "MessageBuffer" }, - "transitions_per_cycle": 4, + "transitions_per_cycle": 32, "memory": { "peer": "system.mem_ctrls.port", "role": "MASTER" }, "power_model": null, + "addr_ranges": [ + "0:268435455:5:0:0:0" + ], "buffer_size": 0, "ruby_system": "system.ruby", "requestToDir": { @@ -1487,13 +1493,13 @@ "p_state_clk_gate_bins": 20, "directory": { "name": "directory", - "version": 0, + "addr_ranges": [ + "0:268435455:5:0:0:0" + ], "eventq_index": 0, "cxx_class": "DirectoryMemory", "path": "system.ruby.dir_cntrl0.directory", - "type": "RubyDirectoryMemory", - "numa_high_bit": 5, - "size": 268435456 + "type": "RubyDirectoryMemory" }, "path": "system.ruby.dir_cntrl0" } @@ -1548,6 +1554,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -1572,21 +1579,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -1598,6 +1606,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr index 63b14556f..14f33408b 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr @@ -4,8 +4,12 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout index e65840d6c..f42d7d8e7 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout @@ -3,13 +3,45 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:31 -gem5 executing on zizzer, pid 34069 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:11:52 +gem5 executing on boldrock, pid 1958 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -lr.w/sc.w: [1;31mFAIL[0m (expected (-1, 0); found (-1, 1)) -Exiting @ tick 796036 because target called exit() +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 1861905 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt index 7b610f7aa..9d4660576 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt @@ -1,632 +1,658 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000796 # Number of seconds simulated -sim_ticks 796036 # Number of ticks simulated -final_tick 796036 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 163786 # Simulator instruction rate (inst/s) -host_op_rate 163781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1970174 # Simulator tick rate (ticks/s) -host_mem_usage 428500 # Number of bytes of host memory used -host_seconds 0.40 # Real time elapsed on the host -sim_insts 66173 # Number of instructions simulated -sim_ops 66173 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 899200 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 899200 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 898944 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 898944 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 14050 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 14050 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 14046 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 14046 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1129597154 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1129597154 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1129275560 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1129275560 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 2258872714 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 2258872714 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 14050 # Number of read requests accepted -system.mem_ctrls.writeReqs 14046 # Number of write requests accepted -system.mem_ctrls.readBursts 14050 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 14046 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 236096 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 663104 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 245056 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 899200 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 898944 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 10361 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 10190 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 171 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 11 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 5 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 94 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 190 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 318 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 159 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 59 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 94 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 356 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 241 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 240 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 629 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 494 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 606 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 22 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 175 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 12 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 4 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 95 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 197 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 332 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 163 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 63 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 96 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 353 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 243 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 245 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 639 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 514 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 676 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 22 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 795950 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 14050 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 14046 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 3689 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 25 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 31 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 198 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 236 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 240 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 247 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 253 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 253 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 240 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 236 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 236 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 236 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 235 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 235 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 235 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 235 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 235 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 235 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 1249 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 383.846277 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 248.755949 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 339.416055 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 261 20.90% 20.90% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 321 25.70% 46.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 184 14.73% 61.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 116 9.29% 70.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 64 5.12% 75.74% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 46 3.68% 79.42% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 41 3.28% 82.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 34 2.72% 85.43% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 182 14.57% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 1249 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 235 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.651064 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.555359 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 1.947371 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 16 6.81% 6.81% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 98 41.70% 48.51% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 97 41.28% 89.79% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 21 8.94% 98.72% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 2 0.85% 99.57% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 0.43% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 235 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 235 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.293617 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.273674 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.844136 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 208 88.51% 88.51% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 14 5.96% 94.47% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 11 4.68% 99.15% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 2 0.85% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 235 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 72649 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 142740 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 18445 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 19.69 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 38.69 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 296.59 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 307.85 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1129.60 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1129.28 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.72 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 2.32 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 2.41 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.57 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 2727 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 3536 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 73.92 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.70 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 28.33 # Average gap between requests -system.mem_ctrls.pageHitRate 83.01 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 3048780 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 1642200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 11503968 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 8694432 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 44868720.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 54752376 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 1331712 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 160437216 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 26780160 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 62430000 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 375489564 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 471.699225 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 672460 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 1456 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 19004 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 250921 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 69740 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 103079 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 351836 # Time in different power states -system.mem_ctrls_1.actEnergy 5911920 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 3183936 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 30639168 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 23285376 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 61464000.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 65872392 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 2049024 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 210691152 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 47203968 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 18571440 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 468872376 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 589.009010 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 646243 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 2396 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 26042 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 61274 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 122927 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 121355 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 462042 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 796036 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 796036 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 66173 # Number of instructions committed -system.cpu.committedOps 66173 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 5169 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls -system.cpu.num_int_insts 66174 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 89437 # number of times the integer registers were read -system.cpu.num_int_register_writes 43419 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 24255 # number of memory refs -system.cpu.num_load_insts 11810 # Number of load instructions -system.cpu.num_store_insts 12445 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 796036 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 15480 # Number of branches fetched -system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction -system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction -system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction -system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 66183 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 28096 # delay histogram for all message -system.ruby.delayHist | 28096 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 28096 # delay histogram for all message +sim_seconds 0.001862 +sim_ticks 1861905 +final_tick 1861905 +sim_freq 1000000000 +host_inst_rate 5985 +host_op_rate 5999 +host_tick_rate 101787 +host_mem_usage 438656 +host_seconds 18.29 +sim_insts 109485 +sim_ops 109730 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 1861905 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 1817984 +system.mem_ctrls.bytes_read::total 1817984 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 1817728 +system.mem_ctrls.bytes_written::total 1817728 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 28406 +system.mem_ctrls.num_reads::total 28406 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 28402 +system.mem_ctrls.num_writes::total 28402 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 976410719 +system.mem_ctrls.bw_read::total 976410719 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 976273226 +system.mem_ctrls.bw_write::total 976273226 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1952683945 +system.mem_ctrls.bw_total::total 1952683945 +system.mem_ctrls.readReqs 28406 +system.mem_ctrls.writeReqs 28402 +system.mem_ctrls.readBursts 28406 +system.mem_ctrls.writeBursts 28402 +system.mem_ctrls.bytesReadDRAM 806208 +system.mem_ctrls.bytesReadWrQ 1011776 +system.mem_ctrls.bytesWritten 849856 +system.mem_ctrls.bytesReadSys 1817984 +system.mem_ctrls.bytesWrittenSys 1817728 +system.mem_ctrls.servicedByWrQ 15809 +system.mem_ctrls.mergedWrBursts 15104 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 671 +system.mem_ctrls.perBankRdBursts::1 579 +system.mem_ctrls.perBankRdBursts::2 902 +system.mem_ctrls.perBankRdBursts::3 1167 +system.mem_ctrls.perBankRdBursts::4 32 +system.mem_ctrls.perBankRdBursts::5 145 +system.mem_ctrls.perBankRdBursts::6 221 +system.mem_ctrls.perBankRdBursts::7 259 +system.mem_ctrls.perBankRdBursts::8 413 +system.mem_ctrls.perBankRdBursts::9 1534 +system.mem_ctrls.perBankRdBursts::10 1398 +system.mem_ctrls.perBankRdBursts::11 1294 +system.mem_ctrls.perBankRdBursts::12 975 +system.mem_ctrls.perBankRdBursts::13 1767 +system.mem_ctrls.perBankRdBursts::14 1094 +system.mem_ctrls.perBankRdBursts::15 146 +system.mem_ctrls.perBankWrBursts::0 695 +system.mem_ctrls.perBankWrBursts::1 586 +system.mem_ctrls.perBankWrBursts::2 943 +system.mem_ctrls.perBankWrBursts::3 1227 +system.mem_ctrls.perBankWrBursts::4 34 +system.mem_ctrls.perBankWrBursts::5 139 +system.mem_ctrls.perBankWrBursts::6 221 +system.mem_ctrls.perBankWrBursts::7 263 +system.mem_ctrls.perBankWrBursts::8 437 +system.mem_ctrls.perBankWrBursts::9 1648 +system.mem_ctrls.perBankWrBursts::10 1420 +system.mem_ctrls.perBankWrBursts::11 1349 +system.mem_ctrls.perBankWrBursts::12 1033 +system.mem_ctrls.perBankWrBursts::13 2005 +system.mem_ctrls.perBankWrBursts::14 1131 +system.mem_ctrls.perBankWrBursts::15 148 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 1861819 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 28406 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 28402 +system.mem_ctrls.rdQLenPdf::0 12597 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 +system.mem_ctrls.rdQLenPdf::26 0 +system.mem_ctrls.rdQLenPdf::27 0 +system.mem_ctrls.rdQLenPdf::28 0 +system.mem_ctrls.rdQLenPdf::29 0 +system.mem_ctrls.rdQLenPdf::30 0 +system.mem_ctrls.rdQLenPdf::31 0 +system.mem_ctrls.wrQLenPdf::0 1 +system.mem_ctrls.wrQLenPdf::1 1 +system.mem_ctrls.wrQLenPdf::2 1 +system.mem_ctrls.wrQLenPdf::3 1 +system.mem_ctrls.wrQLenPdf::4 1 +system.mem_ctrls.wrQLenPdf::5 1 +system.mem_ctrls.wrQLenPdf::6 1 +system.mem_ctrls.wrQLenPdf::7 1 +system.mem_ctrls.wrQLenPdf::8 1 +system.mem_ctrls.wrQLenPdf::9 1 +system.mem_ctrls.wrQLenPdf::10 1 +system.mem_ctrls.wrQLenPdf::11 1 +system.mem_ctrls.wrQLenPdf::12 1 +system.mem_ctrls.wrQLenPdf::13 1 +system.mem_ctrls.wrQLenPdf::14 1 +system.mem_ctrls.wrQLenPdf::15 134 +system.mem_ctrls.wrQLenPdf::16 166 +system.mem_ctrls.wrQLenPdf::17 700 +system.mem_ctrls.wrQLenPdf::18 838 +system.mem_ctrls.wrQLenPdf::19 835 +system.mem_ctrls.wrQLenPdf::20 851 +system.mem_ctrls.wrQLenPdf::21 852 +system.mem_ctrls.wrQLenPdf::22 832 +system.mem_ctrls.wrQLenPdf::23 808 +system.mem_ctrls.wrQLenPdf::24 807 +system.mem_ctrls.wrQLenPdf::25 808 +system.mem_ctrls.wrQLenPdf::26 807 +system.mem_ctrls.wrQLenPdf::27 807 +system.mem_ctrls.wrQLenPdf::28 810 +system.mem_ctrls.wrQLenPdf::29 807 +system.mem_ctrls.wrQLenPdf::30 807 +system.mem_ctrls.wrQLenPdf::31 807 +system.mem_ctrls.wrQLenPdf::32 807 +system.mem_ctrls.wrQLenPdf::33 0 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+system.mem_ctrls.wrQLenPdf::63 0 +system.mem_ctrls.bytesPerActivate::samples 5510 +system.mem_ctrls.bytesPerActivate::mean 300.335390 +system.mem_ctrls.bytesPerActivate::gmean 201.215380 +system.mem_ctrls.bytesPerActivate::stdev 278.905306 +system.mem_ctrls.bytesPerActivate::0-127 1409 25.57% 25.57% +system.mem_ctrls.bytesPerActivate::128-255 1666 30.24% 55.81% +system.mem_ctrls.bytesPerActivate::256-383 813 14.75% 70.56% +system.mem_ctrls.bytesPerActivate::384-511 512 9.29% 79.85% +system.mem_ctrls.bytesPerActivate::512-639 300 5.44% 85.30% +system.mem_ctrls.bytesPerActivate::640-767 201 3.65% 88.95% +system.mem_ctrls.bytesPerActivate::768-895 160 2.90% 91.85% +system.mem_ctrls.bytesPerActivate::896-1023 122 2.21% 94.07% +system.mem_ctrls.bytesPerActivate::1024-1151 327 5.93% 100.00% +system.mem_ctrls.bytesPerActivate::total 5510 +system.mem_ctrls.rdPerTurnAround::samples 807 +system.mem_ctrls.rdPerTurnAround::mean 15.605948 +system.mem_ctrls.rdPerTurnAround::gmean 15.524374 +system.mem_ctrls.rdPerTurnAround::stdev 1.656887 +system.mem_ctrls.rdPerTurnAround::12-13 61 7.56% 7.56% +system.mem_ctrls.rdPerTurnAround::14-15 346 42.87% 50.43% +system.mem_ctrls.rdPerTurnAround::16-17 317 39.28% 89.71% +system.mem_ctrls.rdPerTurnAround::18-19 73 9.05% 98.76% +system.mem_ctrls.rdPerTurnAround::20-21 9 1.12% 99.88% +system.mem_ctrls.rdPerTurnAround::34-35 1 0.12% 100.00% +system.mem_ctrls.rdPerTurnAround::total 807 +system.mem_ctrls.wrPerTurnAround::samples 807 +system.mem_ctrls.wrPerTurnAround::mean 16.454771 +system.mem_ctrls.wrPerTurnAround::gmean 16.428737 +system.mem_ctrls.wrPerTurnAround::stdev 0.958247 +system.mem_ctrls.wrPerTurnAround::16 643 79.68% 79.68% +system.mem_ctrls.wrPerTurnAround::17 24 2.97% 82.65% +system.mem_ctrls.wrPerTurnAround::18 81 10.04% 92.69% +system.mem_ctrls.wrPerTurnAround::19 55 6.82% 99.50% +system.mem_ctrls.wrPerTurnAround::20 4 0.50% 100.00% +system.mem_ctrls.wrPerTurnAround::total 807 +system.mem_ctrls.totQLat 257668 +system.mem_ctrls.totMemAccLat 497011 +system.mem_ctrls.totBusLat 62985 +system.mem_ctrls.avgQLat 20.45 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 39.45 +system.mem_ctrls.avgRdBW 433.00 +system.mem_ctrls.avgWrBW 456.44 +system.mem_ctrls.avgRdBWSys 976.41 +system.mem_ctrls.avgWrBWSys 976.27 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 6.95 +system.mem_ctrls.busUtilRead 3.38 +system.mem_ctrls.busUtilWrite 3.57 +system.mem_ctrls.avgRdQLen 1.00 +system.mem_ctrls.avgWrQLen 25.86 +system.mem_ctrls.readRowHits 8474 +system.mem_ctrls.writeRowHits 11886 +system.mem_ctrls.readRowHitRate 67.27 +system.mem_ctrls.writeRowHitRate 89.38 +system.mem_ctrls.avgGap 32.77 +system.mem_ctrls.pageHitRate 78.63 +system.mem_ctrls_0.actEnergy 11281200 +system.mem_ctrls_0.preEnergy 6101256 +system.mem_ctrls_0.readEnergy 45421824 +system.mem_ctrls_0.writeEnergy 34310016 +system.mem_ctrls_0.refreshEnergy 140137920.000000 +system.mem_ctrls_0.actBackEnergy 182453352 +system.mem_ctrls_0.preBackEnergy 4306560 +system.mem_ctrls_0.actPowerDownEnergy 536540088 +system.mem_ctrls_0.prePowerDownEnergy 57647232 +system.mem_ctrls_0.selfRefreshEnergy 33031920 +system.mem_ctrls_0.totalEnergy 1051231368 +system.mem_ctrls_0.averagePower 564.599895 +system.mem_ctrls_0.totalIdleTime 1450536 +system.mem_ctrls_0.memoryStateTime::IDLE 4697 +system.mem_ctrls_0.memoryStateTime::REF 59316 +system.mem_ctrls_0.memoryStateTime::SREF 123827 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 150123 +system.mem_ctrls_0.memoryStateTime::ACT 347319 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 1176623 +system.mem_ctrls_1.actEnergy 28103040 +system.mem_ctrls_1.preEnergy 15189384 +system.mem_ctrls_1.readEnergy 98486304 +system.mem_ctrls_1.writeEnergy 76596192 +system.mem_ctrls_1.refreshEnergy 148128240.000000 +system.mem_ctrls_1.actBackEnergy 216813864 +system.mem_ctrls_1.preBackEnergy 3596928 +system.mem_ctrls_1.actPowerDownEnergy 575377152 +system.mem_ctrls_1.prePowerDownEnergy 36288768 +system.mem_ctrls_1.selfRefreshEnergy 7747200 +system.mem_ctrls_1.totalEnergy 1206327072 +system.mem_ctrls_1.averagePower 647.899368 +system.mem_ctrls_1.totalIdleTime 1376944 +system.mem_ctrls_1.memoryStateTime::IDLE 2584 +system.mem_ctrls_1.memoryStateTime::REF 62696 +system.mem_ctrls_1.memoryStateTime::SREF 20775 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 94502 +system.mem_ctrls_1.memoryStateTime::ACT 419556 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 1261792 +system.pwrStateResidencyTicks::UNDEFINED 1861905 +system.cpu.clk_domain.clock 1 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 43 +system.cpu.pwrStateResidencyTicks::ON 1861905 +system.cpu.numCycles 1861905 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 109485 +system.cpu.committedOps 109730 +system.cpu.num_int_alu_accesses 109164 +system.cpu.num_fp_alu_accesses 12 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 6221 +system.cpu.num_conditional_control_insts 18218 +system.cpu.num_int_insts 109164 +system.cpu.num_fp_insts 12 +system.cpu.num_vec_insts 0 +system.cpu.num_int_register_reads 137211 +system.cpu.num_int_register_writes 72083 +system.cpu.num_fp_register_reads 12 +system.cpu.num_fp_register_writes 0 +system.cpu.num_vec_register_reads 0 +system.cpu.num_vec_register_writes 0 +system.cpu.num_mem_refs 42276 +system.cpu.num_load_insts 25597 +system.cpu.num_store_insts 16679 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 1861905 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 24439 +system.cpu.op_class::No_OpClass 47 0.04% 0.04% +system.cpu.op_class::IntAlu 67339 61.34% 61.39% +system.cpu.op_class::IntMult 107 0.10% 61.48% +system.cpu.op_class::IntDiv 4 0.00% 61.49% +system.cpu.op_class::FloatAdd 0 0.00% 61.49% +system.cpu.op_class::FloatCmp 0 0.00% 61.49% +system.cpu.op_class::FloatCvt 0 0.00% 61.49% +system.cpu.op_class::FloatMult 0 0.00% 61.49% +system.cpu.op_class::FloatMultAcc 0 0.00% 61.49% +system.cpu.op_class::FloatDiv 0 0.00% 61.49% +system.cpu.op_class::FloatMisc 0 0.00% 61.49% +system.cpu.op_class::FloatSqrt 0 0.00% 61.49% +system.cpu.op_class::SimdAdd 0 0.00% 61.49% +system.cpu.op_class::SimdAddAcc 0 0.00% 61.49% +system.cpu.op_class::SimdAlu 0 0.00% 61.49% +system.cpu.op_class::SimdCmp 0 0.00% 61.49% +system.cpu.op_class::SimdCvt 0 0.00% 61.49% +system.cpu.op_class::SimdMisc 0 0.00% 61.49% +system.cpu.op_class::SimdMult 0 0.00% 61.49% +system.cpu.op_class::SimdMultAcc 0 0.00% 61.49% +system.cpu.op_class::SimdShift 0 0.00% 61.49% +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.49% +system.cpu.op_class::SimdSqrt 0 0.00% 61.49% +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.49% +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.49% +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.49% +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.49% +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.49% +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.49% +system.cpu.op_class::SimdFloatMult 0 0.00% 61.49% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.49% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.49% +system.cpu.op_class::MemRead 25597 23.32% 84.81% +system.cpu.op_class::MemWrite 16667 15.18% 99.99% +system.cpu.op_class::FloatMemRead 0 0.00% 99.99% +system.cpu.op_class::FloatMemWrite 12 0.01% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 109773 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 1861905 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 56808 +system.ruby.delayHist | 56808 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 56808 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 90437 +system.ruby.outstanding_req_hist_seqr::samples 179178 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 90437 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 90437 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 179178 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 179178 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 90436 -system.ruby.latency_hist_seqr::mean 7.802203 -system.ruby.latency_hist_seqr::gmean 1.774694 -system.ruby.latency_hist_seqr::stdev 20.056111 -system.ruby.latency_hist_seqr | 86872 96.06% 96.06% | 3313 3.66% 99.72% | 168 0.19% 99.91% | 27 0.03% 99.94% | 26 0.03% 99.97% | 19 0.02% 99.99% | 1 0.00% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 9 0.01% 100.00% -system.ruby.latency_hist_seqr::total 90436 +system.ruby.latency_hist_seqr::samples 179177 +system.ruby.latency_hist_seqr::mean 9.391429 +system.ruby.latency_hist_seqr::gmean 1.842545 +system.ruby.latency_hist_seqr::stdev 24.126992 +system.ruby.latency_hist_seqr | 167034 93.22% 93.22% | 11341 6.33% 99.55% | 523 0.29% 99.84% | 82 0.05% 99.89% | 110 0.06% 99.95% | 70 0.04% 99.99% | 5 0.00% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 10 0.01% 100.00% +system.ruby.latency_hist_seqr::total 179177 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 76386 +system.ruby.hit_latency_hist_seqr::samples 150771 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 76386 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 76386 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 150771 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 150771 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 14050 -system.ruby.miss_latency_hist_seqr::mean 44.783915 -system.ruby.miss_latency_hist_seqr::gmean 40.136483 -system.ruby.miss_latency_hist_seqr::stdev 31.144722 -system.ruby.miss_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00% -system.ruby.miss_latency_hist_seqr::total 14050 -system.ruby.Directory.incomplete_times_seqr 14049 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.017645 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999377 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.035295 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.715164 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.017650 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999913 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.035295 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999915 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 76386 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 14050 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 90436 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.017645 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.995586 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.113609 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.070590 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999992 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.017650 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999340 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.017645 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.996224 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.017650 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999442 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.105874 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.715264 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 8.823722 -system.ruby.network.routers0.msg_count.Control::2 14050 -system.ruby.network.routers0.msg_count.Data::2 14046 -system.ruby.network.routers0.msg_count.Response_Data::4 14050 -system.ruby.network.routers0.msg_count.Writeback_Control::3 14046 -system.ruby.network.routers0.msg_bytes.Control::2 112400 -system.ruby.network.routers0.msg_bytes.Data::2 1011312 -system.ruby.network.routers0.msg_bytes.Response_Data::4 1011600 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 112368 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.035295 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.715189 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.017645 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.998751 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.017650 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999824 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 8.823722 -system.ruby.network.routers1.msg_count.Control::2 14050 -system.ruby.network.routers1.msg_count.Data::2 14046 -system.ruby.network.routers1.msg_count.Response_Data::4 14050 -system.ruby.network.routers1.msg_count.Writeback_Control::3 14046 -system.ruby.network.routers1.msg_bytes.Control::2 112400 -system.ruby.network.routers1.msg_bytes.Data::2 1011312 -system.ruby.network.routers1.msg_bytes.Response_Data::4 1011600 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 112368 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.035295 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.715249 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.017645 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.998123 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.017650 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.999732 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.017645 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.996859 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.017650 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.999541 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.035295 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.715212 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.017645 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.997493 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.017650 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999638 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.035295 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.715232 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 8.823722 -system.ruby.network.routers2.msg_count.Control::2 14050 -system.ruby.network.routers2.msg_count.Data::2 14046 -system.ruby.network.routers2.msg_count.Response_Data::4 14050 -system.ruby.network.routers2.msg_count.Writeback_Control::3 14046 -system.ruby.network.routers2.msg_bytes.Control::2 112400 -system.ruby.network.routers2.msg_bytes.Data::2 1011312 -system.ruby.network.routers2.msg_bytes.Response_Data::4 1011600 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 112368 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 42150 -system.ruby.network.msg_count.Data 42138 -system.ruby.network.msg_count.Response_Data 42150 -system.ruby.network.msg_count.Writeback_Control 42138 -system.ruby.network.msg_byte.Control 337200 -system.ruby.network.msg_byte.Data 3033936 -system.ruby.network.msg_byte.Response_Data 3034800 -system.ruby.network.msg_byte.Writeback_Control 337104 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 8.824727 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 14050 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 14046 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 1011600 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 112368 -system.ruby.network.routers0.throttle1.link_utilization 8.822717 -system.ruby.network.routers0.throttle1.msg_count.Control::2 14050 -system.ruby.network.routers0.throttle1.msg_count.Data::2 14046 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 112400 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 1011312 -system.ruby.network.routers1.throttle0.link_utilization 8.822717 -system.ruby.network.routers1.throttle0.msg_count.Control::2 14050 -system.ruby.network.routers1.throttle0.msg_count.Data::2 14046 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 112400 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 1011312 -system.ruby.network.routers1.throttle1.link_utilization 8.824727 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 14050 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 14046 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 1011600 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 112368 -system.ruby.network.routers2.throttle0.link_utilization 8.824727 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 14050 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 14046 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 1011600 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 112368 -system.ruby.network.routers2.throttle1.link_utilization 8.822717 -system.ruby.network.routers2.throttle1.msg_count.Control::2 14050 -system.ruby.network.routers2.throttle1.msg_count.Data::2 14046 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 112400 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 1011312 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 14050 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 14050 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 14050 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 14046 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 14046 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 14046 # delay histogram for vnet_2 +system.ruby.miss_latency_hist_seqr::samples 28406 +system.ruby.miss_latency_hist_seqr::mean 53.930754 +system.ruby.miss_latency_hist_seqr::gmean 47.226043 +system.ruby.miss_latency_hist_seqr::stdev 36.253574 +system.ruby.miss_latency_hist_seqr | 16263 57.25% 57.25% | 11341 39.92% 97.18% | 523 1.84% 99.02% | 82 0.29% 99.31% | 110 0.39% 99.69% | 70 0.25% 99.94% | 5 0.02% 99.96% | 2 0.01% 99.96% | 0 0.00% 99.96% | 10 0.04% 100.00% +system.ruby.miss_latency_hist_seqr::total 28406 +system.ruby.Directory.incomplete_times_seqr 28405 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015254 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999852 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030511 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.755161 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015256 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999963 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030511 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999963 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 1861905 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 150771 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 28406 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 179177 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015254 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.998940 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096234 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061021 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999997 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015256 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999718 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 1861905 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 1861905 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015254 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999094 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015256 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999762 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.091528 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.755204 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 1861905 +system.ruby.network.routers0.percent_links_utilized 7.627672 +system.ruby.network.routers0.msg_count.Control::2 28406 +system.ruby.network.routers0.msg_count.Data::2 28402 +system.ruby.network.routers0.msg_count.Response_Data::4 28406 +system.ruby.network.routers0.msg_count.Writeback_Control::3 28402 +system.ruby.network.routers0.msg_bytes.Control::2 227248 +system.ruby.network.routers0.msg_bytes.Data::2 2044944 +system.ruby.network.routers0.msg_bytes.Response_Data::4 2045232 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 227216 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030511 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.755171 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015254 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999702 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015256 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999925 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 1861905 +system.ruby.network.routers1.percent_links_utilized 7.627672 +system.ruby.network.routers1.msg_count.Control::2 28406 +system.ruby.network.routers1.msg_count.Data::2 28402 +system.ruby.network.routers1.msg_count.Response_Data::4 28406 +system.ruby.network.routers1.msg_count.Writeback_Control::3 28402 +system.ruby.network.routers1.msg_bytes.Control::2 227248 +system.ruby.network.routers1.msg_bytes.Data::2 2044944 +system.ruby.network.routers1.msg_bytes.Response_Data::4 2045232 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 227216 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030511 +system.ruby.network.int_link_buffers02.avg_stall_time 7.755197 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015254 +system.ruby.network.int_link_buffers08.avg_stall_time 2.999552 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015256 +system.ruby.network.int_link_buffers09.avg_stall_time 2.999886 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015254 +system.ruby.network.int_link_buffers13.avg_stall_time 4.999248 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015256 +system.ruby.network.int_link_buffers14.avg_stall_time 4.999804 +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030511 +system.ruby.network.int_link_buffers17.avg_stall_time 9.755181 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015254 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999401 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015256 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999845 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030511 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.755190 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 1861905 +system.ruby.network.routers2.percent_links_utilized 7.627672 +system.ruby.network.routers2.msg_count.Control::2 28406 +system.ruby.network.routers2.msg_count.Data::2 28402 +system.ruby.network.routers2.msg_count.Response_Data::4 28406 +system.ruby.network.routers2.msg_count.Writeback_Control::3 28402 +system.ruby.network.routers2.msg_bytes.Control::2 227248 +system.ruby.network.routers2.msg_bytes.Data::2 2044944 +system.ruby.network.routers2.msg_bytes.Response_Data::4 2045232 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 227216 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 1861905 +system.ruby.network.msg_count.Control 85218 +system.ruby.network.msg_count.Data 85206 +system.ruby.network.msg_count.Response_Data 85218 +system.ruby.network.msg_count.Writeback_Control 85206 +system.ruby.network.msg_byte.Control 681744 +system.ruby.network.msg_byte.Data 6134832 +system.ruby.network.msg_byte.Response_Data 6135696 +system.ruby.network.msg_byte.Writeback_Control 681648 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 1861905 +system.ruby.network.routers0.throttle0.link_utilization 7.628101 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 28406 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 28402 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 2045232 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 227216 +system.ruby.network.routers0.throttle1.link_utilization 7.627242 +system.ruby.network.routers0.throttle1.msg_count.Control::2 28406 +system.ruby.network.routers0.throttle1.msg_count.Data::2 28402 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 227248 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 2044944 +system.ruby.network.routers1.throttle0.link_utilization 7.627242 +system.ruby.network.routers1.throttle0.msg_count.Control::2 28406 +system.ruby.network.routers1.throttle0.msg_count.Data::2 28402 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 227248 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 2044944 +system.ruby.network.routers1.throttle1.link_utilization 7.628101 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 28406 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 28402 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 2045232 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 227216 +system.ruby.network.routers2.throttle0.link_utilization 7.628101 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 28406 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 28402 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 2045232 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 227216 +system.ruby.network.routers2.throttle1.link_utilization 7.627242 +system.ruby.network.routers2.throttle1.msg_count.Control::2 28406 +system.ruby.network.routers2.throttle1.msg_count.Data::2 28402 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 227248 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 2044944 +system.ruby.delayVCHist.vnet_1::bucket_size 1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 +system.ruby.delayVCHist.vnet_1::samples 28406 +system.ruby.delayVCHist.vnet_1 | 28406 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 28406 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 28402 +system.ruby.delayVCHist.vnet_2 | 28402 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 28402 system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 11809 -system.ruby.LD.latency_hist_seqr::mean 15.856719 -system.ruby.LD.latency_hist_seqr::gmean 3.539899 -system.ruby.LD.latency_hist_seqr::stdev 26.045304 -system.ruby.LD.latency_hist_seqr | 10771 91.21% 91.21% | 977 8.27% 99.48% | 43 0.36% 99.85% | 9 0.08% 99.92% | 5 0.04% 99.97% | 2 0.02% 99.98% | 0 0.00% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% -system.ruby.LD.latency_hist_seqr::total 11809 +system.ruby.LD.latency_hist_seqr::samples 25321 +system.ruby.LD.latency_hist_seqr::mean 26.407172 +system.ruby.LD.latency_hist_seqr::gmean 6.534976 +system.ruby.LD.latency_hist_seqr::stdev 35.776224 +system.ruby.LD.latency_hist_seqr | 20331 80.29% 80.29% | 4640 18.32% 98.62% | 239 0.94% 99.56% | 35 0.14% 99.70% | 45 0.18% 99.88% | 25 0.10% 99.98% | 3 0.01% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 2 0.01% 100.00% +system.ruby.LD.latency_hist_seqr::total 25321 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 7768 +system.ruby.LD.hit_latency_hist_seqr::samples 12929 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7768 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 7768 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 12929 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 12929 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 4041 -system.ruby.LD.miss_latency_hist_seqr::mean 44.415739 -system.ruby.LD.miss_latency_hist_seqr::gmean 40.208159 -system.ruby.LD.miss_latency_hist_seqr::stdev 27.248261 -system.ruby.LD.miss_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 4041 +system.ruby.LD.miss_latency_hist_seqr::samples 12392 +system.ruby.LD.miss_latency_hist_seqr::mean 52.915349 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.325075 +system.ruby.LD.miss_latency_hist_seqr::stdev 35.201666 +system.ruby.LD.miss_latency_hist_seqr | 7402 59.73% 59.73% | 4640 37.44% 97.18% | 239 1.93% 99.10% | 35 0.28% 99.39% | 45 0.36% 99.75% | 25 0.20% 99.95% | 3 0.02% 99.98% | 1 0.01% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 12392 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 -system.ruby.ST.latency_hist_seqr::samples 12443 -system.ruby.ST.latency_hist_seqr::mean 11.799164 -system.ruby.ST.latency_hist_seqr::gmean 2.546410 -system.ruby.ST.latency_hist_seqr::stdev 25.562634 -system.ruby.ST.latency_hist_seqr | 11787 94.73% 94.73% | 602 4.84% 99.57% | 31 0.25% 99.82% | 7 0.06% 99.87% | 4 0.03% 99.90% | 7 0.06% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 5 0.04% 100.00% -system.ruby.ST.latency_hist_seqr::total 12443 +system.ruby.ST.latency_hist_seqr::samples 16401 +system.ruby.ST.latency_hist_seqr::mean 15.595269 +system.ruby.ST.latency_hist_seqr::gmean 3.522270 +system.ruby.ST.latency_hist_seqr::stdev 27.152428 +system.ruby.ST.latency_hist_seqr | 15183 92.57% 92.57% | 1128 6.88% 99.45% | 65 0.40% 99.85% | 4 0.02% 99.87% | 8 0.05% 99.92% | 8 0.05% 99.97% | 0 0.00% 99.97% | 1 0.01% 99.98% | 0 0.00% 99.98% | 4 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 16401 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 9259 +system.ruby.ST.hit_latency_hist_seqr::samples 10768 system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 9259 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 10768 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 10768 system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 -system.ruby.ST.miss_latency_hist_seqr::samples 3184 -system.ruby.ST.miss_latency_hist_seqr::mean 43.202889 -system.ruby.ST.miss_latency_hist_seqr::gmean 38.579676 -system.ruby.ST.miss_latency_hist_seqr::stdev 35.050159 -system.ruby.ST.miss_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 3184 +system.ruby.ST.miss_latency_hist_seqr::samples 5633 +system.ruby.ST.miss_latency_hist_seqr::mean 43.495473 +system.ruby.ST.miss_latency_hist_seqr::gmean 39.095323 +system.ruby.ST.miss_latency_hist_seqr::stdev 30.999863 +system.ruby.ST.miss_latency_hist_seqr | 4415 78.38% 78.38% | 1128 20.02% 98.40% | 65 1.15% 99.56% | 4 0.07% 99.63% | 8 0.14% 99.77% | 8 0.14% 99.91% | 0 0.00% 99.91% | 1 0.02% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 5633 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 66183 -system.ruby.IFETCH.latency_hist_seqr::mean 5.613677 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.466025 -system.ruby.IFETCH.latency_hist_seqr::stdev 16.923600 -system.ruby.IFETCH.latency_hist_seqr | 64313 97.17% 97.17% | 1734 2.62% 99.79% | 94 0.14% 99.94% | 11 0.02% 99.95% | 17 0.03% 99.98% | 10 0.02% 99.99% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 66183 +system.ruby.IFETCH.latency_hist_seqr::samples 136903 +system.ruby.IFETCH.latency_hist_seqr::mean 5.532983 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.352136 +system.ruby.IFETCH.latency_hist_seqr::stdev 19.063253 +system.ruby.IFETCH.latency_hist_seqr | 130971 95.67% 95.67% | 5570 4.07% 99.74% | 219 0.16% 99.90% | 43 0.03% 99.93% | 57 0.04% 99.97% | 37 0.03% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 4 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 136903 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 59358 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 126527 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 59358 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 59358 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 126527 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 126527 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 6825 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 45.739487 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 40.840935 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.340636 -system.ruby.IFETCH.miss_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 6825 -system.ruby.Load_Linked.latency_hist_seqr::bucket_size 1 -system.ruby.Load_Linked.latency_hist_seqr::max_bucket 9 -system.ruby.Load_Linked.latency_hist_seqr::samples 1 -system.ruby.Load_Linked.latency_hist_seqr::mean 1 -system.ruby.Load_Linked.latency_hist_seqr::gmean 1 -system.ruby.Load_Linked.latency_hist_seqr::stdev nan -system.ruby.Load_Linked.latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Load_Linked.latency_hist_seqr::total 1 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 10376 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 60.809079 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 53.543726 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.587150 +system.ruby.IFETCH.miss_latency_hist_seqr | 4444 42.83% 42.83% | 5570 53.68% 96.51% | 219 2.11% 98.62% | 43 0.41% 99.04% | 57 0.55% 99.59% | 37 0.36% 99.94% | 2 0.02% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 4 0.04% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 10376 +system.ruby.Load_Linked.latency_hist_seqr::bucket_size 8 +system.ruby.Load_Linked.latency_hist_seqr::max_bucket 79 +system.ruby.Load_Linked.latency_hist_seqr::samples 276 +system.ruby.Load_Linked.latency_hist_seqr::mean 1.942029 +system.ruby.Load_Linked.latency_hist_seqr::gmean 1.073385 +system.ruby.Load_Linked.latency_hist_seqr::stdev 7.322462 +system.ruby.Load_Linked.latency_hist_seqr | 271 98.19% 98.19% | 0 0.00% 98.19% | 0 0.00% 98.19% | 0 0.00% 98.19% | 2 0.72% 98.91% | 0 0.00% 98.91% | 0 0.00% 98.91% | 0 0.00% 98.91% | 3 1.09% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.latency_hist_seqr::total 276 system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1 system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9 -system.ruby.Load_Linked.hit_latency_hist_seqr::samples 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::samples 271 system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1 system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1 -system.ruby.Load_Linked.hit_latency_hist_seqr::stdev nan -system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Load_Linked.hit_latency_hist_seqr::total 1 +system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 271 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.hit_latency_hist_seqr::total 271 +system.ruby.Load_Linked.miss_latency_hist_seqr::bucket_size 8 +system.ruby.Load_Linked.miss_latency_hist_seqr::max_bucket 79 +system.ruby.Load_Linked.miss_latency_hist_seqr::samples 5 +system.ruby.Load_Linked.miss_latency_hist_seqr::mean 53 +system.ruby.Load_Linked.miss_latency_hist_seqr::gmean 49.854558 +system.ruby.Load_Linked.miss_latency_hist_seqr::stdev 19.170290 +system.ruby.Load_Linked.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 3 60.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.miss_latency_hist_seqr::total 5 +system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.latency_hist_seqr::samples 276 +system.ruby.Store_Conditional.latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 276 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.latency_hist_seqr::total 276 +system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 276 +system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 276 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.hit_latency_hist_seqr::total 276 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 14050 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 44.783915 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 40.136483 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.144722 -system.ruby.Directory.miss_mach_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 14050 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 28406 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.930754 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.226043 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.253574 +system.ruby.Directory.miss_mach_latency_hist_seqr | 16263 57.25% 57.25% | 11341 39.92% 97.18% | 523 1.84% 99.02% | 82 0.29% 99.31% | 110 0.39% 99.69% | 70 0.25% 99.94% | 5 0.02% 99.96% | 2 0.01% 99.96% | 0 0.00% 99.96% | 10 0.04% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 28406 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 @@ -655,51 +681,59 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 4041 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 44.415739 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 40.208159 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.248261 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 4041 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 12392 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.915349 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.325075 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.201666 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 7402 59.73% 59.73% | 4640 37.44% 97.18% | 239 1.93% 99.10% | 35 0.28% 99.39% | 45 0.36% 99.75% | 25 0.20% 99.95% | 3 0.02% 99.98% | 1 0.01% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 12392 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 3184 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.202889 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 38.579676 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.050159 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 3184 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 5633 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.495473 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 39.095323 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 30.999863 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 4415 78.38% 78.38% | 1128 20.02% 98.40% | 65 1.15% 99.56% | 4 0.07% 99.63% | 8 0.14% 99.77% | 8 0.14% 99.91% | 0 0.00% 99.91% | 1 0.02% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 5633 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 6825 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 45.739487 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 40.840935 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.340636 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 6825 -system.ruby.Directory_Controller.GETX 14050 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 14046 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 14050 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 14046 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 14050 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 14046 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 14050 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 14046 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 11809 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 66183 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 12444 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 14050 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 14046 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 14046 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 4041 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 6825 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 3184 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 7768 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 59358 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 9260 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 14046 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 14046 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 10866 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 3184 0.00% 0.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 10376 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 60.809079 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 53.543726 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.587150 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 4444 42.83% 42.83% | 5570 53.68% 96.51% | 219 2.11% 98.62% | 43 0.41% 99.04% | 57 0.55% 99.59% | 37 0.36% 99.94% | 2 0.02% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 4 0.04% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 10376 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 8 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 79 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 5 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 53 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 49.854558 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 19.170290 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 3 60.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 5 +system.ruby.Directory_Controller.GETX 28406 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 28402 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 28406 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 28402 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 28406 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 28402 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 28406 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 28402 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 25321 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 136903 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 16953 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 28406 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 28402 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 28402 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 12392 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 10376 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 5638 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 12929 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 126527 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 11315 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 28402 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 28402 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 22768 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 5638 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini index 6c2c774c6..a52fa6387 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini @@ -85,8 +85,10 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer +wait_for_remote_gdb=false workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -287,7 +289,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -296,14 +298,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json index 16fd9afa3..835feafef 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json @@ -292,6 +292,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -376,21 +377,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "insttest" @@ -402,6 +404,7 @@ } ], "name": "cpu", + "wait_for_remote_gdb": false, "dtb": { "name": "dtb", "eventq_index": 0, diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr index fd133b12b..780344c78 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr @@ -1,3 +1,5 @@ -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest' +info: Increasing stack size by one page. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout index baa378d02..f87cbcdf6 100755 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout @@ -3,13 +3,45 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6 gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:30 -gem5 executing on zizzer, pid 34063 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:09:50 +gem5 executing on boldrock, pid 1346 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -lr.w/sc.w: [1;31mFAIL[0m (expected (-1, 0); found (-1, 1)) -Exiting @ tick 138549500 because target called exit() +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 250490500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt index 61ce3fb1c..566fe7ef9 100644 --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt @@ -1,519 +1,549 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000139 # Number of seconds simulated -sim_ticks 138549500 # Number of ticks simulated -final_tick 138549500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 338688 # Simulator instruction rate (inst/s) -host_op_rate 338651 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 708977788 # Simulator tick rate (ticks/s) -host_mem_usage 242940 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -sim_insts 66173 # Number of instructions simulated -sim_ops 66173 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 33600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 16064 # Number of bytes read from this memory -system.physmem.bytes_read::total 49664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 33600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 33600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 525 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 251 # Number of read requests responded to by this memory -system.physmem.num_reads::total 776 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 242512604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 115944121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 358456725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 242512604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 242512604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 242512604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 115944121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 358456725 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 138549500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 277099 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 66173 # Number of instructions committed -system.cpu.committedOps 66173 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 5169 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls -system.cpu.num_int_insts 66174 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 89437 # number of times the integer registers were read -system.cpu.num_int_register_writes 43419 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 24255 # number of memory refs -system.cpu.num_load_insts 11810 # Number of load instructions -system.cpu.num_store_insts 12445 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 277099 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 15480 # Number of branches fetched -system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction -system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction -system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction -system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction -system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 66183 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 195.060322 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 24002 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 251 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 95.625498 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 195.060322 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.047622 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.047622 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 251 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.061279 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 48757 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 48757 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 11758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12243 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12243 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 24001 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 24001 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 24001 # number of overall hits -system.cpu.dcache.overall_hits::total 24001 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 200 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 200 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses -system.cpu.dcache.overall_misses::total 251 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3213000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3213000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12600000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12600000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15813000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15813000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15813000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15813000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 11809 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11809 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12443 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12443 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24252 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24252 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24252 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24252 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004319 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004319 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.016073 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.016073 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010350 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010350 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010350 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010350 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 200 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 200 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 251 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 251 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 251 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 251 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3162000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3162000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12400000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12400000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15562000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15562000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15562000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15562000 # number of overall MSHR miss cycles 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-system.cpu.icache.demand_avg_miss_latency::cpu.inst 63002.857143 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63002.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63002.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63002.857143 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10 # number of writebacks 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7064 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7064 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 200 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 200 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 525 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 525 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 51 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 51 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 525 # number of demand (read+write) misses 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overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.288660 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 200 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 200 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 525 # number of 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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12675500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 39189000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.904762 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.904762 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 786 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 200 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 200 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1060 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 502 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1562 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 50304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 776 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 776 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 403000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 787500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 376500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 776 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 576 # Transaction distribution -system.membus.trans_dist::ReadExReq 200 # Transaction distribution -system.membus.trans_dist::ReadExResp 200 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 576 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1552 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 49664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 49664 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 776 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 776 # Request fanout histogram -system.membus.reqLayer0.occupancy 777000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3880000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.8 # Layer utilization (%) +sim_seconds 0.000250 +sim_ticks 250490500 +final_tick 250490500 +sim_freq 1000000000000 +host_inst_rate 3805 +host_op_rate 3814 +host_tick_rate 8705712 +host_mem_usage 268924 +host_seconds 28.77 +sim_insts 109485 +sim_ops 109730 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 250490500 +system.physmem.bytes_read::cpu.inst 44032 +system.physmem.bytes_read::cpu.data 29568 +system.physmem.bytes_read::total 73600 +system.physmem.bytes_inst_read::cpu.inst 44032 +system.physmem.bytes_inst_read::total 44032 +system.physmem.num_reads::cpu.inst 688 +system.physmem.num_reads::cpu.data 462 +system.physmem.num_reads::total 1150 +system.physmem.bw_read::cpu.inst 175783114 +system.physmem.bw_read::cpu.data 118040405 +system.physmem.bw_read::total 293823518 +system.physmem.bw_inst_read::cpu.inst 175783114 +system.physmem.bw_inst_read::total 175783114 +system.physmem.bw_total::cpu.inst 175783114 +system.physmem.bw_total::cpu.data 118040405 +system.physmem.bw_total::total 293823518 +system.pwrStateResidencyTicks::UNDEFINED 250490500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 43 +system.cpu.pwrStateResidencyTicks::ON 250490500 +system.cpu.numCycles 500981 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 109485 +system.cpu.committedOps 109730 +system.cpu.num_int_alu_accesses 109164 +system.cpu.num_fp_alu_accesses 12 +system.cpu.num_vec_alu_accesses 0 +system.cpu.num_func_calls 6221 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61.49% +system.cpu.op_class::SimdFloatMult 0 0.00% 61.49% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.49% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.49% +system.cpu.op_class::MemRead 25597 23.32% 84.81% +system.cpu.op_class::MemWrite 16667 15.18% 99.99% +system.cpu.op_class::FloatMemRead 0 0.00% 99.99% +system.cpu.op_class::FloatMemWrite 12 0.01% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 109773 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250490500 +system.cpu.dcache.tags.replacements 0 +system.cpu.dcache.tags.tagsinuse 331.433935 +system.cpu.dcache.tags.total_refs 41812 +system.cpu.dcache.tags.sampled_refs 462 +system.cpu.dcache.tags.avg_refs 90.502165 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 331.433935 +system.cpu.dcache.tags.occ_percent::cpu.data 0.080916 +system.cpu.dcache.tags.occ_percent::total 0.080916 +system.cpu.dcache.tags.occ_task_id_blocks::1024 462 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 12 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 435 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.112793 +system.cpu.dcache.tags.tag_accesses 85010 +system.cpu.dcache.tags.data_accesses 85010 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250490500 +system.cpu.dcache.ReadReq_hits::cpu.data 25087 +system.cpu.dcache.ReadReq_hits::total 25087 +system.cpu.dcache.WriteReq_hits::cpu.data 16174 +system.cpu.dcache.WriteReq_hits::total 16174 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 275 +system.cpu.dcache.LoadLockedReq_hits::total 275 +system.cpu.dcache.StoreCondReq_hits::cpu.data 276 +system.cpu.dcache.StoreCondReq_hits::total 276 +system.cpu.dcache.demand_hits::cpu.data 41261 +system.cpu.dcache.demand_hits::total 41261 +system.cpu.dcache.overall_hits::cpu.data 41261 +system.cpu.dcache.overall_hits::total 41261 +system.cpu.dcache.ReadReq_misses::cpu.data 234 +system.cpu.dcache.ReadReq_misses::total 234 +system.cpu.dcache.WriteReq_misses::cpu.data 227 +system.cpu.dcache.WriteReq_misses::total 227 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 +system.cpu.dcache.LoadLockedReq_misses::total 1 +system.cpu.dcache.demand_misses::cpu.data 461 +system.cpu.dcache.demand_misses::total 461 +system.cpu.dcache.overall_misses::cpu.data 461 +system.cpu.dcache.overall_misses::total 461 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14742000 +system.cpu.dcache.ReadReq_miss_latency::total 14742000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14301000 +system.cpu.dcache.WriteReq_miss_latency::total 14301000 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63000 +system.cpu.dcache.LoadLockedReq_miss_latency::total 63000 +system.cpu.dcache.demand_miss_latency::cpu.data 29043000 +system.cpu.dcache.demand_miss_latency::total 29043000 +system.cpu.dcache.overall_miss_latency::cpu.data 29043000 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