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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-07-13 18:00:50 -0400 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-14 20:31:05 +0000 |
| commit | cc076757e1471b1080df5c5a0130d96b9c35fb2f (patch) | |
| tree | e78ee49f33ffa977e9ad06f9346e2ae9adc0d395 /tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simout | |
| parent | 68b6f9c8a1819fdeee737cf369cc6a499b505a6c (diff) | |
| download | gem5-cc076757e1471b1080df5c5a0130d96b9c35fb2f.tar.xz | |
tests: Upate RISC-V binaries and results
This patch updates the binaries and results for hello and insttest
regressions using the compressed extension.
Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e
Reviewed-on: https://gem5-review.googlesource.com/4042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simout')
| -rwxr-xr-x | tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simout | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simout new file mode 100755 index 000000000..5d778132a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simout @@ -0,0 +1,66 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 13 2017 17:09:45 +gem5 started Jul 13 2017 17:25:07 +gem5 executing on boldrock, pid 6007 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/o3-timing + +Global frequency set at 1000000000000 ticks per second +c.lwsp: PASS +c.ldsp: PASS +c.fldsp: PASS +c.swsp: PASS +c.sdsp: PASS +c.fsdsp: PASS +c.lw, positive: PASS +c.lw, negative: PASS +c.ld: PASS +c.fld: PASS +c.sw: PASS +c.sd: PASS +c.fsd: PASS +c.j: PASS +c.jr: PASS +c.jalr: PASS +c.beqz, zero: PASS +c.beqz, not zero: PASS +c.bnez, not zero: PASS +c.bnez, zero: PASS +c.li: PASS +c.li, sign extend: PASS +c.lui: PASS +c.addi: PASS +c.addiw: PASS +c.addiw, overflow: PASS +c.addiw, truncate: PASS +c.addi16sp: PASS +c.addi4spn: PASS +c.slli: PASS +c.slli, overflow: PASS +c.srli: PASS +c.srli, overflow: PASS +c.srli, -1: PASS +c.srai: PASS +c.srai, overflow: PASS +c.srai, -1: PASS +c.andi (0): PASS +c.andi (1): PASS +c.mv: PASS +c.add: PASS +c.and (0): PASS +c.and (-1): PASS +c.or (1): PASS +c.or (A): PASS +c.xor (1): PASS +c.xor (0): PASS +c.sub: PASS +c.addw: PASS +c.addw, overflow: PASS +c.addw, truncate: PASS +c.subw: PASS +c.subw, "overflow": PASS +c.subw, truncate: PASS +Exiting @ tick 141034000 because exiting with last active thread context |