diff options
| author | Jason Lowe-Power <jason@lowepower.com> | 2016-11-30 17:12:59 -0500 |
|---|---|---|
| committer | Jason Lowe-Power <jason@lowepower.com> | 2016-11-30 17:12:59 -0500 |
| commit | 752033140228c790e51954bd8ccd3728f4dd7e08 (patch) | |
| tree | 3e3858dd900fed04d38cd331feadc140bec2e530 /tests/quick/se/02.insttest/ref/riscv | |
| parent | 33683bd087c2009db588844e8fa89b454a5c3d77 (diff) | |
| download | gem5-752033140228c790e51954bd8ccd3728f4dd7e08.tar.xz | |
tests: Regression stats updated for recent patches
Diffstat (limited to 'tests/quick/se/02.insttest/ref/riscv')
110 files changed, 51337 insertions, 0 deletions
diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini new file mode 100644 index 000000000..ccd0e2b58 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json new file mode 100644 index 000000000..3a39a409a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "max_insts_any_thread": 0, + "do_statistics_insts": true, + "numThreads": 1, + "fetch1LineSnapWidth": 0, + "fetch1ToFetch2BackwardDelay": 1, + "fetch1FetchLimit": 1, + "executeIssueLimit": 2, + "system": "system", + "executeLSQMaxStoreBufferStoresPerCycle": 2, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "decodeInputWidth": 2, + "cxx_class": "MinorCPU", + "max_loads_all_threads": 0, + "executeMemoryIssueLimit": 1, + "decodeCycleInput": true, + "max_loads_any_thread": 0, + "executeLSQTransfersQueueSize": 2, + "p_state_clk_gate_max": 1000000000000, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "executeMemoryWidth": 0, + "default_p_state": "UNDEFINED", + "executeBranchDelay": 1, + "executeMemoryCommitLimit": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + 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"type": "MinorFU" + }, + { + "issueLat": 9, + "opLat": 9, + "name": "funcUnits3", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntDiv", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits3", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 6, + "name": "funcUnits4", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "FloatAdd", + "name": "opClasses00", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCmp", + "name": "opClasses01", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCvt", + "name": "opClasses02", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMisc", + "name": "opClasses03", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMult", + "name": "opClasses04", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMultAcc", + "name": "opClasses05", + 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"system.cpu.executeFuncUnits.funcUnits4.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "FloatSimd", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits4", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits5", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "MemRead", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "MemWrite", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemRead", + "name": "opClasses2", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemWrite", + "name": "opClasses3", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + 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+ "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout new file mode 100755 index 000000000..842600b45 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout @@ -0,0 +1,49 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:29 +gem5 executing on zizzer, pid 34061 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 167328500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt new file mode 100644 index 000000000..b23a2b88f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt @@ -0,0 +1,769 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000167 # Number of seconds simulated +sim_ticks 167328500 # Number of ticks simulated +final_tick 167328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 54302 # Simulator instruction rate (inst/s) +host_op_rate 54316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79708249 # Simulator tick rate (ticks/s) +host_mem_usage 244184 # Number of bytes of host memory used +host_seconds 2.10 # Real time elapsed on the host +sim_insts 113991 # Number of instructions simulated +sim_ops 114022 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory +system.physmem.bytes_read::total 69760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 52672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 52672 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 314782001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 102122472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 416904472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314782001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314782001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314782001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 102122472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 416904472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1090 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 69760 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 69760 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 110 # Per bank write bursts +system.physmem.perBankRdBursts::1 4 # Per bank write bursts +system.physmem.perBankRdBursts::2 9 # Per bank write bursts +system.physmem.perBankRdBursts::3 124 # Per bank write bursts +system.physmem.perBankRdBursts::4 62 # Per bank write bursts +system.physmem.perBankRdBursts::5 92 # Per bank write bursts +system.physmem.perBankRdBursts::6 88 # Per bank write bursts +system.physmem.perBankRdBursts::7 18 # Per bank write bursts +system.physmem.perBankRdBursts::8 55 # Per bank write bursts +system.physmem.perBankRdBursts::9 86 # Per bank write bursts +system.physmem.perBankRdBursts::10 90 # Per bank write bursts +system.physmem.perBankRdBursts::11 38 # Per bank write bursts +system.physmem.perBankRdBursts::12 113 # Per bank write bursts +system.physmem.perBankRdBursts::13 94 # Per bank write bursts +system.physmem.perBankRdBursts::14 101 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 166995000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1090 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.729469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.587083 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 297.390992 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 56 27.05% 27.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 46 22.22% 49.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39 18.84% 68.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 16 7.73% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14 6.76% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 3.38% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation +system.physmem.totQLat 15434500 # Total ticks spent queuing +system.physmem.totMemAccLat 35872000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14160.09 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32910.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 416.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 416.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.26 # Data bus utilization in percentage +system.physmem.busUtilRead 3.26 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 874 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 153206.42 # Average gap between requests +system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9305250 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 493440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 55143510 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 7150560 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 92951370 # Total energy per rank (pJ) +system.physmem_0.averagePower 555.501490 # Core power per rank (mW) +system.physmem_0.totalIdleTime 145131750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states +system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 18616750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 120922250 # Time in different power states +system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 9798300 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 485280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 44769510 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 12438720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 4465980 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 90204585 # Total energy per rank (pJ) +system.physmem_1.averagePower 539.085991 # Core power per rank (mW) +system.physmem_1.totalIdleTime 144266000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states +system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 14006250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 32390000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 98166500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 31621 # Number of BP lookups +system.cpu.branchPred.condPredicted 20020 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2186 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 28229 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15507 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 54.932870 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 5663 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3671 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1992 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 43 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 167328500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 334657 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113991 # Number of instructions committed +system.cpu.committedOps 114022 # Number of ops (including micro ops) committed +system.cpu.discardedOps 5904 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.935819 # CPI: cycles per instruction +system.cpu.ipc 0.340620 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction +system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction +system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::MemRead 23779 20.85% 82.53% # Class of committed instruction +system.cpu.op_class_0::MemWrite 19915 17.47% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 114022 # Class of committed instruction +system.cpu.tickCycles 171660 # Number of cycles that the object actually ticked +system.cpu.idleCycles 162997 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 215.204481 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44066 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 164.425373 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 215.204481 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052540 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052540 # Average 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(read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 823 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses +system.cpu.l2cache.overall_misses::total 1090 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67908500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 67908500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 67908500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 23501000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 91409500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 67908500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 23501000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 91409500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 823 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 823 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 69 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 69 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 823 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 268 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1091 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 823 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 268 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1091 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.985507 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.985507 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.996269 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.999083 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82513.365735 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82513.365735 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115397.058824 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115397.058824 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83861.926606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83861.926606 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 823 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 823 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 68 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 68 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1090 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59678500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59678500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59678500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 80509500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59678500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 80509500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.985507 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999083 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72513.365735 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72513.365735 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105397.058824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105397.058824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 69 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 536 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 70976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1091 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000917 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.030275 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1090 99.91% 99.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1091 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 572500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1234500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 402000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1090 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 891 # Transaction distribution +system.membus.trans_dist::ReadExReq 199 # Transaction distribution +system.membus.trans_dist::ReadExResp 199 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 891 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2180 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 69760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 69760 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1090 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1090 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1090 # Request fanout histogram +system.membus.reqLayer0.occupancy 1226500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini new file mode 100644 index 000000000..b4b1de997 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json new file mode 100644 index 000000000..3c887fa30 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout new file mode 100755 index 000000000..04963ca82 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout @@ -0,0 +1,49 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:29 +gem5 executing on zizzer, pid 34062 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 57010500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt new file mode 100644 index 000000000..07016a7d8 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt @@ -0,0 +1,156 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 57010500 # Number of ticks simulated +final_tick 57010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 83371 # Simulator instruction rate (inst/s) +host_op_rate 83392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41711101 # Simulator tick rate (ticks/s) +host_mem_usage 233576 # Number of bytes of host memory used +host_seconds 1.37 # Real time elapsed on the host +sim_insts 113947 # Number of instructions simulated +sim_ops 113978 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 455964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156854 # Number of bytes read from this memory +system.physmem.bytes_read::total 612818 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 455964 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 455964 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 111519 # Number of bytes written to this memory +system.physmem.bytes_written::total 111519 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 113991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 23779 # Number of read requests responded to by this memory +system.physmem.num_reads::total 137770 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 19912 # Number of write requests responded to by this memory +system.physmem.num_writes::total 19912 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7997895125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2751317740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10749212864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7997895125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7997895125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1956113348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1956113348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7997895125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4707431087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12705326212 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 43 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 57010500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 114022 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113947 # Number of instructions committed +system.cpu.committedOps 113978 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 113979 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8601 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17313 # number of instructions that are conditional controls +system.cpu.num_int_insts 113979 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 152039 # number of times the integer registers were read +system.cpu.num_int_register_writes 76786 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 43694 # number of memory refs +system.cpu.num_load_insts 23779 # Number of load instructions +system.cpu.num_store_insts 19915 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 114022 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25914 # Number of branches fetched +system.cpu.op_class::No_OpClass 43 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 70180 61.55% 61.59% # Class of executed instruction +system.cpu.op_class::IntMult 105 0.09% 61.68% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::MemRead 23779 20.85% 82.53% # Class of executed instruction +system.cpu.op_class::MemWrite 19915 17.47% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 114022 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 137768 # Transaction distribution +system.membus.trans_dist::ReadResp 137770 # Transaction distribution +system.membus.trans_dist::WriteReq 19910 # Transaction distribution +system.membus.trans_dist::WriteResp 19910 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 2 # Transaction distribution +system.membus.trans_dist::StoreCondReq 4 # Transaction distribution +system.membus.trans_dist::StoreCondResp 4 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 227982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 87386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 315368 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 455964 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 268385 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 724349 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 157684 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 157684 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 157684 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini new file mode 100644 index 000000000..237a0f0d7 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + 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+eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 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+p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json new file mode 100644 index 000000000..00786271a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": "SLAVE" + }, + "name": "sys_port_proxy", + "p_state_clk_gate_min": 1, + "no_retry_on_stall": false, + "p_state_clk_gate_bins": 20, + "support_data_reqs": true, + "cxx_class": "RubyPortProxy", + "clk_domain": "system.clk_domain", + "power_model": null, + "is_cpu_sequencer": true, + "version": 0, + "eventq_index": 0, + "using_ruby_tester": false, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.sys_port_proxy", + "type": "RubyPortProxy", + "ruby_system": "system.ruby" + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "ruby": { + "all_instructions": false, + "memory_size_bits": 48, + "cxx_class": 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"MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout new file mode 100755 index 000000000..e65840d6c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:31 +gem5 executing on zizzer, pid 34069 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: [1;31mFAIL[0m (expected (-1, 0); found (-1, 1)) +Exiting @ tick 796036 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..8b3036b08 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt @@ -0,0 +1,659 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000796 # Number of seconds simulated +sim_ticks 796036 # Number of ticks simulated +final_tick 796036 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 51863 # Simulator instruction rate (inst/s) +host_op_rate 51862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 623875 # Simulator tick rate (ticks/s) +host_mem_usage 411084 # Number of bytes of host memory used +host_seconds 1.28 # Real time elapsed on the host +sim_insts 66173 # Number of instructions simulated +sim_ops 66173 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 899200 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 899200 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 898944 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 898944 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 14050 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 14050 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 14046 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 14046 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1129597154 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1129597154 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1129275560 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1129275560 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2258872714 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2258872714 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 14050 # Number of read requests accepted +system.mem_ctrls.writeReqs 14046 # Number of write requests accepted +system.mem_ctrls.readBursts 14050 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 14046 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 236096 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 663104 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 245056 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 899200 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 898944 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 10361 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 10190 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 171 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 11 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 5 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 94 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 190 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 318 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 159 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 59 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 94 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 356 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 241 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 240 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 629 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 494 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 606 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 22 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 175 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 12 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 4 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 95 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 197 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 332 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 163 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 63 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 96 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 353 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 243 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 245 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 639 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 514 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 676 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 22 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 795950 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 14050 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 14046 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 3689 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 25 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 31 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 198 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 240 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 247 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 253 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 253 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 240 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1249 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 383.846277 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 248.755949 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 339.416055 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 261 20.90% 20.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 321 25.70% 46.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 184 14.73% 61.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 116 9.29% 70.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 64 5.12% 75.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 46 3.68% 79.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 41 3.28% 82.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 34 2.72% 85.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 182 14.57% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1249 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 235 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.651064 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.555359 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.947371 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 16 6.81% 6.81% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 98 41.70% 48.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 97 41.28% 89.79% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 21 8.94% 98.72% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 2 0.85% 99.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.43% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 235 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 235 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.293617 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.273674 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.844136 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 208 88.51% 88.51% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 14 5.96% 94.47% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 11 4.68% 99.15% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 2 0.85% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 235 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 72649 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 142740 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 18445 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 19.69 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 38.69 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 296.59 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 307.85 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1129.60 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1129.28 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.72 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.32 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 2.41 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.57 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 2727 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 3536 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 73.92 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.70 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 28.33 # Average gap between requests +system.mem_ctrls.pageHitRate 83.01 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 3048780 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1642200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 11503968 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 8694432 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 44868720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 54752376 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1331712 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 160437216 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 26780160 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 62430000 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 375489564 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 471.699225 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 672460 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 1456 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 19004 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 250921 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 69740 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 103079 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 351836 # Time in different power states +system.mem_ctrls_1.actEnergy 5911920 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 3183936 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 30639168 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 23285376 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 61464000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 65872392 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2049024 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 210691152 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 47203968 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 18571440 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 468872376 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 589.009010 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 646243 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 2396 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 26042 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 61274 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 122927 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 121355 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 462042 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 796036 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 796036 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 66173 # Number of instructions committed +system.cpu.committedOps 66173 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 5169 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls +system.cpu.num_int_insts 66174 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 89437 # number of times the integer registers were read +system.cpu.num_int_register_writes 43419 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 24255 # number of memory refs +system.cpu.num_load_insts 11810 # Number of load instructions +system.cpu.num_store_insts 12445 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 796036 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 15480 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction +system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction +system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction +system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 66183 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 28096 # delay histogram for all message +system.ruby.delayHist | 28096 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 28096 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 90437 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 90437 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 90437 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 90436 +system.ruby.latency_hist_seqr::mean 7.802203 +system.ruby.latency_hist_seqr::gmean 1.774694 +system.ruby.latency_hist_seqr::stdev 20.056111 +system.ruby.latency_hist_seqr | 86872 96.06% 96.06% | 3313 3.66% 99.72% | 168 0.19% 99.91% | 27 0.03% 99.94% | 26 0.03% 99.97% | 19 0.02% 99.99% | 1 0.00% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 9 0.01% 100.00% +system.ruby.latency_hist_seqr::total 90436 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 76386 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 76386 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 76386 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 14050 +system.ruby.miss_latency_hist_seqr::mean 44.783915 +system.ruby.miss_latency_hist_seqr::gmean 40.136483 +system.ruby.miss_latency_hist_seqr::stdev 31.144722 +system.ruby.miss_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00% +system.ruby.miss_latency_hist_seqr::total 14050 +system.ruby.Directory.incomplete_times_seqr 14049 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 76386 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 14050 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 90436 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 8.823722 +system.ruby.network.routers0.msg_count.Control::2 14050 +system.ruby.network.routers0.msg_count.Data::2 14046 +system.ruby.network.routers0.msg_count.Response_Data::4 14050 +system.ruby.network.routers0.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers0.msg_bytes.Control::2 112400 +system.ruby.network.routers0.msg_bytes.Data::2 1011312 +system.ruby.network.routers0.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 8.823722 +system.ruby.network.routers1.msg_count.Control::2 14050 +system.ruby.network.routers1.msg_count.Data::2 14046 +system.ruby.network.routers1.msg_count.Response_Data::4 14050 +system.ruby.network.routers1.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers1.msg_bytes.Control::2 112400 +system.ruby.network.routers1.msg_bytes.Data::2 1011312 +system.ruby.network.routers1.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 8.823722 +system.ruby.network.routers2.msg_count.Control::2 14050 +system.ruby.network.routers2.msg_count.Data::2 14046 +system.ruby.network.routers2.msg_count.Response_Data::4 14050 +system.ruby.network.routers2.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers2.msg_bytes.Control::2 112400 +system.ruby.network.routers2.msg_bytes.Data::2 1011312 +system.ruby.network.routers2.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 42150 +system.ruby.network.msg_count.Data 42138 +system.ruby.network.msg_count.Response_Data 42150 +system.ruby.network.msg_count.Writeback_Control 42138 +system.ruby.network.msg_byte.Control 337200 +system.ruby.network.msg_byte.Data 3033936 +system.ruby.network.msg_byte.Response_Data 3034800 +system.ruby.network.msg_byte.Writeback_Control 337104 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 8.824727 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 14050 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers0.throttle1.link_utilization 8.822717 +system.ruby.network.routers0.throttle1.msg_count.Control::2 14050 +system.ruby.network.routers0.throttle1.msg_count.Data::2 14046 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 112400 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 1011312 +system.ruby.network.routers1.throttle0.link_utilization 8.822717 +system.ruby.network.routers1.throttle0.msg_count.Control::2 14050 +system.ruby.network.routers1.throttle0.msg_count.Data::2 14046 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 112400 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 1011312 +system.ruby.network.routers1.throttle1.link_utilization 8.824727 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 14050 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers2.throttle0.link_utilization 8.824727 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 14050 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers2.throttle1.link_utilization 8.822717 +system.ruby.network.routers2.throttle1.msg_count.Control::2 14050 +system.ruby.network.routers2.throttle1.msg_count.Data::2 14046 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 112400 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 1011312 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 14050 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 14050 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 14050 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 14046 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 14046 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 14046 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 11809 +system.ruby.LD.latency_hist_seqr::mean 15.856719 +system.ruby.LD.latency_hist_seqr::gmean 3.539899 +system.ruby.LD.latency_hist_seqr::stdev 26.045304 +system.ruby.LD.latency_hist_seqr | 10771 91.21% 91.21% | 977 8.27% 99.48% | 43 0.36% 99.85% | 9 0.08% 99.92% | 5 0.04% 99.97% | 2 0.02% 99.98% | 0 0.00% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% +system.ruby.LD.latency_hist_seqr::total 11809 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 7768 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7768 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 7768 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 4041 +system.ruby.LD.miss_latency_hist_seqr::mean 44.415739 +system.ruby.LD.miss_latency_hist_seqr::gmean 40.208159 +system.ruby.LD.miss_latency_hist_seqr::stdev 27.248261 +system.ruby.LD.miss_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 4041 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 12443 +system.ruby.ST.latency_hist_seqr::mean 11.799164 +system.ruby.ST.latency_hist_seqr::gmean 2.546410 +system.ruby.ST.latency_hist_seqr::stdev 25.562634 +system.ruby.ST.latency_hist_seqr | 11787 94.73% 94.73% | 602 4.84% 99.57% | 31 0.25% 99.82% | 7 0.06% 99.87% | 4 0.03% 99.90% | 7 0.06% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 5 0.04% 100.00% +system.ruby.ST.latency_hist_seqr::total 12443 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 9259 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 9259 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 3184 +system.ruby.ST.miss_latency_hist_seqr::mean 43.202889 +system.ruby.ST.miss_latency_hist_seqr::gmean 38.579676 +system.ruby.ST.miss_latency_hist_seqr::stdev 35.050159 +system.ruby.ST.miss_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 3184 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 66183 +system.ruby.IFETCH.latency_hist_seqr::mean 5.613677 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.466025 +system.ruby.IFETCH.latency_hist_seqr::stdev 16.923600 +system.ruby.IFETCH.latency_hist_seqr | 64313 97.17% 97.17% | 1734 2.62% 99.79% | 94 0.14% 99.94% | 11 0.02% 99.95% | 17 0.03% 99.98% | 10 0.02% 99.99% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 66183 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 59358 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 59358 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 59358 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 6825 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 45.739487 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 40.840935 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.340636 +system.ruby.IFETCH.miss_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 6825 +system.ruby.Load_Linked.latency_hist_seqr::bucket_size 1 +system.ruby.Load_Linked.latency_hist_seqr::max_bucket 9 +system.ruby.Load_Linked.latency_hist_seqr::samples 1 +system.ruby.Load_Linked.latency_hist_seqr::mean 1 +system.ruby.Load_Linked.latency_hist_seqr::gmean 1 +system.ruby.Load_Linked.latency_hist_seqr::stdev nan +system.ruby.Load_Linked.latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.latency_hist_seqr::total 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Load_Linked.hit_latency_hist_seqr::samples 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::stdev nan +system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.hit_latency_hist_seqr::total 1 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 14050 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 44.783915 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 40.136483 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.144722 +system.ruby.Directory.miss_mach_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 14050 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 4041 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 44.415739 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 40.208159 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.248261 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 4041 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 3184 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.202889 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 38.579676 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.050159 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 3184 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 6825 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 45.739487 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 40.840935 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.340636 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 6825 +system.ruby.Directory_Controller.GETX 14050 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 14046 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 14050 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 14046 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 14050 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 14046 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 14050 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 14046 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 11809 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 66183 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 12444 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 14050 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 14046 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 14046 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 4041 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 6825 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 3184 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 7768 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 59358 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 9260 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 14046 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 14046 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 10866 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 3184 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini new file mode 100644 index 000000000..6c2c774c6 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json new file mode 100644 index 000000000..16fd9afa3 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout new file mode 100755 index 000000000..baa378d02 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:30 +gem5 executing on zizzer, pid 34063 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: [1;31mFAIL[0m (expected (-1, 0); found (-1, 1)) +Exiting @ tick 138549500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt new file mode 100644 index 000000000..918afc87c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt @@ -0,0 +1,519 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000139 # Number of seconds simulated +sim_ticks 138549500 # Number of ticks simulated +final_tick 138549500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 338688 # Simulator instruction rate (inst/s) +host_op_rate 338651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 708977788 # Simulator tick rate (ticks/s) +host_mem_usage 242940 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +sim_insts 66173 # Number of instructions simulated +sim_ops 66173 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 33600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16064 # Number of bytes read from this memory +system.physmem.bytes_read::total 49664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 33600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 33600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 251 # Number of read requests responded to by this memory +system.physmem.num_reads::total 776 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 242512604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 115944121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 358456725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 242512604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 242512604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 242512604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 115944121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 358456725 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 138549500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 277099 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 66173 # Number of instructions committed +system.cpu.committedOps 66173 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 5169 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls +system.cpu.num_int_insts 66174 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 89437 # number of times the integer registers were read +system.cpu.num_int_register_writes 43419 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 24255 # number of memory refs +system.cpu.num_load_insts 11810 # Number of load instructions +system.cpu.num_store_insts 12445 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 277099 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 15480 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction +system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction +system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction +system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 66183 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 195.060322 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 24002 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 251 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 95.625498 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 195.060322 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.047622 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.047622 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 251 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.061279 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 48757 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 48757 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 11758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12243 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12243 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1 # number of LoadLockedReq hits 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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.288660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.904762 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.288660 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 200 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 200 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 525 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 525 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 51 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 51 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 525 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 776 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 525 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 251 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 776 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10100000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10100000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26513500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26513500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2575500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2575500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26513500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12675500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 39189000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26513500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12675500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 39189000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.904762 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.904762 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 786 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 502 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1562 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 50304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 776 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 776 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 403000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 787500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 376500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 776 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 576 # Transaction distribution +system.membus.trans_dist::ReadExReq 200 # Transaction distribution +system.membus.trans_dist::ReadExResp 200 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 576 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1552 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 49664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 49664 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 776 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 776 # Request fanout histogram +system.membus.reqLayer0.occupancy 777000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3880000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini new file mode 100644 index 000000000..91d76ecd0 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 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system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true 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+type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json new file mode 100644 index 000000000..e97e6327e --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 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"MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 2, + "description": "Mem", + "srcRegsRelativeLats": [ + 1 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout new file mode 100755 index 000000000..fa339d512 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout @@ -0,0 +1,168 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:31 +gem5 executing on zizzer, pid 34070 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 339160000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt new file mode 100644 index 000000000..c2cf1b21c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt @@ -0,0 +1,763 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000339 # Number of seconds simulated +sim_ticks 339160000 # Number of ticks simulated +final_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 25032 # Simulator instruction rate (inst/s) +host_op_rate 25032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28360795 # Simulator tick rate (ticks/s) +host_mem_usage 244952 # Number of bytes of host memory used +host_seconds 11.96 # Real time elapsed on the host +sim_insts 299354 # Number of instructions simulated +sim_ops 299354 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory +system.physmem.bytes_read::total 95040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 74688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 74688 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1485 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 95040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 95040 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 175 # Per bank write bursts +system.physmem.perBankRdBursts::1 68 # Per bank write bursts +system.physmem.perBankRdBursts::2 18 # Per bank write bursts +system.physmem.perBankRdBursts::3 72 # Per bank write bursts +system.physmem.perBankRdBursts::4 169 # Per bank write bursts +system.physmem.perBankRdBursts::5 291 # Per bank write bursts +system.physmem.perBankRdBursts::6 95 # Per bank write bursts +system.physmem.perBankRdBursts::7 4 # Per bank write bursts +system.physmem.perBankRdBursts::8 9 # Per bank write bursts +system.physmem.perBankRdBursts::9 115 # Per bank write bursts +system.physmem.perBankRdBursts::10 155 # Per bank write bursts +system.physmem.perBankRdBursts::11 169 # Per bank write bursts +system.physmem.perBankRdBursts::12 48 # Per bank write bursts +system.physmem.perBankRdBursts::13 55 # Per bank write bursts +system.physmem.perBankRdBursts::14 15 # Per bank write bursts +system.physmem.perBankRdBursts::15 27 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 338943500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1485 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation +system.physmem.totQLat 19805250 # Total ticks spent queuing +system.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.19 # Data bus utilization in percentage +system.physmem.busUtilRead 2.19 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1195 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 228244.78 # Average gap between requests +system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ) +system.physmem_0.averagePower 553.629673 # Core power per rank (mW) +system.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states +system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states +system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ) +system.physmem_1.averagePower 537.082660 # Core power per rank (mW) +system.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states +system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 80709 # Number of BP lookups +system.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38294 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7506 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 162 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 678320 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 299354 # Number of instructions committed +system.cpu.committedOps 299354 # Number of ops (including micro ops) committed +system.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.265946 # CPI: cycles per instruction +system.cpu.ipc 0.441317 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction +system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction +system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction +system.cpu.op_class_0::IntDiv 40 0.01% 60.32% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 120 0.04% 60.36% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 157 0.05% 60.42% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 60 0.02% 60.44% # Class of committed instruction +system.cpu.op_class_0::FloatMult 30 0.01% 60.45% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 11 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 5 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::MemRead 69348 23.17% 83.62% # Class of committed instruction +system.cpu.op_class_0::MemWrite 48400 16.17% 99.79% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 495 0.17% 99.95% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 299354 # Class of committed instruction +system.cpu.tickCycles 449536 # Number of cycles that the object actually ticked +system.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 241156 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits +system.cpu.dcache.overall_hits::total 119907 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 393 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses +system.cpu.dcache.overall_misses::total 511 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles 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accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # 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overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1167 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1167 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 116 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 116 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1167 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1167 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 318 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990662 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.983051 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.983051 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.991322 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1178 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 118 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2436 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 80512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 100992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1498 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.036527 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1496 99.87% 99.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1498 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 869000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1767000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 480000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1485 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1283 # Transaction distribution +system.membus.trans_dist::ReadExReq 202 # Transaction distribution +system.membus.trans_dist::ReadExResp 202 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1283 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2970 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 95040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 95040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1485 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1485 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1485 # Request fanout histogram +system.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini new file mode 100644 index 000000000..287aed562 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json new file mode 100644 index 000000000..f654bdba2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout new file mode 100755 index 000000000..0379b0893 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout @@ -0,0 +1,168 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:31 +gem5 executing on zizzer, pid 34072 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 149676500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt new file mode 100644 index 000000000..3ddd316d7 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000150 # Number of seconds simulated +sim_ticks 149676500 # Number of ticks simulated +final_tick 149676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 28553 # Simulator instruction rate (inst/s) +host_op_rate 28553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14284274 # Simulator tick rate (ticks/s) +host_mem_usage 234416 # Number of bytes of host memory used +host_seconds 10.48 # Real time elapsed on the host +sim_insts 299191 # Number of instructions simulated +sim_ops 299191 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1197416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 459717 # Number of bytes read from this memory +system.physmem.bytes_read::total 1657133 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1197416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1197416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 301409 # Number of bytes written to this memory +system.physmem.bytes_written::total 301409 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 299354 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 69843 # Number of read requests responded to by this memory +system.physmem.num_reads::total 369197 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 48546 # Number of write requests responded to by this memory +system.physmem.num_writes::total 48546 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000026724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3071403995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11071430719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000026724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000026724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2013736291 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2013736291 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000026724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5085140286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13085167010 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 162 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 149676500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 299354 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 299191 # Number of instructions committed +system.cpu.committedOps 299191 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses +system.cpu.num_func_calls 21816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls +system.cpu.num_int_insts 299008 # number of integer instructions +system.cpu.num_fp_insts 1025 # number of float instructions +system.cpu.num_int_register_reads 394163 # number of times the integer registers were read +system.cpu.num_int_register_writes 205779 # number of times the integer registers were written +system.cpu.num_fp_register_reads 851 # number of times the floating registers were read +system.cpu.num_fp_register_writes 688 # number of times the floating registers were written +system.cpu.num_mem_refs 118390 # number of memory refs +system.cpu.num_load_insts 69843 # Number of load instructions +system.cpu.num_store_insts 48547 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 299354 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 66377 # Number of branches fetched +system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction +system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction +system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction +system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction +system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction +system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction +system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 299354 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 369197 # Transaction distribution +system.membus.trans_dist::ReadResp 369197 # Transaction distribution +system.membus.trans_dist::WriteReq 48546 # Transaction distribution +system.membus.trans_dist::WriteResp 48546 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 598708 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 236778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 835486 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1197416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 761126 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1958542 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 417743 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 417743 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 417743 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini new file mode 100644 index 000000000..0a11055d6 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + 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+[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 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+p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json new file mode 100644 index 000000000..e041cd07a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + 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"MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout new file mode 100755 index 000000000..6698d57dd --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout @@ -0,0 +1,168 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:32 +gem5 executing on zizzer, pid 34074 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 6393532 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..fef27ae57 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt @@ -0,0 +1,645 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.006394 # Number of seconds simulated +sim_ticks 6393532 # Number of ticks simulated +final_tick 6393532 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 13428 # Simulator instruction rate (inst/s) +host_op_rate 13428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 286950 # Simulator tick rate (ticks/s) +host_mem_usage 412476 # Number of bytes of host memory used +host_seconds 22.28 # Real time elapsed on the host +sim_insts 299191 # Number of instructions simulated +sim_ops 299191 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 6256640 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 6256640 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6256384 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 6256384 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 97760 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 97760 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 97756 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 97756 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 978588986 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 978588986 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 978548946 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 978548946 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1957137933 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1957137933 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 97760 # Number of read requests accepted +system.mem_ctrls.writeReqs 97756 # Number of write requests accepted +system.mem_ctrls.readBursts 97760 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 97756 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 3295040 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 2961600 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 3443712 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 6256640 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 6256384 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 46275 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 43917 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 352 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1012 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 26 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 3288 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 5256 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 9431 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 7439 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1368 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1039 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 2533 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 14031 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 3005 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1537 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 918 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 359 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 1066 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 34 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 3555 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 5446 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9633 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8466 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 1431 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 225 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 1069 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2579 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 14351 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 3053 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 1590 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 28 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 923 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 6393460 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 97760 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 97756 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 51485 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 306 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 334 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2779 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 3333 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 3383 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 3473 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 3559 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 3516 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 3321 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 3315 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 3312 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 3312 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 20661 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 326.074440 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 208.715959 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 320.266569 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 5014 24.27% 24.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 6296 30.47% 54.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 3457 16.73% 71.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1315 6.36% 77.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 736 3.56% 81.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 594 2.87% 84.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 389 1.88% 86.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 293 1.42% 87.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 2567 12.42% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 20661 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 3312 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.540459 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.485552 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.332467 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 139 4.20% 4.20% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1517 45.80% 50.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1421 42.90% 92.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 229 6.91% 99.82% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 5 0.15% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.03% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 3312 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 3312 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.246377 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.229566 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.773105 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2986 90.16% 90.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.42% 90.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 147 4.44% 95.02% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 153 4.62% 99.64% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 11 0.33% 99.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 1 0.03% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 3312 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1034437 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 2012652 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 257425 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 20.09 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 39.09 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 515.37 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 538.62 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 978.59 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 978.55 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.23 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.21 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.90 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 36136 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 48490 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 70.19 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.06 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.70 # Average gap between requests +system.mem_ctrls.pageHitRate 80.35 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 95226180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 51522576 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 321836928 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 250476480 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 501546240.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 829542432 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 11702016 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1925180016 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 78745728 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 34138560 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 4099917156 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 641.260129 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 4543849 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 6758 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 212226 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 116933 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 205067 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1630662 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 4221886 # Time in different power states +system.mem_ctrls_1.actEnergy 52336200 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 28311528 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 266327712 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 198927936 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 482492400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 818266464 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 13925376 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1847919480 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 72638976 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 80402640 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 3861548712 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 603.977381 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 4562502 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 13661 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 204136 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 321205 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 189164 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1612911 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 4052455 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 162 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 6393532 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 6393532 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 299191 # Number of instructions committed +system.cpu.committedOps 299191 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses +system.cpu.num_func_calls 21816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls +system.cpu.num_int_insts 299008 # number of integer instructions +system.cpu.num_fp_insts 1025 # number of float instructions +system.cpu.num_int_register_reads 394163 # number of times the integer registers were read +system.cpu.num_int_register_writes 205779 # number of times the integer registers were written +system.cpu.num_fp_register_reads 851 # number of times the floating registers were read +system.cpu.num_fp_register_writes 688 # number of times the floating registers were written +system.cpu.num_mem_refs 118390 # number of memory refs +system.cpu.num_load_insts 69843 # Number of load instructions +system.cpu.num_store_insts 48547 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 6393532 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 66377 # Number of branches fetched +system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction +system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction +system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction +system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction +system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction +system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction +system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 299354 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 195516 # delay histogram for all message +system.ruby.delayHist | 195516 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 195516 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 417744 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 417744 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 417744 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 417743 +system.ruby.latency_hist_seqr::mean 14.304941 +system.ruby.latency_hist_seqr::gmean 2.506373 +system.ruby.latency_hist_seqr::stdev 29.993401 +system.ruby.latency_hist_seqr | 367877 88.06% 88.06% | 46330 11.09% 99.15% | 2431 0.58% 99.74% | 380 0.09% 99.83% | 382 0.09% 99.92% | 309 0.07% 99.99% | 15 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 16 0.00% 100.00% +system.ruby.latency_hist_seqr::total 417743 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 319983 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 319983 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 319983 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 97760 +system.ruby.miss_latency_hist_seqr::mean 57.853989 +system.ruby.miss_latency_hist_seqr::gmean 50.720255 +system.ruby.miss_latency_hist_seqr::stdev 36.989317 +system.ruby.miss_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 97760 +system.ruby.Directory.incomplete_times_seqr 97759 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 319983 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 97760 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 417743 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.645070 +system.ruby.network.routers0.msg_count.Control::2 97760 +system.ruby.network.routers0.msg_count.Data::2 97756 +system.ruby.network.routers0.msg_count.Response_Data::4 97760 +system.ruby.network.routers0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers0.msg_bytes.Control::2 782080 +system.ruby.network.routers0.msg_bytes.Data::2 7038432 +system.ruby.network.routers0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.645070 +system.ruby.network.routers1.msg_count.Control::2 97760 +system.ruby.network.routers1.msg_count.Data::2 97756 +system.ruby.network.routers1.msg_count.Response_Data::4 97760 +system.ruby.network.routers1.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers1.msg_bytes.Control::2 782080 +system.ruby.network.routers1.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.645070 +system.ruby.network.routers2.msg_count.Control::2 97760 +system.ruby.network.routers2.msg_count.Data::2 97756 +system.ruby.network.routers2.msg_count.Response_Data::4 97760 +system.ruby.network.routers2.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers2.msg_bytes.Control::2 782080 +system.ruby.network.routers2.msg_bytes.Data::2 7038432 +system.ruby.network.routers2.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 293280 +system.ruby.network.msg_count.Data 293268 +system.ruby.network.msg_count.Response_Data 293280 +system.ruby.network.msg_count.Writeback_Control 293268 +system.ruby.network.msg_byte.Control 2346240 +system.ruby.network.msg_byte.Data 21115296 +system.ruby.network.msg_byte.Response_Data 21116160 +system.ruby.network.msg_byte.Writeback_Control 2346144 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.645195 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 97760 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers0.throttle1.link_utilization 7.644945 +system.ruby.network.routers0.throttle1.msg_count.Control::2 97760 +system.ruby.network.routers0.throttle1.msg_count.Data::2 97756 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 782080 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.throttle0.link_utilization 7.644945 +system.ruby.network.routers1.throttle0.msg_count.Control::2 97760 +system.ruby.network.routers1.throttle0.msg_count.Data::2 97756 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 782080 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.throttle1.link_utilization 7.645195 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 97760 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.throttle0.link_utilization 7.645195 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 97760 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.throttle1.link_utilization 7.644945 +system.ruby.network.routers2.throttle1.msg_count.Control::2 97760 +system.ruby.network.routers2.throttle1.msg_count.Data::2 97756 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 782080 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 7038432 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 97760 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 97760 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 97760 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 97756 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 97756 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 97756 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 69843 +system.ruby.LD.latency_hist_seqr::mean 28.322194 +system.ruby.LD.latency_hist_seqr::gmean 7.510857 +system.ruby.LD.latency_hist_seqr::stdev 36.108227 +system.ruby.LD.latency_hist_seqr | 55897 80.03% 80.03% | 12888 18.45% 98.49% | 741 1.06% 99.55% | 131 0.19% 99.73% | 105 0.15% 99.88% | 76 0.11% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 69843 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 33083 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 33083 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 33083 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 36760 +system.ruby.LD.miss_latency_hist_seqr::mean 52.911425 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.109058 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.651513 +system.ruby.LD.miss_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 36760 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 48546 +system.ruby.ST.latency_hist_seqr::mean 14.735838 +system.ruby.ST.latency_hist_seqr::gmean 3.058930 +system.ruby.ST.latency_hist_seqr::stdev 27.657147 +system.ruby.ST.latency_hist_seqr | 44298 91.25% 91.25% | 3958 8.15% 99.40% | 180 0.37% 99.77% | 35 0.07% 99.85% | 42 0.09% 99.93% | 23 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 10 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 48546 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 33996 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 33996 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 33996 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 14550 +system.ruby.ST.miss_latency_hist_seqr::mean 46.829553 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.696554 +system.ruby.ST.miss_latency_hist_seqr::stdev 32.883513 +system.ruby.ST.miss_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 14550 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 299354 +system.ruby.IFETCH.latency_hist_seqr::mean 10.964664 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.878483 +system.ruby.IFETCH.latency_hist_seqr::stdev 27.751002 +system.ruby.IFETCH.latency_hist_seqr | 267682 89.42% 89.42% | 29484 9.85% 99.27% | 1510 0.50% 99.77% | 214 0.07% 99.84% | 235 0.08% 99.92% | 210 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 299354 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 252904 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 252904 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 252904 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 46450 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.218773 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.155656 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.458091 +system.ruby.IFETCH.miss_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 46450 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 97760 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.853989 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.720255 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.989317 +system.ruby.Directory.miss_mach_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 97760 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 36760 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.911425 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.109058 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.651513 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 36760 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 14550 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.829553 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.696554 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 32.883513 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 14550 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 46450 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.218773 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.155656 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.458091 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46450 +system.ruby.Directory_Controller.GETX 97760 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 97756 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 97760 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 97756 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 97760 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 97756 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 97760 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 69843 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 299354 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 48546 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 97760 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 36760 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 46450 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 14550 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 33083 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 252904 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 33996 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 83210 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 14550 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini new file mode 100644 index 000000000..be13c3ba9 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json new file mode 100644 index 000000000..382338e98 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout new file mode 100755 index 000000000..709d5c6f6 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout @@ -0,0 +1,168 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:31 +gem5 executing on zizzer, pid 34073 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 497165500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt new file mode 100644 index 000000000..13b031fa9 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000497 # Number of seconds simulated +sim_ticks 497165500 # Number of ticks simulated +final_tick 497165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 27513 # Simulator instruction rate (inst/s) +host_op_rate 27513 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45717681 # Simulator tick rate (ticks/s) +host_mem_usage 243824 # Number of bytes of host memory used +host_seconds 10.87 # Real time elapsed on the host +sim_insts 299191 # Number of instructions simulated +sim_ops 299191 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 20224 # Number of bytes read from this memory +system.physmem.bytes_read::total 81984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 316 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1281 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 124224227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 40678607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 164902834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 124224227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 124224227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 124224227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 40678607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 164902834 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 162 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 497165500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 994331 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 299191 # Number of instructions committed +system.cpu.committedOps 299191 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses +system.cpu.num_func_calls 21816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls +system.cpu.num_int_insts 299008 # number of integer instructions +system.cpu.num_fp_insts 1025 # number of float instructions +system.cpu.num_int_register_reads 394163 # number of times the integer registers were read +system.cpu.num_int_register_writes 205779 # number of times the integer registers were written +system.cpu.num_fp_register_reads 851 # number of times the floating registers were read +system.cpu.num_fp_register_writes 688 # number of times the floating registers were written +system.cpu.num_mem_refs 118390 # number of memory refs +system.cpu.num_load_insts 69843 # Number of load instructions +system.cpu.num_store_insts 48547 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 994331 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 66377 # Number of branches fetched +system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction +system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction +system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction +system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction +system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction 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0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction +system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction +system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 299354 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states 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Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 296 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.077148 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 237094 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 237094 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 69732 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 69732 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 48341 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 48341 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 118073 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 118073 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 118073 # number of overall hits +system.cpu.dcache.overall_hits::total 118073 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 205 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 205 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 316 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 316 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 316 # number of overall misses +system.cpu.dcache.overall_misses::total 316 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6993000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6993000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12915000 # number of WriteReq miss cycles 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demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 118389 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 118389 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001589 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001589 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004223 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004223 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002669 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002669 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002669 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002669 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 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cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6882000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12710000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12710000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19592000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19592000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004223 # mshr miss rate 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latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 26 # number of replacements +system.cpu.icache.tags.tagsinuse 551.353598 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 298390 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 309.212435 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 551.353598 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.269216 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.269216 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 939 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 774 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.458496 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 599675 # Number of tag accesses +system.cpu.icache.tags.data_accesses 599675 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 298390 # number of ReadReq hits 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number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60795500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60795500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60795500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60795500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 299355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 299355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 299355 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 299355 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 299355 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 299355 # number of overall (read+write) accesses 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latency +system.cpu.icache.overall_avg_miss_latency::total 63000.518135 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 26 # number of writebacks +system.cpu.icache.writebacks::total 26 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59830500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59830500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59830500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59830500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59830500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59830500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003224 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.003224 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.003224 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62000.518135 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62000.518135 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62000.518135 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62000.518135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62000.518135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62000.518135 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 821.156872 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 26 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1281 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.020297 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 562.696450 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 258.460422 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017172 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007888 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.025060 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1281 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1096 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.039093 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 11737 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 11737 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 26 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 26 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 205 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 205 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 965 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 965 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 111 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 111 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 965 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 316 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1281 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 965 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 316 # number of overall misses +system.cpu.l2cache.overall_misses::total 1281 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12402500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12402500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58383000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 58383000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6715500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6715500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58383000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19118000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 77501000 # number of demand (read+write) miss cycles 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accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.518135 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.518135 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.518135 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.390320 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.518135 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.390320 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 965 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 965 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1281 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 316 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1281 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10352500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10352500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 48733000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 48733000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5605500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5605500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48733000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15958000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 64691000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48733000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15958000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 64691000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.518135 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.518135 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.518135 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.390320 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.518135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.390320 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1307 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 111 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1956 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 632 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2588 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 83648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1281 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1281 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1281 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 679500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1447500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 474000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1281 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1076 # Transaction distribution +system.membus.trans_dist::ReadExReq 205 # Transaction distribution +system.membus.trans_dist::ReadExResp 205 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1076 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2562 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2562 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 81984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 81984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1281 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1281 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1281 # Request fanout histogram +system.membus.reqLayer0.occupancy 1281500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 6405000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini new file mode 100644 index 000000000..4631a10f3 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json new file mode 100644 index 000000000..0a349ce2a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + 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"cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "max_insts_any_thread": 0, + "do_statistics_insts": true, + "numThreads": 1, + "fetch1LineSnapWidth": 0, + "fetch1ToFetch2BackwardDelay": 1, + "fetch1FetchLimit": 1, + "executeIssueLimit": 2, + "system": "system", + "executeLSQMaxStoreBufferStoresPerCycle": 2, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + 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"opClass": "SimdCmp", + "name": "opClasses11", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCvt", + "name": "opClasses12", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMisc", + "name": "opClasses13", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMult", + "name": "opClasses14", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMultAcc", + "name": "opClasses15", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShift", + "name": "opClasses16", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShiftAcc", + "name": "opClasses17", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17", + "type": "MinorOpClass" + }, + { + "opClass": "SimdSqrt", + "name": "opClasses18", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAdd", + "name": "opClasses19", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAlu", + "name": "opClasses20", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCmp", + "name": "opClasses21", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCvt", + "name": "opClasses22", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatDiv", + "name": "opClasses23", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMisc", + "name": "opClasses24", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMult", + "name": "opClasses25", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMultAcc", + "name": "opClasses26", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatSqrt", + "name": "opClasses27", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "FloatSimd", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits4", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits5", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "MemRead", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "MemWrite", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemRead", + "name": "opClasses2", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemWrite", + "name": "opClasses3", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 2, + "description": "Mem", + "srcRegsRelativeLats": [ + 1 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout new file mode 100755 index 000000000..695544b14 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:32 +gem5 executing on zizzer, pid 34076 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 270200000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt new file mode 100644 index 000000000..a1e10e23b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt @@ -0,0 +1,765 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000270 # Number of seconds simulated +sim_ticks 270200000 # Number of ticks simulated +final_tick 270200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 24805 # Simulator instruction rate (inst/s) +host_op_rate 24804 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29619482 # Simulator tick rate (ticks/s) +host_mem_usage 244928 # Number of bytes of host memory used +host_seconds 9.12 # Real time elapsed on the host +sim_insts 226275 # Number of instructions simulated +sim_ops 226275 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory +system.physmem.bytes_read::total 86336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 67072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 67072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 248230940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 71295337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 319526277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248230940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248230940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248230940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 71295337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 319526277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1349 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 86336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 86336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 173 # Per bank write bursts +system.physmem.perBankRdBursts::1 19 # Per bank write bursts +system.physmem.perBankRdBursts::2 18 # Per bank write bursts +system.physmem.perBankRdBursts::3 76 # Per bank write bursts +system.physmem.perBankRdBursts::4 196 # Per bank write bursts +system.physmem.perBankRdBursts::5 259 # Per bank write bursts +system.physmem.perBankRdBursts::6 19 # Per bank write bursts +system.physmem.perBankRdBursts::7 4 # Per bank write bursts +system.physmem.perBankRdBursts::8 26 # Per bank write bursts +system.physmem.perBankRdBursts::9 99 # Per bank write bursts +system.physmem.perBankRdBursts::10 157 # Per bank write bursts +system.physmem.perBankRdBursts::11 158 # Per bank write bursts +system.physmem.perBankRdBursts::12 48 # Per bank write bursts +system.physmem.perBankRdBursts::13 47 # Per bank write bursts +system.physmem.perBankRdBursts::14 17 # Per bank write bursts +system.physmem.perBankRdBursts::15 33 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 269959000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1349 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 238.583723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 292.748127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53 22.18% 22.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57 23.85% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 30 12.55% 58.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21 8.79% 82.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16 6.69% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation +system.physmem.totQLat 15283750 # Total ticks spent queuing +system.physmem.totMemAccLat 40577500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11329.69 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30079.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 319.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 319.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.50 # Data bus utilization in percentage +system.physmem.busUtilRead 2.50 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1101 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 200117.87 # Average gap between requests +system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13396710 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 455520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 92913420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 13776960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 148257960 # Total energy per rank (pJ) +system.physmem_0.averagePower 548.697113 # Core power per rank (mW) +system.physmem_0.totalIdleTime 238953500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 216000 # Time in different power states +system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 35871500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21502750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 203769750 # Time in different power states +system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11664480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3533280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 82867740 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 20352000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 146140035 # Total energy per rank (pJ) +system.physmem_1.averagePower 540.858753 # Core power per rank (mW) +system.physmem_1.totalIdleTime 235236750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states +system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 53009000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 181741250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 61485 # Number of BP lookups +system.cpu.branchPred.condPredicted 39320 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4384 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 51667 # Number of BTB lookups +system.cpu.branchPred.BTBHits 29457 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 57.013181 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6105 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 4159 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 270200000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 540400 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226275 # Number of instructions committed +system.cpu.committedOps 226275 # Number of ops (including micro ops) committed +system.cpu.discardedOps 10623 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.388244 # CPI: cycles per instruction +system.cpu.ipc 0.418718 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction +system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction +system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction +system.cpu.op_class_0::IntDiv 40 0.02% 60.56% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 104 0.05% 60.60% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 119 0.05% 60.65% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 43 0.02% 60.67% # Class of committed instruction +system.cpu.op_class_0::FloatMult 30 0.01% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 11 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 5 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::MemRead 51297 22.67% 83.36% # Class of committed instruction +system.cpu.op_class_0::MemWrite 37094 16.39% 99.76% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 226275 # Class of committed instruction +system.cpu.tickCycles 340080 # Number of cycles that the object actually ticked +system.cpu.idleCycles 200320 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 242.026814 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 90015 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 298.062914 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 242.026814 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059089 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059089 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 181330 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 181330 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 53182 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 53182 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits 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for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997146 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.996689 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997044 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997146 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80677.958015 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80677.958015 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90864.583333 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90864.583333 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81039.288362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81039.288362 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1048 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1048 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1048 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1349 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1048 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74070500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74070500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7763000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7763000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74070500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21761500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 95832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74070500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21761500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 95832000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997146 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.989691 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989691 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997044 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70677.958015 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70677.958015 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80864.583333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80864.583333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 604 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 91008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1353 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000739 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.027186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1352 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1353 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 780000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1576500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 453000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1349 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1144 # Transaction distribution +system.membus.trans_dist::ReadExReq 205 # Transaction distribution +system.membus.trans_dist::ReadExResp 205 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1144 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2698 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2698 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 86336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 86336 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1349 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1349 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1349 # Request fanout histogram +system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 7151000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini new file mode 100644 index 000000000..22d4ff3c2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini @@ -0,0 +1,872 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + 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+pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 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+tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json new file mode 100644 index 000000000..2675fc23a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json @@ -0,0 +1,1151 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": 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+ "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout new file mode 100755 index 000000000..44893f204 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:32 +gem5 executing on zizzer, pid 34077 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 113397000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt new file mode 100644 index 000000000..7007d9f9a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt @@ -0,0 +1,1020 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000113 # Number of seconds simulated +sim_ticks 113397000 # Number of ticks simulated +final_tick 113397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 22733 # Simulator instruction rate (inst/s) +host_op_rate 22733 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11398414 # Simulator tick rate (ticks/s) +host_mem_usage 246096 # Number of bytes of host memory used +host_seconds 9.95 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory +system.physmem.bytes_read::total 85120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65856 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1330 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 580756105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169881037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 750637142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 580756105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 580756105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 580756105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169881037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 750637142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1330 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1330 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 85120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 85120 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 174 # Per bank write bursts +system.physmem.perBankRdBursts::1 18 # Per bank write bursts +system.physmem.perBankRdBursts::2 15 # Per bank write bursts +system.physmem.perBankRdBursts::3 82 # Per bank write bursts +system.physmem.perBankRdBursts::4 195 # Per bank write bursts +system.physmem.perBankRdBursts::5 254 # Per bank write bursts +system.physmem.perBankRdBursts::6 22 # Per bank write bursts +system.physmem.perBankRdBursts::7 4 # Per bank write bursts +system.physmem.perBankRdBursts::8 25 # Per bank write bursts +system.physmem.perBankRdBursts::9 103 # Per bank write bursts +system.physmem.perBankRdBursts::10 149 # Per bank write bursts +system.physmem.perBankRdBursts::11 145 # Per bank write bursts +system.physmem.perBankRdBursts::12 50 # Per bank write bursts +system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::14 14 # Per bank write bursts +system.physmem.perBankRdBursts::15 29 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 113291000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1330 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 107 # What read queue length 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+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 393.752381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.589157 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.600882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48 22.86% 22.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 44 20.95% 43.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 35 16.67% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18 8.57% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13 6.19% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10 4.76% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 2.38% 82.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 2.38% 84.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32 15.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 210 # Bytes accessed per row activation +system.physmem.totQLat 16749000 # Total ticks spent queuing +system.physmem.totMemAccLat 41686500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12593.23 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31343.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 750.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 750.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 5.86 # Data bus utilization in percentage +system.physmem.busUtilRead 5.86 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.57 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1108 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 85181.20 # Average gap between requests +system.physmem.pageHitRate 83.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9828510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 194400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 40216350 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1207200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 66657450 # Total energy per rank (pJ) +system.physmem_0.averagePower 587.821160 # Core power per rank (mW) +system.physmem_0.totalIdleTime 91041000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 89500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3640000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 3144500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18326750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 88196250 # Time in different power states +system.physmem_1.actEnergy 821100 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 409860 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4041240 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 7868280 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 220800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 41251470 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1959840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 65177550 # Total energy per rank (pJ) +system.physmem_1.averagePower 574.770608 # Core power per rank (mW) +system.physmem_1.totalIdleTime 95505000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 174500 # Time in different power states +system.physmem_1.memoryStateTime::REF 3640000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 5102500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14007750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 90472250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 78040 # Number of BP lookups +system.cpu.branchPred.condPredicted 47825 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4968 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 59525 # Number of BTB lookups +system.cpu.branchPred.BTBHits 36023 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 60.517430 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14832 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6672 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8160 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2577 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 113397000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 226795 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 73757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 336548 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78040 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42695 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 87262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10228 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 60631 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2398 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 166726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.018569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.822541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 89937 53.94% 53.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11784 7.07% 61.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13843 8.30% 69.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 11668 7.00% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5791 3.47% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6797 4.08% 83.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2856 1.71% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4611 2.77% 88.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19439 11.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 166726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.344099 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483930 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 72653 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18351 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70165 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1269 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4288 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 13538 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 899 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 310274 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2536 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4288 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 75144 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7711 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3158 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68795 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7630 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 298982 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 782 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6500 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 208109 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 389749 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 387389 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2360 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 155141 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 52968 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 133 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3030 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 62164 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43440 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1172 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 335 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 273555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 261697 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 610 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 47545 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26182 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 166726 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.569623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.886679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67362 40.40% 40.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36208 21.72% 62.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 23951 14.37% 76.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10817 6.49% 82.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10352 6.21% 89.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8029 4.82% 94.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7579 4.55% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1315 0.79% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1113 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 166726 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 704 10.43% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2989 44.27% 54.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2970 43.99% 98.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 88 1.30% 99.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1 0.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 117 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 159679 61.02% 61.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 172 0.07% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 59286 22.65% 84.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 40948 15.65% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 721 0.28% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 179 0.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 261697 # Type of FU issued +system.cpu.iq.rate 1.153892 # Inst issue rate +system.cpu.iq.fu_busy_cnt 6752 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025801 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 694798 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 318360 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249994 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2684 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2938 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1006 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266946 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1386 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5628 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 10453 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6211 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 4288 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4913 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 272 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 273705 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3278 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 62164 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43440 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 150 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1281 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3469 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4750 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 254156 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 58399 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7541 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 98174 # number of memory reference insts executed +system.cpu.iew.exec_branches 57098 # Number of branches executed +system.cpu.iew.exec_stores 39775 # Number of stores executed +system.cpu.iew.exec_rate 1.120642 # Inst execution rate +system.cpu.iew.wb_sent 252228 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 251000 # cumulative count of insts written-back +system.cpu.iew.wb_producers 95690 # num instructions producing a value +system.cpu.iew.wb_consumers 132115 # num instructions consuming a value +system.cpu.iew.wb_rate 1.106726 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.724293 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 47577 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 117 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4142 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.434355 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.158076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82961 52.62% 52.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 25849 16.39% 69.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14396 9.13% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11000 6.98% 85.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5848 3.71% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5974 3.79% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3323 2.11% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1258 0.80% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7064 4.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157673 # Number of insts commited each cycle +system.cpu.commit.committedInsts 226159 # Number of instructions committed +system.cpu.commit.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 88940 # Number of memory references committed +system.cpu.commit.loads 51711 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 50405 # Number of branches committed +system.cpu.commit.fp_insts 862 # Number of committed floating point instructions. +system.cpu.commit.int_insts 225991 # Number of committed integer instructions. +system.cpu.commit.function_calls 16616 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 136540 60.37% 60.37% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 325 0.14% 60.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 40 0.02% 60.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 104 0.05% 60.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 119 0.05% 60.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 43 0.02% 60.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 30 0.01% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 11 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 5 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 51297 22.68% 83.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 37093 16.40% 99.76% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 226159 # Class of committed instruction +system.cpu.commit.bw_lim_events 7064 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 422850 # The number of ROB reads +system.cpu.rob.rob_writes 556608 # The number of ROB writes +system.cpu.timesIdled 458 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60069 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 226159 # Number of Instructions Simulated +system.cpu.committedOps 226159 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.002812 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.002812 # CPI: Total CPI of All Threads +system.cpu.ipc 0.997196 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.997196 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 329004 # number of integer regfile reads +system.cpu.int_regfile_writes 174767 # number of integer regfile writes +system.cpu.fp_regfile_reads 880 # number of floating regfile reads +system.cpu.fp_regfile_writes 753 # number of floating regfile writes +system.cpu.misc_regfile_reads 448 # number of misc regfile reads +system.cpu.misc_regfile_writes 313 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 244.736374 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 87597 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 291.019934 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 244.736374 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059750 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059750 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.073486 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 179361 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179361 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 51858 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51858 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 35739 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 35739 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 87597 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 87597 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 87597 # number of overall hits +system.cpu.dcache.overall_hits::total 87597 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 443 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 443 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1490 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1490 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1933 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1933 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1933 # number of overall misses +system.cpu.dcache.overall_misses::total 1933 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36817500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36817500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 96718425 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 96718425 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133535925 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133535925 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133535925 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133535925 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 52301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 52301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 89530 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 89530 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 89530 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 89530 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008470 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008470 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040023 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.040023 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021591 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021591 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021591 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021591 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83109.480813 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83109.480813 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64911.694631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64911.694631 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69082.216762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69082.216762 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5513 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 79 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.784810 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1286 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1632 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1632 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1632 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1632 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 204 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 204 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 301 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16055500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16055500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24812500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24812500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24812500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24812500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003362 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003362 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90278.350515 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90278.350515 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78703.431373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78703.431373 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency 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+system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 122286 # Number of tag accesses +system.cpu.icache.tags.data_accesses 122286 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 59273 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59273 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59273 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59273 # number of demand (read+write) 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miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1404 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 72 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1131 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2736 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 89664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 3 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 192 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002247 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.047369 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1332 99.78% 99.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3 0.22% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1335 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 771000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1551000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 451500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1330 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1126 # Transaction distribution +system.membus.trans_dist::ReadExReq 204 # Transaction distribution +system.membus.trans_dist::ReadExResp 204 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1126 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2660 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 85120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1330 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1330 # Request fanout histogram +system.membus.reqLayer0.occupancy 1627500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 7008750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini new file mode 100644 index 000000000..50ff7280f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json new file mode 100644 index 000000000..ecd3e1c52 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout new file mode 100755 index 000000000..1aedc7412 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:33 +gem5 executing on zizzer, pid 34079 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 113137000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt new file mode 100644 index 000000000..9a7a22440 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000113 # Number of seconds simulated +sim_ticks 113137000 # Number of ticks simulated +final_tick 113137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 28615 # Simulator instruction rate (inst/s) +host_op_rate 28615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14314809 # Simulator tick rate (ticks/s) +host_mem_usage 234404 # Number of bytes of host memory used +host_seconds 7.90 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 905100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 339455 # Number of bytes read from this memory +system.physmem.bytes_read::total 1244555 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 905100 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 905100 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 226262 # Number of bytes written to this memory +system.physmem.bytes_written::total 226262 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 226275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 51711 # Number of read requests responded to by this memory +system.physmem.num_reads::total 277986 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 37229 # Number of write requests responded to by this memory +system.physmem.num_writes::total 37229 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000035355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3000388909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11000424264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000035355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000035355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1999893934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1999893934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000035355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5000282843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13000318198 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 113137000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 226275 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226159 # Number of instructions committed +system.cpu.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses +system.cpu.num_func_calls 16616 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls +system.cpu.num_int_insts 225992 # number of integer instructions +system.cpu.num_fp_insts 862 # number of float instructions +system.cpu.num_int_register_reads 298589 # number of times the integer registers were read +system.cpu.num_int_register_writes 154866 # number of times the integer registers were written +system.cpu.num_fp_register_reads 733 # number of times the floating registers were read +system.cpu.num_fp_register_writes 588 # number of times the floating registers were written +system.cpu.num_mem_refs 88941 # number of memory refs +system.cpu.num_load_insts 51711 # Number of load instructions +system.cpu.num_store_insts 37230 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 226275 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 50405 # Number of branches fetched +system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction +system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction +system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction +system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction +system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction +system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 226275 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 277986 # Transaction distribution +system.membus.trans_dist::ReadResp 277986 # Transaction distribution +system.membus.trans_dist::WriteReq 37229 # Transaction distribution +system.membus.trans_dist::WriteResp 37229 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 452550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 177880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 630430 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 905100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 565717 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1470817 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 315215 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 315215 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 315215 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini new file mode 100644 index 000000000..eb91af64f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 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int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 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system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] 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+type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 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+[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + 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system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + 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+[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json new file mode 100644 index 000000000..10ddc0f69 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": 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"max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout new file mode 100755 index 000000000..5fb7ec2e1 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:42 +gem5 executing on zizzer, pid 34083 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 4665394 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..2726406d4 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.004665 # Number of seconds simulated +sim_ticks 4665394 # Number of ticks simulated +final_tick 4665394 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 17585 # Simulator instruction rate (inst/s) +host_op_rate 17585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 362753 # Simulator tick rate (ticks/s) +host_mem_usage 412420 # Number of bytes of host memory used +host_seconds 12.86 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 4623808 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 4623808 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4623552 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 4623552 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 72247 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 72247 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 72243 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 72243 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 991086283 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 991086283 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 991031411 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 991031411 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1982117695 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1982117695 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 72247 # Number of read requests accepted +system.mem_ctrls.writeReqs 72243 # Number of write requests accepted +system.mem_ctrls.readBursts 72247 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 72243 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 2375168 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 2248640 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 2474112 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 4623808 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 4623552 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 35135 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 33568 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 360 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 641 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 2702 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 5567 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 5413 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 5211 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1018 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 201 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 679 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1777 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 10251 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1439 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 39 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 620 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 374 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 689 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 35 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 2847 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 5733 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 5572 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 5809 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 1085 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 201 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 742 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 1831 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 10392 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 1454 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 1229 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 39 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 626 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 4665243 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 72247 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 72243 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 37112 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 208 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 255 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2030 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 2392 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2414 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 2512 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 2548 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 2499 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 2385 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 2380 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 2383 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 2380 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 13232 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 366.340992 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 230.810737 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 342.245951 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 3082 23.29% 23.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 3681 27.82% 51.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1764 13.33% 64.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 976 7.38% 71.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 696 5.26% 77.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 455 3.44% 80.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 307 2.32% 82.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 275 2.08% 84.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1996 15.08% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 13232 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 2379 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.599412 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.547106 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.309736 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 94 3.95% 3.95% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1021 42.92% 46.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1131 47.54% 94.41% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 122 5.13% 99.54% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 10 0.42% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.04% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 2379 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 2379 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.249685 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.232515 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.782399 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2139 89.91% 89.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 18 0.76% 90.67% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 109 4.58% 95.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 94 3.95% 99.20% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 19 0.80% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 2379 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 719075 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 1424203 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 185560 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 19.38 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 38.38 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 509.10 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 530.31 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 991.09 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 991.03 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.12 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.98 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.14 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.97 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 27462 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 35070 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 74.00 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.68 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.29 # Average gap between requests +system.mem_ctrls.pageHitRate 82.51 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 60632880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 32801496 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 239275680 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 184946688 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 366325440.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 608748144 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 8669568 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1381360344 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 69824640 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 28732560 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 2981317440 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 639.028009 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 3307806 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 5774 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 155020 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 96709 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 181835 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1196757 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 3029299 # Time in different power states +system.mem_ctrls_1.actEnergy 33886440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 18326952 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 184691808 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 137924928 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 348500880.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 590211744 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 11048832 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1320078504 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 60484992 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 72883440 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 2778038520 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 595.456358 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 3342297 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 12341 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 147456 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 289875 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 157513 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1163300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 2894909 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 4665394 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 4665394 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226159 # Number of instructions committed +system.cpu.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses +system.cpu.num_func_calls 16616 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls +system.cpu.num_int_insts 225992 # number of integer instructions +system.cpu.num_fp_insts 862 # number of float instructions +system.cpu.num_int_register_reads 298589 # number of times the integer registers were read +system.cpu.num_int_register_writes 154866 # number of times the integer registers were written +system.cpu.num_fp_register_reads 733 # number of times the floating registers were read +system.cpu.num_fp_register_writes 588 # number of times the floating registers were written +system.cpu.num_mem_refs 88941 # number of memory refs +system.cpu.num_load_insts 51711 # Number of load instructions +system.cpu.num_store_insts 37230 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 4665394 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 50405 # Number of branches fetched +system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction +system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction +system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction +system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction +system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction +system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 226275 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 144490 # delay histogram for all message +system.ruby.delayHist | 144490 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 144490 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 315216 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 315216 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 315216 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 315215 +system.ruby.latency_hist_seqr::mean 13.800673 +system.ruby.latency_hist_seqr::gmean 2.449814 +system.ruby.latency_hist_seqr::stdev 29.448647 +system.ruby.latency_hist_seqr | 279385 88.63% 88.63% | 33252 10.55% 99.18% | 1716 0.54% 99.73% | 307 0.10% 99.82% | 278 0.09% 99.91% | 236 0.07% 99.99% | 20 0.01% 99.99% | 8 0.00% 100.00% | 0 0.00% 100.00% | 13 0.00% 100.00% +system.ruby.latency_hist_seqr::total 315215 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 242968 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 242968 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 242968 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 72247 +system.ruby.miss_latency_hist_seqr::mean 56.849572 +system.ruby.miss_latency_hist_seqr::gmean 49.864909 +system.ruby.miss_latency_hist_seqr::stdev 37.140999 +system.ruby.miss_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 72247 +system.ruby.Directory.incomplete_times_seqr 72246 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 242968 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 72247 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 315215 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.742647 +system.ruby.network.routers0.msg_count.Control::2 72247 +system.ruby.network.routers0.msg_count.Data::2 72243 +system.ruby.network.routers0.msg_count.Response_Data::4 72247 +system.ruby.network.routers0.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers0.msg_bytes.Control::2 577976 +system.ruby.network.routers0.msg_bytes.Data::2 5201496 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.742647 +system.ruby.network.routers1.msg_count.Control::2 72247 +system.ruby.network.routers1.msg_count.Data::2 72243 +system.ruby.network.routers1.msg_count.Response_Data::4 72247 +system.ruby.network.routers1.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers1.msg_bytes.Control::2 577976 +system.ruby.network.routers1.msg_bytes.Data::2 5201496 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.742647 +system.ruby.network.routers2.msg_count.Control::2 72247 +system.ruby.network.routers2.msg_count.Data::2 72243 +system.ruby.network.routers2.msg_count.Response_Data::4 72247 +system.ruby.network.routers2.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers2.msg_bytes.Control::2 577976 +system.ruby.network.routers2.msg_bytes.Data::2 5201496 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 216741 +system.ruby.network.msg_count.Data 216729 +system.ruby.network.msg_count.Response_Data 216741 +system.ruby.network.msg_count.Writeback_Control 216729 +system.ruby.network.msg_byte.Control 1733928 +system.ruby.network.msg_byte.Data 15604488 +system.ruby.network.msg_byte.Response_Data 15605352 +system.ruby.network.msg_byte.Writeback_Control 1733832 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.742819 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 72247 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers0.throttle1.link_utilization 7.742476 +system.ruby.network.routers0.throttle1.msg_count.Control::2 72247 +system.ruby.network.routers0.throttle1.msg_count.Data::2 72243 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 577976 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5201496 +system.ruby.network.routers1.throttle0.link_utilization 7.742476 +system.ruby.network.routers1.throttle0.msg_count.Control::2 72247 +system.ruby.network.routers1.throttle0.msg_count.Data::2 72243 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 577976 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 5201496 +system.ruby.network.routers1.throttle1.link_utilization 7.742819 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 72247 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers2.throttle0.link_utilization 7.742819 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 72247 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers2.throttle1.link_utilization 7.742476 +system.ruby.network.routers2.throttle1.msg_count.Control::2 72247 +system.ruby.network.routers2.throttle1.msg_count.Data::2 72243 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 577976 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5201496 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 72247 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 72247 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 72247 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 72243 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 72243 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 72243 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 51711 +system.ruby.LD.latency_hist_seqr::mean 28.269208 +system.ruby.LD.latency_hist_seqr::gmean 7.619512 +system.ruby.LD.latency_hist_seqr::stdev 36.060908 +system.ruby.LD.latency_hist_seqr | 41177 79.63% 79.63% | 9735 18.83% 98.45% | 541 1.05% 99.50% | 99 0.19% 99.69% | 79 0.15% 99.85% | 70 0.14% 99.98% | 7 0.01% 99.99% | 2 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 51711 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 24257 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 24257 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 24257 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 27454 +system.ruby.LD.miss_latency_hist_seqr::mean 52.362934 +system.ruby.LD.miss_latency_hist_seqr::gmean 45.830488 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.811219 +system.ruby.LD.miss_latency_hist_seqr | 16920 61.63% 61.63% | 9735 35.46% 97.09% | 541 1.97% 99.06% | 99 0.36% 99.42% | 79 0.29% 99.71% | 70 0.25% 99.96% | 7 0.03% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 27454 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 37229 +system.ruby.ST.latency_hist_seqr::mean 15.219587 +system.ruby.ST.latency_hist_seqr::gmean 3.175846 +system.ruby.ST.latency_hist_seqr::stdev 28.311515 +system.ruby.ST.latency_hist_seqr | 33814 90.83% 90.83% | 3147 8.45% 99.28% | 181 0.49% 99.77% | 30 0.08% 99.85% | 22 0.06% 99.91% | 24 0.06% 99.97% | 1 0.00% 99.97% | 1 0.00% 99.98% | 0 0.00% 99.98% | 9 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 37229 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 25699 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 25699 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 25699 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 11530 +system.ruby.ST.miss_latency_hist_seqr::mean 46.913356 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.729617 +system.ruby.ST.miss_latency_hist_seqr::stdev 33.659248 +system.ruby.ST.miss_latency_hist_seqr | 8115 70.38% 70.38% | 3147 27.29% 97.68% | 181 1.57% 99.25% | 30 0.26% 99.51% | 22 0.19% 99.70% | 24 0.21% 99.90% | 1 0.01% 99.91% | 1 0.01% 99.92% | 0 0.00% 99.92% | 9 0.08% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 11530 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 226275 +system.ruby.IFETCH.latency_hist_seqr::mean 10.260700 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.811203 +system.ruby.IFETCH.latency_hist_seqr::stdev 26.801914 +system.ruby.IFETCH.latency_hist_seqr | 204394 90.33% 90.33% | 20370 9.00% 99.33% | 994 0.44% 99.77% | 178 0.08% 99.85% | 177 0.08% 99.93% | 142 0.06% 99.99% | 12 0.01% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 226275 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 193012 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 193012 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 193012 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 33263 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.996873 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 56.865504 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.748066 +system.ruby.IFETCH.miss_latency_hist_seqr | 11382 34.22% 34.22% | 20370 61.24% 95.46% | 994 2.99% 98.45% | 178 0.54% 98.98% | 177 0.53% 99.51% | 142 0.43% 99.94% | 12 0.04% 99.98% | 5 0.02% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 33263 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 72247 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.849572 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.864909 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.140999 +system.ruby.Directory.miss_mach_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 72247 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 27454 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.362934 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.830488 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.811219 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 16920 61.63% 61.63% | 9735 35.46% 97.09% | 541 1.97% 99.06% | 99 0.36% 99.42% | 79 0.29% 99.71% | 70 0.25% 99.96% | 7 0.03% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 27454 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 11530 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.913356 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.729617 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.659248 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 8115 70.38% 70.38% | 3147 27.29% 97.68% | 181 1.57% 99.25% | 30 0.26% 99.51% | 22 0.19% 99.70% | 24 0.21% 99.90% | 1 0.01% 99.91% | 1 0.01% 99.92% | 0 0.00% 99.92% | 9 0.08% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 11530 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 33263 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.996873 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 56.865504 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.748066 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 11382 34.22% 34.22% | 20370 61.24% 95.46% | 994 2.99% 98.45% | 178 0.54% 98.98% | 177 0.53% 99.51% | 142 0.43% 99.94% | 12 0.04% 99.98% | 5 0.02% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 33263 +system.ruby.Directory_Controller.GETX 72247 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 72243 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 72247 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 72243 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 72247 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 72243 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 72247 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 51711 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 226275 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 37229 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 72247 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 27454 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 33263 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 11530 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 24257 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 193012 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 25699 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 60717 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 11530 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini new file mode 100644 index 000000000..47eb7a125 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json new file mode 100644 index 000000000..58b36202f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout new file mode 100755 index 000000000..5080c6704 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:33 +gem5 executing on zizzer, pid 34081 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 385535500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt new file mode 100644 index 000000000..b9ee4135f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt @@ -0,0 +1,521 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000386 # Number of seconds simulated +sim_ticks 385535500 # Number of ticks simulated +final_tick 385535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 27855 # Simulator instruction rate (inst/s) +host_op_rate 27855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47485128 # Simulator tick rate (ticks/s) +host_mem_usage 243704 # Number of bytes of host memory used +host_seconds 8.12 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 53632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18944 # Number of bytes read from this memory +system.physmem.bytes_read::total 72576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 53632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 53632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 838 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 296 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1134 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 139110406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 49136850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 188247256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 139110406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 139110406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 139110406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 49136850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 188247256 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 385535500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 771071 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226159 # Number of instructions committed +system.cpu.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses +system.cpu.num_func_calls 16616 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls +system.cpu.num_int_insts 225992 # number of integer instructions +system.cpu.num_fp_insts 862 # number of float instructions +system.cpu.num_int_register_reads 298589 # number of times the integer registers were read +system.cpu.num_int_register_writes 154866 # number of times the integer registers were written +system.cpu.num_fp_register_reads 733 # number of times the floating registers were read +system.cpu.num_fp_register_writes 588 # number of times the floating registers were written +system.cpu.num_mem_refs 88941 # number of memory refs +system.cpu.num_load_insts 51711 # Number of load instructions +system.cpu.num_store_insts 37230 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 771071 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 50405 # Number of branches fetched +system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction +system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction +system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction +system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction +system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction +system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 226275 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 246.215915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 88644 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 299.472973 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 246.215915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.060111 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.060111 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 178176 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 178176 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 51622 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51622 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 88644 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 88644 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 88644 # number of overall hits +system.cpu.dcache.overall_hits::total 88644 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses 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average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 207 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 838 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 838 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 89 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 89 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 838 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 838 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1134 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 42319500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 42319500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4494500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4494500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42319500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14948000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 57267500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42319500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14948000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 57267500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998808 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999119 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999119 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.596659 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.596659 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.596659 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.440917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.596659 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.440917 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1166 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 928 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 31 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 839 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 89 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1709 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2301 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 55680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 74624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1135 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1135 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1135 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 614000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1258500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1134 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 927 # Transaction distribution +system.membus.trans_dist::ReadExReq 207 # Transaction distribution +system.membus.trans_dist::ReadExResp 207 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 927 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2268 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2268 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 72576 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1134 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1134 # Request fanout histogram +system.membus.reqLayer0.occupancy 1134500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 5670000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini new file mode 100644 index 000000000..8ba8fdf37 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json new file mode 100644 index 000000000..5ab2c4281 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + 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"eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout new file mode 100755 index 000000000..5f73fd76b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:43 +gem5 executing on zizzer, pid 34087 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157E0 +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540730 +fstat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540730 +open, stat: PASS +Bytes read: 1 +String read: +open, read, unlink: [1;31mFAIL[0m (expected 1; found 0) +Exiting @ tick 257396500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt new file mode 100644 index 000000000..b9db11c0c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt @@ -0,0 +1,761 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000257 # Number of seconds simulated +sim_ticks 257396500 # Number of ticks simulated +final_tick 257396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 23064 # Simulator instruction rate (inst/s) +host_op_rate 23064 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29446323 # Simulator tick rate (ticks/s) +host_mem_usage 244684 # Number of bytes of host memory used +host_seconds 8.74 # Real time elapsed on the host +sim_insts 201609 # Number of instructions simulated +sim_ops 201609 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 70720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18880 # Number of bytes read from this memory +system.physmem.bytes_read::total 89600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 70720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 70720 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 295 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1400 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 274751211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 73349871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 348101081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 274751211 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 274751211 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 274751211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 73349871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 348101081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1400 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1400 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 89600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 89600 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 195 # Per bank write bursts +system.physmem.perBankRdBursts::1 221 # Per bank write bursts +system.physmem.perBankRdBursts::2 35 # Per bank write bursts +system.physmem.perBankRdBursts::3 87 # Per bank write bursts +system.physmem.perBankRdBursts::4 141 # Per bank write bursts +system.physmem.perBankRdBursts::5 86 # Per bank write bursts +system.physmem.perBankRdBursts::6 5 # Per bank write bursts +system.physmem.perBankRdBursts::7 106 # Per bank write bursts +system.physmem.perBankRdBursts::8 78 # Per bank write bursts +system.physmem.perBankRdBursts::9 96 # Per bank write bursts +system.physmem.perBankRdBursts::10 80 # Per bank write bursts +system.physmem.perBankRdBursts::11 128 # Per bank write bursts +system.physmem.perBankRdBursts::12 40 # Per bank write bursts +system.physmem.perBankRdBursts::13 27 # Per bank write bursts +system.physmem.perBankRdBursts::14 51 # Per bank write bursts +system.physmem.perBankRdBursts::15 24 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 257156500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1400 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 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+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 274 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.270073 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.910663 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 283.246990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 71 25.91% 25.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 59 21.53% 47.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52 18.98% 66.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26 9.49% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14 5.11% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 23 8.39% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8 2.92% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.09% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18 6.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 274 # Bytes accessed per row activation +system.physmem.totQLat 19864500 # Total ticks spent queuing +system.physmem.totMemAccLat 46114500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7000000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14188.93 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32938.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 348.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 348.10 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.72 # Data bus utilization in percentage +system.physmem.busUtilRead 2.72 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1124 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 183683.21 # Average gap between requests +system.physmem.pageHitRate 80.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1299480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 690690 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6254640 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14953950 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 477120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 94483770 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6205440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 144648210 # Total energy per rank (pJ) +system.physmem_0.averagePower 561.964316 # Core power per rank (mW) +system.physmem_0.totalIdleTime 223185500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states +system.physmem_0.memoryStateTime::REF 8580000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16154500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 25250500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 207201500 # Time in different power states +system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 349140 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3741360 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 14751360.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 9433500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3408960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 53834790 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 13144800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18682440 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 118017510 # Total energy per rank (pJ) +system.physmem_1.averagePower 458.502938 # Core power per rank (mW) +system.physmem_1.totalIdleTime 227632750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8194250 # Time in different power states +system.physmem_1.memoryStateTime::REF 6246000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 75541750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 34227000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15120250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 118067250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 58095 # Number of BP lookups +system.cpu.branchPred.condPredicted 37339 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4808 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 47628 # Number of BTB lookups +system.cpu.branchPred.BTBHits 25748 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 54.060637 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 9498 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5462 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 4036 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2282 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 130 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 257396500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 514793 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 201609 # Number of instructions committed +system.cpu.committedOps 201609 # Number of ops (including micro ops) committed +system.cpu.discardedOps 12686 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.553423 # CPI: cycles per instruction +system.cpu.ipc 0.391631 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 132 0.07% 0.07% # Class of committed instruction +system.cpu.op_class_0::IntAlu 120936 59.99% 60.05% # Class of committed instruction +system.cpu.op_class_0::IntMult 297 0.15% 60.20% # Class of committed instruction +system.cpu.op_class_0::IntDiv 166 0.08% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::MemRead 46389 23.01% 83.29% # Class of committed instruction +system.cpu.op_class_0::MemWrite 33689 16.71% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 201609 # Class of committed instruction +system.cpu.tickCycles 299839 # Number of cycles that the object actually ticked +system.cpu.idleCycles 214954 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 237.251323 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 81600 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 275.675676 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 237.251323 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.057923 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.057923 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 164496 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 164496 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 48321 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48321 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 33279 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 33279 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 81600 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 81600 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 81600 # number of overall hits +system.cpu.dcache.overall_hits::total 81600 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses +system.cpu.dcache.overall_misses::total 500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8843000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8843000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32769500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32769500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41612500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41612500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41612500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41612500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48412 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48412 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 82100 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82100 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82100 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82100 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001880 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001880 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012141 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012141 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006090 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006090 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006090 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006090 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 97175.824176 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 97175.824176 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80121.026895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80121.026895 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 83225 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 83225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 83225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 83225 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 198 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 198 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 204 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 204 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 204 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 85 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 85 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 211 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 211 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8161000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8161000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16932000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16932000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25093000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25093000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25093000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25093000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001756 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001756 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003605 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003605 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96011.764706 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96011.764706 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80246.445498 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80246.445498 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 44 # number of replacements +system.cpu.icache.tags.tagsinuse 581.971054 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 86953 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1105 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 78.690498 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 581.971054 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.284166 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.284166 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1061 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 746 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.518066 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 177221 # Number of tag accesses +system.cpu.icache.tags.data_accesses 177221 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 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(read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21686500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 103472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 81785500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21686500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 103472000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 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mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74014.027149 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74014.027149 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 85488.095238 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85488.095238 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74014.027149 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73513.559322 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73908.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74014.027149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73513.559322 # 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# Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2846 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 92480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1401 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000714 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.026717 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1400 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1401 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 766500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1657500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1400 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1189 # Transaction distribution +system.membus.trans_dist::ReadExReq 211 # Transaction distribution +system.membus.trans_dist::ReadExResp 211 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1189 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2800 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 89600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 89600 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1400 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1400 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1400 # Request fanout histogram +system.membus.reqLayer0.occupancy 1611500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 7433000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini new file mode 100644 index 000000000..d8016ae2d --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json new file mode 100644 index 000000000..e72d8a19b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout new file mode 100755 index 000000000..97d9d4fd2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout @@ -0,0 +1,171 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:43 +gem5 executing on zizzer, pid 34088 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157E0 +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540729 +fstat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540730 +open, stat: PASS +Bytes read: 15 +String read: this is a test +open, read, unlink: PASS +times: + tms_utime = 0 + tms_stime = 0 + tms_cutime = 0 + tms_cstime = 0 +times: PASS +timeval: + tv_sec = 1000000000 + tv_usec = 102 +gettimeofday: PASS +Cycles: 210287 +rdcycle: PASS +Time: 1480540732 +rdtime: PASS +Instructions Retired: 215205 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 133105500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt new file mode 100644 index 000000000..774499b09 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000133 # Number of seconds simulated +sim_ticks 133105500 # Number of ticks simulated +final_tick 133105500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 24056 # Simulator instruction rate (inst/s) +host_op_rate 24056 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12036090 # Simulator tick rate (ticks/s) +host_mem_usage 234212 # Number of bytes of host memory used +host_seconds 11.06 # Real time elapsed on the host +sim_insts 266028 # Number of instructions simulated +sim_ops 266028 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1064848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 412103 # Number of bytes read from this memory +system.physmem.bytes_read::total 1476951 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1064848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1064848 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 270848 # Number of bytes written to this memory +system.physmem.bytes_written::total 270848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 266212 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 62869 # Number of read requests responded to by this memory +system.physmem.num_reads::total 329081 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 43712 # Number of write requests responded to by this memory +system.physmem.num_writes::total 43712 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000030051 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3096062897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11096092949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000030051 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000030051 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2034837028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2034837028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000030051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5130899925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13130929977 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 183 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 133105500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 266212 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 266028 # Number of instructions committed +system.cpu.committedOps 266028 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 266027 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 19074 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39822 # number of instructions that are conditional controls +system.cpu.num_int_insts 266027 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 351579 # number of times the integer registers were read +system.cpu.num_int_register_writes 182492 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 106582 # number of memory refs +system.cpu.num_load_insts 62869 # Number of load instructions +system.cpu.num_store_insts 43713 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 266212 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 58896 # Number of branches fetched +system.cpu.op_class::No_OpClass 188 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 158769 59.64% 59.71% # Class of executed instruction +system.cpu.op_class::IntMult 431 0.16% 59.87% # Class of executed instruction +system.cpu.op_class::IntDiv 242 0.09% 59.96% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::MemRead 62869 23.62% 83.58% # Class of executed instruction +system.cpu.op_class::MemWrite 43713 16.42% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 266212 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 329081 # Transaction distribution +system.membus.trans_dist::ReadResp 329081 # Transaction distribution +system.membus.trans_dist::WriteReq 43712 # Transaction distribution +system.membus.trans_dist::WriteResp 43712 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 532424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 213162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 745586 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1064848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 682951 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1747799 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 372793 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 372793 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 372793 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini new file mode 100644 index 000000000..f98935352 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + 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int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 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+[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + 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system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] 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+port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json new file mode 100644 index 000000000..0c28bed70 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": "SLAVE" + }, + "name": "sys_port_proxy", + "p_state_clk_gate_min": 1, + "no_retry_on_stall": false, + "p_state_clk_gate_bins": 20, + "support_data_reqs": true, + "cxx_class": "RubyPortProxy", + "clk_domain": "system.clk_domain", + "power_model": null, + "is_cpu_sequencer": true, + "version": 0, + "eventq_index": 0, + "using_ruby_tester": false, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.sys_port_proxy", + "type": "RubyPortProxy", + "ruby_system": "system.ruby" + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "ruby": { + "all_instructions": false, + "memory_size_bits": 48, + "cxx_class": "RubySystem", + "l1_cntrl0": { + "requestFromCache": { + "ordered": true, + "name": "requestFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[0]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.requestFromCache", + "type": "MessageBuffer" + }, + "cxx_class": "L1Cache_Controller", + "forwardToCache": { + "ordered": true, + "name": "forwardToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[0]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.forwardToCache", + "type": "MessageBuffer" + }, + "system": "system", + "cluster_id": 0, + "sequencer": { + "no_retry_on_stall": false, + "deadlock_threshold": 500000, + "using_ruby_tester": false, + "system": "system", + "dcache": "system.ruby.l1_cntrl0.cacheMemory", + "cxx_class": "Sequencer", + "garnet_standalone": false, + "clk_domain": "system.cpu.clk_domain", + "icache_hit_latency": 1, + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "type": "RubySequencer", + "icache": "system.ruby.l1_cntrl0.cacheMemory", + "slave": { + "peer": [ + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "power_model": null, + "coreid": 99, + "path": "system.ruby.l1_cntrl0.sequencer", + "ruby_system": "system.ruby", + "support_inst_reqs": true, + "name": "sequencer", + "max_outstanding_requests": 16, + "p_state_clk_gate_bins": 20, + "dcache_hit_latency": 1, + "support_data_reqs": true, + "is_cpu_sequencer": true + }, + "type": "L1Cache_Controller", + "issue_latency": 2, + "recycle_latency": 10, + "clk_domain": "system.cpu.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "number_of_TBEs": 256, + "p_state_clk_gate_min": 1, + "responseToCache": { + "ordered": true, + "name": "responseToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[1]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseToCache", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "responseFromCache": { + "ordered": true, + "name": "responseFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[1]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseFromCache", + "type": "MessageBuffer" + }, + "power_model": null, + "cache_response_latency": 12, + "buffer_size": 0, + "send_evictions": false, + "cacheMemory": { + "size": 256, + "resourceStalls": false, + "is_icache": false, + "name": "cacheMemory", + "eventq_index": 0, + "dataAccessLatency": 1, + "tagArrayBanks": 1, + "tagAccessLatency": 1, + "replacement_policy": { + "name": "replacement_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "PseudoLRUPolicy", + "path": "system.ruby.l1_cntrl0.cacheMemory.replacement_policy", + "block_size": 64, + "type": "PseudoLRUReplacementPolicy", + "size": 256 + }, + "assoc": 2, + "start_index_bit": 6, + "cxx_class": "CacheMemory", + "path": "system.ruby.l1_cntrl0.cacheMemory", + "block_size": 0, + "type": "RubyCache", + "dataArrayBanks": 1, + "ruby_system": "system.ruby" + }, + "ruby_system": "system.ruby", + "name": "l1_cntrl0", + "p_state_clk_gate_bins": 20, + "mandatoryQueue": { + "ordered": false, + "name": "mandatoryQueue", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.mandatoryQueue", + "type": "MessageBuffer" + }, + "path": "system.ruby.l1_cntrl0" + }, + "network": { + "int_link_buffers": [ + { + "ordered": true, + "name": "int_link_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": 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"peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout new file mode 100755 index 000000000..ea970ac1c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout @@ -0,0 +1,171 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:44 +gem5 executing on zizzer, pid 34093 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157E0 +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540733 +fstat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540733 +open, stat: PASS +Bytes read: 15 +String read: this is a test +open, read, unlink: PASS +times: + tms_utime = 0 + tms_stime = 0 + tms_cutime = 0 + tms_cstime = 0 +times: PASS +timeval: + tv_sec = 1000000000 + tv_usec = 3935 +gettimeofday: PASS +Cycles: 4032706 +rdcycle: PASS +Time: 1480540736 +rdtime: PASS +Instructions Retired: 215243 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 5246466 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..70b5b9855 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.005246 # Number of seconds simulated +sim_ticks 5246466 # Number of ticks simulated +final_tick 5246466 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 18477 # Simulator instruction rate (inst/s) +host_op_rate 18477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 364337 # Simulator tick rate (ticks/s) +host_mem_usage 412052 # Number of bytes of host memory used +host_seconds 14.40 # Real time elapsed on the host +sim_insts 266066 # Number of instructions simulated +sim_ops 266066 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 5073344 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 5073344 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5073088 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 5073088 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 79271 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 79271 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 79267 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 79267 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 967002169 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 967002169 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 966953374 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 966953374 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1933955543 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1933955543 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 79271 # Number of read requests accepted +system.mem_ctrls.writeReqs 79267 # Number of write requests accepted +system.mem_ctrls.readBursts 79271 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 79267 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 2666176 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 2407168 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 2784128 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 5073344 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 5073088 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 37612 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 35741 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 4161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 6493 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 322 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11183 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 1470 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 254 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 830 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 271 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 850 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 2251 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 11315 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 562 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 405 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 342 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 906 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 4421 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 6791 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 332 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 11984 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 1476 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 255 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 44 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 877 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 282 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 852 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2350 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 11612 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 563 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 405 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 350 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 908 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 5246394 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 79271 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 79267 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 41659 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 330 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 402 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2224 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 2668 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2708 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 2791 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 2963 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 2810 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 2680 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 2663 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 2661 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2661 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2660 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 15795 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 344.923330 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 229.090130 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 305.803840 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 3621 22.92% 22.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 4154 26.30% 49.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 2325 14.72% 63.94% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1784 11.29% 75.24% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 865 5.48% 80.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 706 4.47% 85.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 510 3.23% 88.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 328 2.08% 90.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1502 9.51% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 15795 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 2658 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.670429 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.605623 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.463558 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 110 4.14% 4.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1181 44.43% 48.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1114 41.91% 90.48% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 223 8.39% 98.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 29 1.09% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.04% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 2658 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 2658 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.366441 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.340186 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.970216 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2300 86.53% 86.53% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 19 0.71% 87.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 111 4.18% 91.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 179 6.73% 98.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 49 1.84% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 2658 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 835288 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 1626809 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 208295 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 20.05 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 39.05 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 508.19 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 530.67 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 967.00 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 966.95 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.12 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.97 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.15 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 26.01 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 29472 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 39888 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 70.75 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.64 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 33.09 # Average gap between requests +system.mem_ctrls.pageHitRate 81.42 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 79710960 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 43126104 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 282823968 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 218655360 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 414882000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 659598072 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10126848 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1616957760 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 62452224 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 21677280 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 3410010576 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 649.963342 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 3773570 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 6170 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 175566 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 65011 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 162636 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1291123 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 3545960 # Time in different power states +system.mem_ctrls_1.actEnergy 33108180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 17905776 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 193088448 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 144673344 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 397057440.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 650520024 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 12185088 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1517506896 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 81936768 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 62020080 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 3110002044 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 592.780368 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 3787958 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 12732 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 167990 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 246912 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 213377 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1277589 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 3327866 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 183 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 5246466 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5246466 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 266066 # Number of instructions committed +system.cpu.committedOps 266066 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 266065 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 19074 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39832 # number of instructions that are conditional controls +system.cpu.num_int_insts 266065 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 351637 # number of times the integer registers were read +system.cpu.num_int_register_writes 182516 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 106592 # number of memory refs +system.cpu.num_load_insts 62875 # Number of load instructions +system.cpu.num_store_insts 43717 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 5246466 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 58906 # Number of branches fetched +system.cpu.op_class::No_OpClass 188 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 158793 59.64% 59.71% # Class of executed instruction +system.cpu.op_class::IntMult 431 0.16% 59.87% # Class of executed instruction +system.cpu.op_class::IntDiv 246 0.09% 59.97% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::MemRead 62875 23.62% 83.58% # Class of executed instruction +system.cpu.op_class::MemWrite 43717 16.42% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 266250 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 158538 # delay histogram for all message +system.ruby.delayHist | 158538 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 158538 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 372842 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 372842 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 372842 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 372841 +system.ruby.latency_hist_seqr::mean 13.071591 +system.ruby.latency_hist_seqr::gmean 2.303358 +system.ruby.latency_hist_seqr::stdev 28.899910 +system.ruby.latency_hist_seqr | 332521 89.19% 89.19% | 37494 10.06% 99.24% | 1855 0.50% 99.74% | 376 0.10% 99.84% | 322 0.09% 99.93% | 238 0.06% 99.99% | 17 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 13 0.00% 100.00% +system.ruby.latency_hist_seqr::total 372841 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 293570 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 293570 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 293570 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 79271 +system.ruby.miss_latency_hist_seqr::mean 57.777182 +system.ruby.miss_latency_hist_seqr::gmean 50.619805 +system.ruby.miss_latency_hist_seqr::stdev 37.283085 +system.ruby.miss_latency_hist_seqr | 38951 49.14% 49.14% | 37494 47.30% 96.44% | 1855 2.34% 98.78% | 376 0.47% 99.25% | 322 0.41% 99.66% | 238 0.30% 99.96% | 17 0.02% 99.98% | 3 0.00% 99.98% | 2 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 79271 +system.ruby.Directory.incomplete_times_seqr 79270 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 293570 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 79271 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 372841 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.554514 +system.ruby.network.routers0.msg_count.Control::2 79271 +system.ruby.network.routers0.msg_count.Data::2 79267 +system.ruby.network.routers0.msg_count.Response_Data::4 79271 +system.ruby.network.routers0.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers0.msg_bytes.Control::2 634168 +system.ruby.network.routers0.msg_bytes.Data::2 5707224 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.554514 +system.ruby.network.routers1.msg_count.Control::2 79271 +system.ruby.network.routers1.msg_count.Data::2 79267 +system.ruby.network.routers1.msg_count.Response_Data::4 79271 +system.ruby.network.routers1.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers1.msg_bytes.Control::2 634168 +system.ruby.network.routers1.msg_bytes.Data::2 5707224 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.554514 +system.ruby.network.routers2.msg_count.Control::2 79271 +system.ruby.network.routers2.msg_count.Data::2 79267 +system.ruby.network.routers2.msg_count.Response_Data::4 79271 +system.ruby.network.routers2.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers2.msg_bytes.Control::2 634168 +system.ruby.network.routers2.msg_bytes.Data::2 5707224 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 237813 +system.ruby.network.msg_count.Data 237801 +system.ruby.network.msg_count.Response_Data 237813 +system.ruby.network.msg_count.Writeback_Control 237801 +system.ruby.network.msg_byte.Control 1902504 +system.ruby.network.msg_byte.Data 17121672 +system.ruby.network.msg_byte.Response_Data 17122536 +system.ruby.network.msg_byte.Writeback_Control 1902408 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.554666 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 79271 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.routers0.throttle1.link_utilization 7.554361 +system.ruby.network.routers0.throttle1.msg_count.Control::2 79271 +system.ruby.network.routers0.throttle1.msg_count.Data::2 79267 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 634168 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5707224 +system.ruby.network.routers1.throttle0.link_utilization 7.554361 +system.ruby.network.routers1.throttle0.msg_count.Control::2 79271 +system.ruby.network.routers1.throttle0.msg_count.Data::2 79267 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 634168 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 5707224 +system.ruby.network.routers1.throttle1.link_utilization 7.554666 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 79271 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.routers2.throttle0.link_utilization 7.554666 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 79271 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.routers2.throttle1.link_utilization 7.554361 +system.ruby.network.routers2.throttle1.msg_count.Control::2 79271 +system.ruby.network.routers2.throttle1.msg_count.Data::2 79267 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 634168 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5707224 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 79271 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 79271 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 79271 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 79267 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 79267 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 79267 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 62875 +system.ruby.LD.latency_hist_seqr::mean 27.680191 +system.ruby.LD.latency_hist_seqr::gmean 7.180276 +system.ruby.LD.latency_hist_seqr::stdev 35.811045 +system.ruby.LD.latency_hist_seqr | 50013 79.54% 79.54% | 11930 18.97% 98.52% | 656 1.04% 99.56% | 86 0.14% 99.70% | 110 0.17% 99.87% | 69 0.11% 99.98% | 11 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 62875 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 30585 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 30585 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 30585 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 32290 +system.ruby.LD.miss_latency_hist_seqr::mean 52.951595 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.459624 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.412980 +system.ruby.LD.miss_latency_hist_seqr | 19428 60.17% 60.17% | 11930 36.95% 97.11% | 656 2.03% 99.15% | 86 0.27% 99.41% | 110 0.34% 99.75% | 69 0.21% 99.97% | 11 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 32290 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 43716 +system.ruby.ST.latency_hist_seqr::mean 11.968158 +system.ruby.ST.latency_hist_seqr::gmean 2.425644 +system.ruby.ST.latency_hist_seqr::stdev 26.441690 +system.ruby.ST.latency_hist_seqr | 40932 93.63% 93.63% | 2520 5.76% 99.40% | 167 0.38% 99.78% | 45 0.10% 99.88% | 22 0.05% 99.93% | 18 0.04% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 2 0.00% 99.98% | 10 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 43716 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 33299 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 33299 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 33299 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 10417 +system.ruby.ST.miss_latency_hist_seqr::mean 47.028991 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.206543 +system.ruby.ST.miss_latency_hist_seqr::stdev 36.336668 +system.ruby.ST.miss_latency_hist_seqr | 7633 73.27% 73.27% | 2520 24.19% 97.47% | 167 1.60% 99.07% | 45 0.43% 99.50% | 22 0.21% 99.71% | 18 0.17% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.02% 99.90% | 10 0.10% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 10417 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 266250 +system.ruby.IFETCH.latency_hist_seqr::mean 9.802941 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.746090 +system.ruby.IFETCH.latency_hist_seqr::stdev 26.280316 +system.ruby.IFETCH.latency_hist_seqr | 241576 90.73% 90.73% | 23044 8.66% 99.39% | 1032 0.39% 99.78% | 245 0.09% 99.87% | 190 0.07% 99.94% | 151 0.06% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 266250 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 229686 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 229686 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 229686 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 36564 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.100837 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 57.898658 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.529976 +system.ruby.IFETCH.miss_latency_hist_seqr | 11890 32.52% 32.52% | 23044 63.02% 95.54% | 1032 2.82% 98.36% | 245 0.67% 99.03% | 190 0.52% 99.55% | 151 0.41% 99.97% | 6 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 36564 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 79271 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.777182 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.619805 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.283085 +system.ruby.Directory.miss_mach_latency_hist_seqr | 38951 49.14% 49.14% | 37494 47.30% 96.44% | 1855 2.34% 98.78% | 376 0.47% 99.25% | 322 0.41% 99.66% | 238 0.30% 99.96% | 17 0.02% 99.98% | 3 0.00% 99.98% | 2 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 79271 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 32290 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.951595 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.459624 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.412980 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 19428 60.17% 60.17% | 11930 36.95% 97.11% | 656 2.03% 99.15% | 86 0.27% 99.41% | 110 0.34% 99.75% | 69 0.21% 99.97% | 11 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 32290 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 10417 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 47.028991 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.206543 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 36.336668 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 7633 73.27% 73.27% | 2520 24.19% 97.47% | 167 1.60% 99.07% | 45 0.43% 99.50% | 22 0.21% 99.71% | 18 0.17% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.02% 99.90% | 10 0.10% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 10417 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 36564 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.100837 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 57.898658 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.529976 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 11890 32.52% 32.52% | 23044 63.02% 95.54% | 1032 2.82% 98.36% | 245 0.67% 99.03% | 190 0.52% 99.55% | 151 0.41% 99.97% | 6 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 36564 +system.ruby.Directory_Controller.GETX 79271 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 79267 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 79271 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 79267 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 79271 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 79267 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 79271 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 79267 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 62875 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 266250 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 43716 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 79271 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 79267 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 79267 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 32290 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 36564 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 10417 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 30585 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 229686 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 33299 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 79267 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 79267 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 68854 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 10417 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini new file mode 100644 index 000000000..eb052bbd2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json new file mode 100644 index 000000000..e14de7091 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout new file mode 100755 index 000000000..ac54effb0 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:43 +gem5 executing on zizzer, pid 34089 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157E0 +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540730 +fstat: + st_dev = 2054 + st_ino = 58196126 + st_mode = 33277 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540723 +open, stat: PASS +Bytes read: 9 +String read: Ð +open, read, unlink: [1;31mFAIL[0m (expected 1; found 0) +Exiting @ tick 352925500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt new file mode 100644 index 000000000..32254e280 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000353 # Number of seconds simulated +sim_ticks 352925500 # Number of ticks simulated +final_tick 352925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 23308 # Simulator instruction rate (inst/s) +host_op_rate 23308 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40827277 # Simulator tick rate (ticks/s) +host_mem_usage 243536 # Number of bytes of host memory used +host_seconds 8.64 # Real time elapsed on the host +sim_insts 201478 # Number of instructions simulated +sim_ops 201478 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 55168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18368 # Number of bytes read from this memory +system.physmem.bytes_read::total 73536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 55168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 55168 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1149 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 156316276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52044978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 208361255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 156316276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156316276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 156316276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52044978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 208361255 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 130 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 352925500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 705851 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 201478 # Number of instructions committed +system.cpu.committedOps 201478 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 201477 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 14627 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 30164 # number of instructions that are conditional controls +system.cpu.num_int_insts 201477 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 266871 # number of times the integer registers were read +system.cpu.num_int_register_writes 137624 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 80078 # number of memory refs +system.cpu.num_load_insts 46389 # Number of load instructions +system.cpu.num_store_insts 33689 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 705851 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 44791 # Number of branches fetched +system.cpu.op_class::No_OpClass 132 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 120936 59.99% 60.05% # Class of executed instruction +system.cpu.op_class::IntMult 297 0.15% 60.20% # Class of executed instruction +system.cpu.op_class::IntDiv 166 0.08% 60.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::MemRead 46389 23.01% 83.29% # Class of executed instruction +system.cpu.op_class::MemWrite 33689 16.71% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 201609 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 237.806291 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 79790 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 287 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 278.013937 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 237.806291 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.058058 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.058058 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 287 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.070068 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 160441 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 160441 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 46314 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46314 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 33476 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 33476 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 79790 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 79790 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 79790 # number of overall hits +system.cpu.dcache.overall_hits::total 79790 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 212 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 212 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 287 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 287 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 287 # number of overall misses +system.cpu.dcache.overall_misses::total 287 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4725000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4725000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13356000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13356000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18081000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18081000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18081000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18081000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 80077 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 80077 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 80077 # number of overall (read+write) accesses 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+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 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# mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.160093 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.160093 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1165 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 16 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 862 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 75 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 574 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2314 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 74560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1149 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1149 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 598500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1293000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 430500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1149 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 937 # Transaction distribution +system.membus.trans_dist::ReadExReq 212 # Transaction distribution +system.membus.trans_dist::ReadExResp 212 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 937 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2298 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2298 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 73536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1149 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1149 # Request fanout histogram +system.membus.reqLayer0.occupancy 1150000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 5745000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini new file mode 100644 index 000000000..778748b0c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.json new file mode 100644 index 000000000..c05fef680 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "max_insts_any_thread": 0, + "do_statistics_insts": true, + "numThreads": 1, + "fetch1LineSnapWidth": 0, + "fetch1ToFetch2BackwardDelay": 1, + "fetch1FetchLimit": 1, + "executeIssueLimit": 2, + "system": "system", + "executeLSQMaxStoreBufferStoresPerCycle": 2, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": 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"localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout new file mode 100755 index 000000000..eb07824f2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:44 +gem5 executing on zizzer, pid 34094 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 165091500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt new file mode 100644 index 000000000..4aec07287 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt @@ -0,0 +1,761 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000165 # Number of seconds simulated +sim_ticks 165091500 # Number of ticks simulated +final_tick 165091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 30601 # Simulator instruction rate (inst/s) +host_op_rate 30601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44574860 # Simulator tick rate (ticks/s) +host_mem_usage 244264 # Number of bytes of host memory used +host_seconds 3.70 # Real time elapsed on the host +sim_insts 113337 # Number of instructions simulated +sim_ops 113337 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 49984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16768 # Number of bytes read from this memory +system.physmem.bytes_read::total 66752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 781 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 262 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1043 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 302765436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 101567918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 404333355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302765436 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302765436 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302765436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 101567918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 404333355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1043 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1043 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 66752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 66752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 93 # Per bank write bursts +system.physmem.perBankRdBursts::1 5 # Per bank write bursts +system.physmem.perBankRdBursts::2 17 # Per bank write bursts +system.physmem.perBankRdBursts::3 108 # Per bank write bursts +system.physmem.perBankRdBursts::4 59 # Per bank write bursts +system.physmem.perBankRdBursts::5 95 # Per bank write bursts +system.physmem.perBankRdBursts::6 66 # Per bank write bursts +system.physmem.perBankRdBursts::7 26 # Per bank write bursts +system.physmem.perBankRdBursts::8 58 # Per bank write bursts +system.physmem.perBankRdBursts::9 78 # Per bank write bursts +system.physmem.perBankRdBursts::10 82 # Per bank write bursts +system.physmem.perBankRdBursts::11 51 # Per bank write bursts +system.physmem.perBankRdBursts::12 133 # Per bank write bursts +system.physmem.perBankRdBursts::13 67 # Per bank write bursts +system.physmem.perBankRdBursts::14 98 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 164764000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1043 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What 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+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 209 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.956938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.620752 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 291.549711 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 58 27.75% 27.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 50 23.92% 51.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39 18.66% 70.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19 9.09% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9 4.31% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 3.83% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 2.87% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.44% 91.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17 8.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation +system.physmem.totQLat 16657750 # Total ticks spent queuing +system.physmem.totMemAccLat 36214000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15971.00 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 34721.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 404.33 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 404.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.16 # Data bus utilization in percentage +system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 829 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 157971.24 # Average gap between requests +system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 778260 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 409860 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3348660 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9067560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 480480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 54701760 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6869760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 2569980 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 91748400 # Total energy per rank (pJ) +system.physmem_0.averagePower 555.739358 # Core power per rank (mW) +system.physmem_0.totalIdleTime 143461250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 642000 # Time in different power states +system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 6106000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 17892500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14770000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 119949000 # Time in different power states +system.physmem_1.actEnergy 749700 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 383295 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4098360 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 9572580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 409440 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 46964580 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 13642080 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 1635840 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 90363315 # Total energy per rank (pJ) +system.physmem_1.averagePower 547.349607 # Core power per rank (mW) +system.physmem_1.totalIdleTime 142759500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 477500 # Time in different power states +system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 4514500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 35521500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16091750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 103014250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 31704 # Number of BP lookups +system.cpu.branchPred.condPredicted 20239 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 27881 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15332 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 54.990854 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 5600 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3678 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1922 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1024 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 165091500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 330183 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113337 # Number of instructions committed +system.cpu.committedOps 113337 # Number of ops (including micro ops) committed +system.cpu.discardedOps 5814 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.913285 # CPI: cycles per instruction +system.cpu.ipc 0.343255 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 45 0.04% 0.04% # Class of committed instruction +system.cpu.op_class_0::IntAlu 69651 61.45% 61.49% # Class of committed instruction +system.cpu.op_class_0::IntMult 122 0.11% 61.60% # Class of committed instruction +system.cpu.op_class_0::IntDiv 26 0.02% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::MemRead 23780 20.98% 82.61% # Class of committed instruction +system.cpu.op_class_0::MemWrite 19713 17.39% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 113337 # Class of committed instruction +system.cpu.tickCycles 171254 # Number of cycles that the object actually ticked +system.cpu.idleCycles 158929 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 213.474286 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43868 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 263 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.798479 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 213.474286 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052118 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 263 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.064209 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88905 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88905 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 24540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19328 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19328 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 43868 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 43868 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 43868 # number of overall hits +system.cpu.dcache.overall_hits::total 43868 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 69 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 69 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 453 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 453 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 453 # number of overall misses +system.cpu.dcache.overall_misses::total 453 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7586500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7586500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31133500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31133500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38720000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38720000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38720000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38720000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 44321 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44321 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44321 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44321 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002804 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002804 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019481 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019481 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010221 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010221 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010221 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010221 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 109949.275362 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 109949.275362 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81076.822917 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81076.822917 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85474.613687 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85474.613687 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 186 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 186 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 190 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 190 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 190 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 190 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 198 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 198 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 263 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 263 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16117500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16117500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23239000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23239000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23239000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23239000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002641 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002641 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010045 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010045 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005934 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005934 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 109561.538462 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 109561.538462 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81401.515152 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81401.515152 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 14 # number of replacements +system.cpu.icache.tags.tagsinuse 386.834879 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49717 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 781 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63.658131 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 386.834879 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.188884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.188884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 767 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 497 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.374512 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 101777 # Number of tag accesses +system.cpu.icache.tags.data_accesses 101777 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 49717 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49717 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49717 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49717 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49717 # number of overall hits +system.cpu.icache.overall_hits::total 49717 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 781 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 781 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 781 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 781 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 781 # number of overall misses +system.cpu.icache.overall_misses::total 781 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68473000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68473000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68473000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68473000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68473000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68473000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50498 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50498 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50498 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50498 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50498 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50498 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015466 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015466 # miss rate for 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overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85668.264621 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 198 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 198 # 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198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 526 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2102 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 67712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1044 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.030949 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1043 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1044 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 543000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1171500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 394500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1043 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 845 # Transaction distribution +system.membus.trans_dist::ReadExReq 198 # Transaction distribution +system.membus.trans_dist::ReadExResp 198 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 845 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2086 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 66752 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1043 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1043 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1043 # Request fanout histogram +system.membus.reqLayer0.occupancy 1170500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 5536250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini new file mode 100644 index 000000000..aba900b27 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini @@ -0,0 +1,872 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json new file mode 100644 index 000000000..c507a1468 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json @@ -0,0 +1,1151 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + 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"cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList06", + "type": "OpDesc" + }, + { + "opClass": "SimdMultAcc", + "opLat": 1, + "name": "opList07", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList07", + "type": "OpDesc" + }, + { + "opClass": "SimdShift", + "opLat": 1, + "name": "opList08", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList08", + "type": "OpDesc" + }, + { + "opClass": "SimdShiftAcc", + "opLat": 1, + "name": "opList09", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList09", + "type": "OpDesc" + }, + { + "opClass": "SimdSqrt", + "opLat": 1, + "name": "opList10", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList10", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatAdd", + "opLat": 1, + "name": "opList11", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList11", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatAlu", + "opLat": 1, + "name": "opList12", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList12", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCmp", + "opLat": 1, + "name": "opList13", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList13", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCvt", + "opLat": 1, + "name": "opList14", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList14", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatDiv", + "opLat": 1, + "name": "opList15", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList15", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMisc", + "opLat": 1, + "name": "opList16", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList16", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMult", + "opLat": 1, + "name": "opList17", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList17", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMultAcc", + "opLat": 1, + "name": "opList18", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList18", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatSqrt", + "opLat": 1, + "name": "opList19", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList19", + "type": "OpDesc" + } + ], + "name": "FUList5", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList5", + "type": "FUDesc" + }, + { + "count": 0, + "opList": [ + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList1", + "type": "OpDesc" + } + ], + "name": "FUList6", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList6", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList0", + "type": "OpDesc" + }, + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList3", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout new file mode 100755 index 000000000..0c05eb2fe --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:44 +gem5 executing on zizzer, pid 34095 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 66726000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt new file mode 100644 index 000000000..0be26640f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt @@ -0,0 +1,1006 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000067 # Number of seconds simulated +sim_ticks 66726000 # Number of ticks simulated +final_tick 66726000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 30660 # Simulator instruction rate (inst/s) +host_op_rate 30660 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18058105 # Simulator tick rate (ticks/s) +host_mem_usage 245440 # Number of bytes of host memory used +host_seconds 3.70 # Real time elapsed on the host +sim_insts 113291 # Number of instructions simulated +sim_ops 113291 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16960 # Number of bytes read from this memory +system.physmem.bytes_read::total 66432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 265 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1038 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 741420136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 254173785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 995593921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 741420136 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 741420136 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 741420136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 254173785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 995593921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1039 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1039 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 66496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 66496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 89 # Per bank write bursts +system.physmem.perBankRdBursts::1 8 # Per bank write bursts +system.physmem.perBankRdBursts::2 16 # Per bank write bursts +system.physmem.perBankRdBursts::3 108 # Per bank write bursts +system.physmem.perBankRdBursts::4 64 # Per bank write bursts +system.physmem.perBankRdBursts::5 91 # Per bank write bursts +system.physmem.perBankRdBursts::6 61 # Per bank write bursts +system.physmem.perBankRdBursts::7 30 # Per bank write bursts +system.physmem.perBankRdBursts::8 56 # Per bank write bursts +system.physmem.perBankRdBursts::9 76 # Per bank write bursts +system.physmem.perBankRdBursts::10 79 # Per bank write bursts +system.physmem.perBankRdBursts::11 53 # Per bank write bursts +system.physmem.perBankRdBursts::12 133 # Per bank write bursts +system.physmem.perBankRdBursts::13 64 # Per bank write bursts +system.physmem.perBankRdBursts::14 104 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 66707000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1039 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.131707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.178317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.046077 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 71 34.63% 34.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 47 22.93% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 29 14.15% 71.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 5.37% 77.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 11 5.37% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 2.93% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.46% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 2.44% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22 10.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 205 # Bytes accessed per row activation +system.physmem.totQLat 13576000 # Total ticks spent queuing +system.physmem.totMemAccLat 33057250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13066.41 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31816.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 996.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 996.55 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 7.79 # Data bus utilization in percentage +system.physmem.busUtilRead 7.79 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 821 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 64203.08 # Average gap between requests +system.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 835380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 413655 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3334380 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6568110 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 113280 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 22288140 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1209600 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 39679665 # Total energy per rank (pJ) +system.physmem_0.averagePower 594.663495 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51714500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 59500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2080000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 3148750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 12569500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 48868250 # Time in different power states +system.physmem_1.actEnergy 721140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 364320 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4084080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6353220 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 143040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 20623170 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 2762880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 39968970 # Total energy per rank (pJ) +system.physmem_1.averagePower 598.999194 # Core power per rank (mW) +system.physmem_1.totalIdleTime 52416000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 150500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2080000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 7195250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 12079500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 45220750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 39966 # Number of BP lookups +system.cpu.branchPred.condPredicted 24999 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2671 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 33955 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19441 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 57.255191 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7662 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3924 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3738 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1190 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 66726000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 133453 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 32838 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 168786 # Number of instructions fetch has processed +system.cpu.fetch.Branches 39966 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23365 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 44071 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5482 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 181 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22322 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.101053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.833149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 43916 54.67% 54.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3396 4.23% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6102 7.60% 66.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5424 6.75% 73.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2470 3.07% 76.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6562 8.17% 84.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1937 2.41% 86.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1614 2.01% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8913 11.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 80334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.299476 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.264760 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33037 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11879 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 32363 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 923 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2132 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6308 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 640 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 154953 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1928 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2132 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34625 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3379 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1413 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31599 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7186 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 148471 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 97 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 431 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6512 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 101480 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 195404 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 195404 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 76188 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 25292 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 58 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 58 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3325 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 28879 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22638 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 630 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 137222 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 131068 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 381 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23997 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13432 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.631538 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.013515 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 38041 47.35% 47.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10252 12.76% 60.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8094 10.08% 70.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 8074 10.05% 80.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5916 7.36% 87.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4749 5.91% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3775 4.70% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1117 1.39% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 316 0.39% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80334 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 175 6.09% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1363 47.43% 53.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1336 46.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 45 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 81693 62.33% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 129 0.10% 62.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 30 0.02% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27948 21.32% 83.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21223 16.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 131068 # Type of FU issued +system.cpu.iq.rate 0.982129 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2874 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021928 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 345725 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 161326 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 125053 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 133897 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2531 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 5099 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2926 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 101 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 2132 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2287 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 246 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 137289 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 950 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 28879 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22638 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 254 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1893 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2391 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 126811 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 27146 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4257 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 47872 # number of memory reference insts executed +system.cpu.iew.exec_branches 29089 # Number of branches executed +system.cpu.iew.exec_stores 20726 # Number of stores executed +system.cpu.iew.exec_rate 0.950230 # Inst execution rate +system.cpu.iew.wb_sent 125714 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 125053 # cumulative count of insts written-back +system.cpu.iew.wb_producers 49299 # num instructions producing a value +system.cpu.iew.wb_consumers 72928 # num instructions consuming a value +system.cpu.iew.wb_rate 0.937056 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675996 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 24018 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 45 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 75915 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.492340 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.298348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42174 55.55% 55.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10802 14.23% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5429 7.15% 76.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4052 5.34% 82.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3273 4.31% 86.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3050 4.02% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2519 3.32% 93.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 909 1.20% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3707 4.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 75915 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113291 # Number of instructions committed +system.cpu.commit.committedOps 113291 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 43492 # Number of memory references committed +system.cpu.commit.loads 23780 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 25920 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 113291 # Number of committed integer instructions. +system.cpu.commit.function_calls 8529 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 69651 61.48% 61.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 122 0.11% 61.59% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 26 0.02% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 23780 20.99% 82.60% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 19712 17.40% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 113291 # Class of committed instruction +system.cpu.commit.bw_lim_events 3707 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 208932 # The number of ROB reads +system.cpu.rob.rob_writes 279096 # The number of ROB writes +system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53119 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 113291 # Number of Instructions Simulated +system.cpu.committedOps 113291 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.177966 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.177966 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848921 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848921 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 166154 # number of integer regfile reads +system.cpu.int_regfile_writes 85972 # number of integer regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 217.973737 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42393 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 265 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 159.973585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 217.973737 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.053216 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.053216 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 265 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.064697 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88473 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88473 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 24147 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24147 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18246 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18246 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 42393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42393 # number of overall hits +system.cpu.dcache.overall_hits::total 42393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 245 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 245 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1466 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1466 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1711 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1711 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1711 # number of overall misses +system.cpu.dcache.overall_misses::total 1711 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20376500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95969940 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95969940 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 116346440 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 116346440 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 116346440 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 116346440 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24392 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24392 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 44104 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44104 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44104 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44104 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.074371 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.074371 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.038795 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038795 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038795 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038795 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83169.387755 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83169.387755 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65463.806276 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65463.806276 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67999.088252 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67999.088252 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67999.088252 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67999.088252 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 63 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 175 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1269 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1269 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1444 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1444 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1444 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1444 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 197 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses 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cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56626500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19056000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 75682500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56626500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19056000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 75682500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68248.730964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68248.730964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73255.498060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73255.498060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80157.142857 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80157.142857 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73255.498060 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71370.786517 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72771.634615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73255.498060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71370.786517 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72771.634615 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 18 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 843 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 70 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 532 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2096 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 67456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 128 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1042 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001919 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043790 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1040 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1042 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 545000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1162500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 397500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1039 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 841 # Transaction distribution +system.membus.trans_dist::ReadExReq 197 # Transaction distribution +system.membus.trans_dist::ReadExResp 197 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 842 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2077 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 66432 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1039 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1039 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1039 # Request fanout histogram +system.membus.reqLayer0.occupancy 1253500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 5477500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini new file mode 100644 index 000000000..9b465ed9b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json new file mode 100644 index 000000000..56400a045 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout new file mode 100755 index 000000000..100328c9d --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:49 +gem5 executing on zizzer, pid 34098 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 56668000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt new file mode 100644 index 000000000..729707f96 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 56668000 # Number of ticks simulated +final_tick 56668000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 42634 # Simulator instruction rate (inst/s) +host_op_rate 42633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21324951 # Simulator tick rate (ticks/s) +host_mem_usage 233724 # Number of bytes of host memory used +host_seconds 2.66 # Real time elapsed on the host +sim_insts 113291 # Number of instructions simulated +sim_ops 113291 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 453348 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156046 # Number of bytes read from this memory +system.physmem.bytes_read::total 609394 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 453348 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 453348 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 110317 # Number of bytes written to this memory +system.physmem.bytes_written::total 110317 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 113337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 23780 # Number of read requests responded to by this memory +system.physmem.num_reads::total 137117 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 19712 # Number of write requests responded to by this memory +system.physmem.num_writes::total 19712 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000070587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2753688149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10753758735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000070587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000070587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1946724783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1946724783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000070587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4700412931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12700483518 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 56668000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 113337 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113291 # Number of instructions committed +system.cpu.committedOps 113291 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8529 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls +system.cpu.num_int_insts 113292 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 151096 # number of times the integer registers were read +system.cpu.num_int_register_writes 76188 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 43493 # number of memory refs +system.cpu.num_load_insts 23780 # Number of load instructions +system.cpu.num_store_insts 19713 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 113337 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25920 # Number of branches fetched +system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction +system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction +system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction +system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 113337 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 137117 # Transaction distribution +system.membus.trans_dist::ReadResp 137117 # Transaction distribution +system.membus.trans_dist::WriteReq 19712 # Transaction distribution +system.membus.trans_dist::WriteResp 19712 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 226674 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 86984 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 313658 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 453348 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 266363 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 719711 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 156829 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 156829 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 156829 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini new file mode 100644 index 000000000..2d0e2ebad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue 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int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 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+dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 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+type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] 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+ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json new file mode 100644 index 000000000..491401e32 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": "SLAVE" + }, + "name": "sys_port_proxy", + "p_state_clk_gate_min": 1, + "no_retry_on_stall": false, + "p_state_clk_gate_bins": 20, + "support_data_reqs": true, + "cxx_class": "RubyPortProxy", + "clk_domain": "system.clk_domain", + "power_model": null, + "is_cpu_sequencer": true, + "version": 0, + "eventq_index": 0, + "using_ruby_tester": false, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.sys_port_proxy", + "type": "RubyPortProxy", + "ruby_system": "system.ruby" + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "ruby": { + "all_instructions": false, + "memory_size_bits": 48, + "cxx_class": "RubySystem", + "l1_cntrl0": { + "requestFromCache": { + "ordered": true, + "name": "requestFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[0]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.requestFromCache", + "type": "MessageBuffer" + }, + "cxx_class": "L1Cache_Controller", + "forwardToCache": { + "ordered": true, + "name": "forwardToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[0]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.forwardToCache", + "type": "MessageBuffer" + }, + "system": "system", + "cluster_id": 0, + "sequencer": { + "no_retry_on_stall": false, + "deadlock_threshold": 500000, + "using_ruby_tester": false, + "system": "system", + "dcache": "system.ruby.l1_cntrl0.cacheMemory", + "cxx_class": "Sequencer", + "garnet_standalone": false, + "clk_domain": "system.cpu.clk_domain", + "icache_hit_latency": 1, + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "type": "RubySequencer", + "icache": "system.ruby.l1_cntrl0.cacheMemory", + "slave": { + "peer": [ + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "power_model": null, + "coreid": 99, + "path": "system.ruby.l1_cntrl0.sequencer", + "ruby_system": "system.ruby", + "support_inst_reqs": true, + "name": "sequencer", + "max_outstanding_requests": 16, + "p_state_clk_gate_bins": 20, + "dcache_hit_latency": 1, + "support_data_reqs": true, + "is_cpu_sequencer": true + }, + "type": "L1Cache_Controller", + "issue_latency": 2, + "recycle_latency": 10, + "clk_domain": "system.cpu.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "number_of_TBEs": 256, + "p_state_clk_gate_min": 1, + "responseToCache": { + "ordered": true, + "name": "responseToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[1]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseToCache", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "responseFromCache": { + "ordered": true, + "name": "responseFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[1]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseFromCache", + "type": "MessageBuffer" + }, + "power_model": null, + "cache_response_latency": 12, + "buffer_size": 0, + "send_evictions": false, + "cacheMemory": { + "size": 256, + "resourceStalls": false, + "is_icache": false, + "name": "cacheMemory", + "eventq_index": 0, + "dataAccessLatency": 1, + "tagArrayBanks": 1, + "tagAccessLatency": 1, + "replacement_policy": { + "name": "replacement_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "PseudoLRUPolicy", + "path": "system.ruby.l1_cntrl0.cacheMemory.replacement_policy", + "block_size": 64, + "type": "PseudoLRUReplacementPolicy", + "size": 256 + }, + "assoc": 2, + "start_index_bit": 6, + "cxx_class": "CacheMemory", + "path": "system.ruby.l1_cntrl0.cacheMemory", + "block_size": 0, + "type": "RubyCache", + "dataArrayBanks": 1, + "ruby_system": "system.ruby" + }, + "ruby_system": "system.ruby", + "name": "l1_cntrl0", + "p_state_clk_gate_bins": 20, + "mandatoryQueue": { + "ordered": false, + "name": "mandatoryQueue", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.mandatoryQueue", + "type": "MessageBuffer" + }, + "path": "system.ruby.l1_cntrl0" + }, + "network": { + "int_link_buffers": [ + { + "ordered": true, + "name": "int_link_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": 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"max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout new file mode 100755 index 000000000..81d54f27f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:53 +gem5 executing on zizzer, pid 34103 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 1841805 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..bf416790e --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.001842 # Number of seconds simulated +sim_ticks 1841805 # Number of ticks simulated +final_tick 1841805 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 30529 # Simulator instruction rate (inst/s) +host_op_rate 30529 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 496310 # Simulator tick rate (ticks/s) +host_mem_usage 411128 # Number of bytes of host memory used +host_seconds 3.71 # Real time elapsed on the host +sim_insts 113291 # Number of instructions simulated +sim_ops 113291 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 1901888 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1901888 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 1901632 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 1901632 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 29717 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 29717 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 29713 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 29713 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1032621803 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1032621803 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1032482809 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1032482809 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2065104612 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2065104612 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 29717 # Number of read requests accepted +system.mem_ctrls.writeReqs 29713 # Number of write requests accepted +system.mem_ctrls.readBursts 29717 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 29713 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 810816 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 1091072 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 842496 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1901888 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 1901632 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 17048 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 16517 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 1366 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 3 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 241 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 400 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 244 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 371 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 334 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 67 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 341 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 2380 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1301 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1236 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1592 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 483 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 2223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 87 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 1405 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 241 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 412 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 257 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 383 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 346 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 69 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 351 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 2448 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 1316 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 1275 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 1634 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 505 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 2424 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 95 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 1841733 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 29717 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 29713 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 12669 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What 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does an incoming req see +system.mem_ctrls.wrQLenPdf::18 812 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 810 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 826 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 868 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 857 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 811 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 807 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 805 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 4235 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 390.135537 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 255.090286 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 338.320461 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 828 19.55% 19.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 1136 26.82% 46.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 580 13.70% 60.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 361 8.52% 68.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 278 6.56% 75.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 169 3.99% 79.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 146 3.45% 82.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 150 3.54% 86.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 587 13.86% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 4235 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 805 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.719255 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.645655 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.595450 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 50 6.21% 6.21% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 309 38.39% 44.60% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 373 46.34% 90.93% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 65 8.07% 99.01% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 7 0.87% 99.88% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.12% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 805 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 805 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.352795 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.329834 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.903150 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 691 85.84% 85.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 4 0.50% 86.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 56 6.96% 93.29% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 48 5.96% 99.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 6 0.75% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 805 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 239535 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 480246 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 63345 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 18.91 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 37.91 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 440.23 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 457.43 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1032.62 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1032.48 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 7.01 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.44 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.57 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.93 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 9468 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 12124 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 74.73 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.88 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 30.99 # Average gap between requests +system.mem_ctrls.pageHitRate 83.48 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 10074540 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 5448240 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 34569024 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 26024832 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 127230480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 197709288 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3259392 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 446690304 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 61497984 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 65163360 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 977667444 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 530.820279 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 1399707 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 2653 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 53850 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 260009 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 160151 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 385558 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 979584 # Time in different power states +system.mem_ctrls_1.actEnergy 20206200 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 10915800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 110161632 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 83920896 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 145055040.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 217978032 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3880704 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 529686864 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 51989376 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 18024480 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 1191819024 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 647.092946 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 1353468 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 3236 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 61408 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 56694 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 135389 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 423484 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 1161594 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1841805 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1841805 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113291 # Number of instructions committed +system.cpu.committedOps 113291 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8529 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls +system.cpu.num_int_insts 113292 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 151096 # number of times the integer registers were read +system.cpu.num_int_register_writes 76188 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 43493 # number of memory refs +system.cpu.num_load_insts 23780 # Number of load instructions +system.cpu.num_store_insts 19713 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1841805 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25920 # Number of branches fetched +system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction +system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction +system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction +system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 113337 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 59430 # delay histogram for all message +system.ruby.delayHist | 59430 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 59430 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 156830 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 156830 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 156830 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 156829 +system.ruby.latency_hist_seqr::mean 10.744033 +system.ruby.latency_hist_seqr::gmean 2.067079 +system.ruby.latency_hist_seqr::stdev 25.213617 +system.ruby.latency_hist_seqr | 144536 92.16% 92.16% | 11426 7.29% 99.45% | 606 0.39% 99.83% | 87 0.06% 99.89% | 95 0.06% 99.95% | 65 0.04% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 0 0.00% 99.99% | 10 0.01% 100.00% +system.ruby.latency_hist_seqr::total 156829 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 127112 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 127112 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 127112 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 29717 +system.ruby.miss_latency_hist_seqr::mean 52.423327 +system.ruby.miss_latency_hist_seqr::gmean 46.160524 +system.ruby.miss_latency_hist_seqr::stdev 34.809845 +system.ruby.miss_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00% +system.ruby.miss_latency_hist_seqr::total 29717 +system.ruby.Directory.incomplete_times_seqr 29716 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 127112 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 29717 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 156829 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 8.066815 +system.ruby.network.routers0.msg_count.Control::2 29717 +system.ruby.network.routers0.msg_count.Data::2 29713 +system.ruby.network.routers0.msg_count.Response_Data::4 29717 +system.ruby.network.routers0.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers0.msg_bytes.Control::2 237736 +system.ruby.network.routers0.msg_bytes.Data::2 2139336 +system.ruby.network.routers0.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 8.066815 +system.ruby.network.routers1.msg_count.Control::2 29717 +system.ruby.network.routers1.msg_count.Data::2 29713 +system.ruby.network.routers1.msg_count.Response_Data::4 29717 +system.ruby.network.routers1.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers1.msg_bytes.Control::2 237736 +system.ruby.network.routers1.msg_bytes.Data::2 2139336 +system.ruby.network.routers1.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 8.066815 +system.ruby.network.routers2.msg_count.Control::2 29717 +system.ruby.network.routers2.msg_count.Data::2 29713 +system.ruby.network.routers2.msg_count.Response_Data::4 29717 +system.ruby.network.routers2.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers2.msg_bytes.Control::2 237736 +system.ruby.network.routers2.msg_bytes.Data::2 2139336 +system.ruby.network.routers2.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 89151 +system.ruby.network.msg_count.Data 89139 +system.ruby.network.msg_count.Response_Data 89151 +system.ruby.network.msg_count.Writeback_Control 89139 +system.ruby.network.msg_byte.Control 713208 +system.ruby.network.msg_byte.Data 6418008 +system.ruby.network.msg_byte.Response_Data 6418872 +system.ruby.network.msg_byte.Writeback_Control 713112 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 8.067249 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 29717 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers0.throttle1.link_utilization 8.066381 +system.ruby.network.routers0.throttle1.msg_count.Control::2 29717 +system.ruby.network.routers0.throttle1.msg_count.Data::2 29713 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 237736 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 2139336 +system.ruby.network.routers1.throttle0.link_utilization 8.066381 +system.ruby.network.routers1.throttle0.msg_count.Control::2 29717 +system.ruby.network.routers1.throttle0.msg_count.Data::2 29713 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 237736 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 2139336 +system.ruby.network.routers1.throttle1.link_utilization 8.067249 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 29717 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers2.throttle0.link_utilization 8.067249 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 29717 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers2.throttle1.link_utilization 8.066381 +system.ruby.network.routers2.throttle1.msg_count.Control::2 29717 +system.ruby.network.routers2.throttle1.msg_count.Data::2 29713 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 237736 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 2139336 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 29717 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 29717 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 29717 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 29713 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 29713 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 29713 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 23780 +system.ruby.LD.latency_hist_seqr::mean 23.543860 +system.ruby.LD.latency_hist_seqr::gmean 5.728326 +system.ruby.LD.latency_hist_seqr::stdev 33.566569 +system.ruby.LD.latency_hist_seqr | 19950 83.89% 83.89% | 3533 14.86% 98.75% | 205 0.86% 99.61% | 27 0.11% 99.73% | 36 0.15% 99.88% | 25 0.11% 99.98% | 0 0.00% 99.98% | 2 0.01% 99.99% | 0 0.00% 99.99% | 2 0.01% 100.00% +system.ruby.LD.latency_hist_seqr::total 23780 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 12809 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 12809 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 12809 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 10971 +system.ruby.LD.miss_latency_hist_seqr::mean 49.864552 +system.ruby.LD.miss_latency_hist_seqr::gmean 43.959200 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.000652 +system.ruby.LD.miss_latency_hist_seqr | 7141 65.09% 65.09% | 3533 32.20% 97.29% | 205 1.87% 99.16% | 27 0.25% 99.41% | 36 0.33% 99.74% | 25 0.23% 99.96% | 0 0.00% 99.96% | 2 0.02% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 10971 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 19712 +system.ruby.ST.latency_hist_seqr::mean 12.481128 +system.ruby.ST.latency_hist_seqr::gmean 2.637325 +system.ruby.ST.latency_hist_seqr::stdev 25.900228 +system.ruby.ST.latency_hist_seqr | 18468 93.69% 93.69% | 1151 5.84% 99.53% | 59 0.30% 99.83% | 14 0.07% 99.90% | 7 0.04% 99.93% | 6 0.03% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 7 0.04% 100.00% +system.ruby.ST.latency_hist_seqr::total 19712 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 14522 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 14522 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 14522 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 5190 +system.ruby.ST.miss_latency_hist_seqr::mean 44.606166 +system.ruby.ST.miss_latency_hist_seqr::gmean 39.775024 +system.ruby.ST.miss_latency_hist_seqr::stdev 33.868458 +system.ruby.ST.miss_latency_hist_seqr | 3946 76.03% 76.03% | 1151 22.18% 98.21% | 59 1.14% 99.34% | 14 0.27% 99.61% | 7 0.13% 99.75% | 6 0.12% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 7 0.13% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 5190 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 113337 +system.ruby.IFETCH.latency_hist_seqr::mean 7.756293 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.599835 +system.ruby.IFETCH.latency_hist_seqr::stdev 21.972545 +system.ruby.IFETCH.latency_hist_seqr | 106118 93.63% 93.63% | 6742 5.95% 99.58% | 342 0.30% 99.88% | 46 0.04% 99.92% | 52 0.05% 99.97% | 34 0.03% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 113337 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 99781 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 99781 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 99781 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 13556 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 57.487017 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.839427 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.033938 +system.ruby.IFETCH.miss_latency_hist_seqr | 6337 46.75% 46.75% | 6742 49.73% 96.48% | 342 2.52% 99.00% | 46 0.34% 99.34% | 52 0.38% 99.73% | 34 0.25% 99.98% | 1 0.01% 99.99% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 13556 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 29717 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 52.423327 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 46.160524 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.809845 +system.ruby.Directory.miss_mach_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 29717 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 10971 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 49.864552 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 43.959200 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.000652 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 7141 65.09% 65.09% | 3533 32.20% 97.29% | 205 1.87% 99.16% | 27 0.25% 99.41% | 36 0.33% 99.74% | 25 0.23% 99.96% | 0 0.00% 99.96% | 2 0.02% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 10971 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 5190 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 44.606166 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 39.775024 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.868458 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 3946 76.03% 76.03% | 1151 22.18% 98.21% | 59 1.14% 99.34% | 14 0.27% 99.61% | 7 0.13% 99.75% | 6 0.12% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 7 0.13% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 5190 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 13556 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 57.487017 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.839427 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.033938 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 6337 46.75% 46.75% | 6742 49.73% 96.48% | 342 2.52% 99.00% | 46 0.34% 99.34% | 52 0.38% 99.73% | 34 0.25% 99.98% | 1 0.01% 99.99% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 13556 +system.ruby.Directory_Controller.GETX 29717 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 29713 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 29717 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 29713 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 29717 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 29713 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 29717 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 29713 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 23780 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 113337 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 19712 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 29717 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 29713 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 29713 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 10971 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 13556 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 5190 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 12809 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 99781 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 14522 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 29713 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 29713 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 24527 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 5190 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini new file mode 100644 index 000000000..4d0cc1f98 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json new file mode 100644 index 000000000..70b4bf86d --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + 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"eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout new file mode 100755 index 000000000..7cb72814c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:50 +gem5 executing on zizzer, pid 34099 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 209715500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt new file mode 100644 index 000000000..a860f5326 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000210 # Number of seconds simulated +sim_ticks 209715500 # Number of ticks simulated +final_tick 209715500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 42175 # Simulator instruction rate (inst/s) +host_op_rate 42174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78069260 # Simulator tick rate (ticks/s) +host_mem_usage 242960 # Number of bytes of host memory used +host_seconds 2.69 # Real time elapsed on the host +sim_insts 113291 # Number of instructions simulated +sim_ops 113291 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 37952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16640 # Number of bytes read from this memory +system.physmem.bytes_read::total 54592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 37952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 37952 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 260 # Number of read requests responded to by this memory +system.physmem.num_reads::total 853 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 180968979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 79345590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 260314569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 180968979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 180968979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 180968979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 79345590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 260314569 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 209715500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 419431 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113291 # Number of instructions committed +system.cpu.committedOps 113291 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8529 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls +system.cpu.num_int_insts 113292 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 151096 # number of times the integer registers were read +system.cpu.num_int_register_writes 76188 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 43493 # number of memory refs +system.cpu.num_load_insts 23780 # Number of load instructions +system.cpu.num_store_insts 19713 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 419431 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25920 # Number of branches fetched +system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction +system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction +system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction +system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 113337 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 215.473039 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43232 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 260 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.276923 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 215.473039 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052606 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052606 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 260 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.063477 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 87244 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87244 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23719 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23719 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19513 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19513 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 43232 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 43232 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 43232 # number of overall hits +system.cpu.dcache.overall_hits::total 43232 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 199 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 199 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 260 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 260 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 260 # number of overall misses +system.cpu.dcache.overall_misses::total 260 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3843000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3843000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12537000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12537000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16380000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16380000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16380000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16380000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23780 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23780 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43492 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43492 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43492 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43492 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002565 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002565 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010095 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005978 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005978 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005978 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005978 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 260 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 260 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3782000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3782000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12338000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12338000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16120000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16120000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16120000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16120000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002565 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002565 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010095 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010095 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005978 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005978 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005978 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005978 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 6 # number of replacements +system.cpu.icache.tags.tagsinuse 302.746737 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 112745 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 593 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 190.126476 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 302.746737 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.147826 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.147826 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 587 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 229 # 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Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 6 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 199 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 199 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 593 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 593 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 593 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 260 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 853 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 593 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 43077000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29947000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13130000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 43077000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.843170 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.843170 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.843170 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.586166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.843170 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.586166 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 859 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 520 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1712 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 54976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 853 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 853 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 853 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 435500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 889500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 390000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 853 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 654 # Transaction distribution +system.membus.trans_dist::ReadExReq 199 # Transaction distribution +system.membus.trans_dist::ReadExResp 199 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 654 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1706 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 54592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 853 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 853 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 853 # Request fanout histogram +system.membus.reqLayer0.occupancy 853500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4265000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |