diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
| commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
| tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt | |
| parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
| download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz | |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt | 512 |
1 files changed, 256 insertions, 256 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 9c26db577..165716ee5 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24110500 # Number of ticks simulated -final_tick 24110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 22522500 # Number of ticks simulated +final_tick 22522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94813 # Simulator instruction rate (inst/s) -host_op_rate 94805 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 150747979 # Simulator tick rate (ticks/s) -host_mem_usage 222632 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 65265 # Simulator instruction rate (inst/s) +host_op_rate 65259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96930117 # Simulator tick rate (ticks/s) +host_mem_usage 222888 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 791024657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 366313432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1157338089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 791024657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 791024657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 791024657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 366313432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1157338089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 846797647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 392141192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1238938839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 846797647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 846797647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 846797647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 392141192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1238938839 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24077000 # Total gap between requests +system.physmem.totGap 22489000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,49 +164,49 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1670434 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11016434 # Sum of mem lat for all requests +system.physmem.totQLat 1783436 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10779436 # Sum of mem lat for all requests system.physmem.totBusLat 1744000 # Total cycles spent in databus access -system.physmem.totBankLat 7602000 # Total cycles spent in bank access -system.physmem.avgQLat 3831.27 # Average queueing delay per request -system.physmem.avgBankLat 17435.78 # Average bank access latency per request +system.physmem.totBankLat 7252000 # Total cycles spent in bank access +system.physmem.avgQLat 4090.45 # Average queueing delay per request +system.physmem.avgBankLat 16633.03 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25267.05 # Average memory access latency -system.physmem.avgRdBW 1157.34 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24723.48 # Average memory access latency +system.physmem.avgRdBW 1238.94 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1157.34 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1238.94 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.23 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.46 # Average read queue length over time +system.physmem.busUtil 7.74 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.48 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 359 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 55222.48 # Average gap between requests +system.physmem.avgGap 51580.28 # Average gap between requests system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 48222 # number of cpu cycles simulated +system.cpu.numCycles 45046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 5021 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 3412 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 5017 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 3408 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 3518 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 2142 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 3514 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2140 # Number of BTB hits system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 60.886868 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 2318 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2703 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 14367 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 60.899260 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 2316 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 2701 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 14466 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 25466 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 25565 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 5027 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3931 # Number of Address Generations +system.cpu.regfile_manager.regForwards 4899 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3932 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 1367 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 948 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 2315 # Number of Branches Incorrectly Predicted @@ -216,12 +216,12 @@ system.cpu.execution_unit.executions 11058 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 22133 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21840 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30866 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17356 # Number of cycles cpu stages are processed. -system.cpu.activity 35.991871 # Percentage of cycles cpu is active +system.cpu.timesIdled 501 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27681 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17365 # Number of cycles cpu stages are processed. +system.cpu.activity 38.549483 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -233,146 +233,146 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.180451 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 2.970980 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.180451 # CPI: Total CPI of All Threads -system.cpu.ipc 0.314421 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 2.970980 # CPI: Total CPI of All Threads +system.cpu.ipc 0.336589 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.314421 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 35090 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 27.232384 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 39034 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 19.053544 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 39406 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 18.282112 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 45338 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.980673 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38904 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 19.323131 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.336589 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 31894 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 13152 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 29.196821 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35835 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9211 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 20.447987 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 36237 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8809 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 19.555565 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 42168 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 6.389025 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35732 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9314 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 20.676642 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 166.100833 # Cycle average of tags in use -system.cpu.icache.total_refs 2586 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 171.605866 # Cycle average of tags in use +system.cpu.icache.total_refs 2584 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 8.642140 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 166.100833 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.081104 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.081104 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2586 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2586 # number of overall hits -system.cpu.icache.overall_hits::total 2586 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses -system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18278500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18278500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18278500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18278500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18278500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18278500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2955 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2955 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2955 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124873 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124873 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124873 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49535.230352 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49535.230352 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49535.230352 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49535.230352 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 171.605866 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.083792 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.083792 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2584 # number of overall hits +system.cpu.icache.overall_hits::total 2584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 372 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 372 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 372 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 372 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 372 # number of overall misses +system.cpu.icache.overall_misses::total 372 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18064500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18064500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18064500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18064500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18064500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18064500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2956 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2956 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2956 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2956 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.125846 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.125846 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.125846 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.125846 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.125846 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.125846 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48560.483871 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48560.483871 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48560.483871 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48560.483871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48560.483871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48560.483871 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 85 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 42.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14783500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14783500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49114.617940 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49114.617940 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49114.617940 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49114.617940 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49114.617940 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49114.617940 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14600500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14600500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14600500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14600500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14600500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14600500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101827 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.101827 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.101827 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48506.644518 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48506.644518 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48506.644518 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48506.644518 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48506.644518 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48506.644518 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.064476 # Cycle average of tags in use -system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 99.150895 # Cycle average of tags in use +system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.064476 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023697 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023697 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 99.150895 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024207 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024207 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1141 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3308 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3308 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3308 # number of overall hits -system.cpu.dcache.overall_hits::total 3308 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 3187 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3187 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3187 # number of overall hits +system.cpu.dcache.overall_hits::total 3187 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 359 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses -system.cpu.dcache.overall_misses::total 359 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3241000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3241000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14317500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14317500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17558500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17558500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17558500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17558500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 422 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 422 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses +system.cpu.dcache.overall_misses::total 480 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3300500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19262500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19262500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22563000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22563000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22563000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22563000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -385,36 +385,36 @@ system.cpu.dcache.overall_accesses::cpu.data 3667 system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208738 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.208738 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097900 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55879.310345 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55879.310345 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47566.445183 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47566.445183 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48909.470752 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48909.470752 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48909.470752 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48909.470752 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3701 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 82.244444 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292649 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292649 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56905.172414 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56905.172414 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45645.734597 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45645.734597 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47006.250000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47006.250000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47006.250000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47006.250000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 680 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 216 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 221 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 221 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 221 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 337 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 337 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 342 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 342 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 342 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses @@ -423,14 +423,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2840500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2840500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4329000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4329000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7169500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7169500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4513000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4513000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7413000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7413000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7413000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7413000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -439,26 +439,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53594.339623 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53594.339623 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50929.411765 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50929.411765 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51952.898551 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51952.898551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54716.981132 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54716.981132 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53094.117647 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53094.117647 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 196.769171 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 202.986818 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 165.497362 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.271809 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005051 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006005 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 170.969481 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.017336 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005218 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000977 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006195 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -476,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14500500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17286500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4241500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4241500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14500500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7027500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21528000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14500500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7027500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21528000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14317500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2845500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17163000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4425000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4425000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14317500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7270500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21588000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14317500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7270500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21588000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -509,17 +509,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48496.655518 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49109.375000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49900 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49900 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50923.913043 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49263.157895 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50923.913043 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49263.157895 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47884.615385 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53688.679245 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48758.522727 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52058.823529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52058.823529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49400.457666 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49400.457666 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -539,17 +539,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10728482 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2122568 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12851050 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166632 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166632 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10728482 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5289200 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16017682 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10728482 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5289200 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16017682 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547482 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12729050 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547482 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16111114 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547482 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16111114 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -561,17 +561,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35881.210702 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40048.452830 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36508.664773 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37254.494118 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37254.494118 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35275.859532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36162.073864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |