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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-11-16 05:08:57 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-11-16 05:08:57 -0600 |
| commit | de489e1997ee6c37aaf6e876e32622f6c648fe95 (patch) | |
| tree | 40d4093453491b007167c971ebbb18c8ae0b77fa /tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout | |
| parent | 08cec03f8ec3bc427700343a7bd7d216433f93fc (diff) | |
| download | gem5-de489e1997ee6c37aaf6e876e32622f6c648fe95.tar.xz | |
stats: updates due to recent chagnesets
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout')
| -rwxr-xr-x | tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 81d821c63..24428b019 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 08:08:31 -gem5 started Apr 22 2015 08:14:03 -gem5 executing on phenom -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing +gem5 compiled Nov 15 2015 15:07:43 +gem5 started Nov 15 2015 15:08:27 +gem5 executing on ribera.cs.wisc.edu, pid 7788 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -19,4 +21,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 27482500 because target called exit() +Exiting @ tick 26944000 because target called exit() |