all: Update stats for memory per master and total fix.

1 files changed, 65 insertions, 14 deletions

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 693d12ddb..a887522dd 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    19744500                       # Number of ticks simulated
 final_tick                                   19744500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  52427                       # Simulator instruction rate (inst/s)
-host_op_rate                                    52424                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               71633039                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221536                       # Number of bytes of host memory used
-host_seconds                                     0.28                       # Real time elapsed on the host
+host_inst_rate                                  74885                       # Simulator instruction rate (inst/s)
+host_op_rate                                    74878                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              102311932                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222004                       # Number of bytes of host memory used
+host_seconds                                     0.19                       # Real time elapsed on the host
 sim_insts                                       14449                       # Number of instructions simulated
 sim_ops                                         14449                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       30976                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  21632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          484                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     1568841956                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1095596242                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    1568841956                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             21632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9344                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                30976                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21632                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                338                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                146                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   484                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1095596242                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            473245714                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1568841956                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1095596242                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1095596242                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1095596242                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           473245714                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1568841956                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
 system.cpu.numCycles                            39490                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -318,11 +325,17 @@ system.cpu.icache.demand_accesses::total         5506                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         5506                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         5506                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.088267                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.088267                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.088267                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.088267                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.088267                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.088267                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 34414.609053                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 34414.609053                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 34414.609053                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -350,11 +363,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     11937500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11937500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     11937500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.061751                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.061751                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.061751                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.061751                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.061751                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.061751                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                103.476464                       # Cycle average of tags in use
@@ -402,13 +421,21 @@ system.cpu.dcache.demand_accesses::total         4603                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         4603                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         4603                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037330                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.037330                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.282940                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.282940                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.114273                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.114273                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.114273                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.114273                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34682.203390                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35768.382353                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 35524.714829                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35524.714829                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -442,13 +469,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      5223000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5223000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      5223000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019930                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019930                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.057559                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031718                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.031718                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031718                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031718                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35897.590361                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35773.972603                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35773.972603                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 35773.972603                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               236.259194                       # Cycle average of tags in use
@@ -502,18 +537,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          146
 system.cpu.l2cache.overall_accesses::total          486                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.994118                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.995037                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994118                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.995885                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994118                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.995885                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.751479                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34293.017456                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34339.876033                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34339.876033                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -546,18 +589,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4576000
 system.cpu.l2cache.overall_mshr_miss_latency::total     15073000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.994118                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995037                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994118                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995885                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994118                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995885                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.034913                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31142.561983                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31142.561983                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------