diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/quick/se/02.insttest/ref/sparc/linux/o3-timing | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/o3-timing')
3 files changed, 264 insertions, 180 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 6652fe60b..a7b62ffbf 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 14970f00a..2cf0bff32 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:22 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:35 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 3a1cfc4e9..b63661760 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000018 # Nu sim_ticks 18114000 # Number of ticks simulated final_tick 18114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74785 # Simulator instruction rate (inst/s) -host_tick_rate 93746300 # Simulator tick rate (ticks/s) -host_mem_usage 213808 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 120891 # Simulator instruction rate (inst/s) +host_op_rate 120873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 151511225 # Simulator tick rate (ticks/s) +host_mem_usage 211580 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated +sim_ops 14449 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30464 # Number of bytes read from this memory system.physmem.bytes_inst_read 21120 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -234,6 +236,7 @@ system.cpu.iew.wb_rate 0.481079 # in system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions +system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted @@ -254,7 +257,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle -system.cpu.commit.count 15175 # Number of instructions committed +system.cpu.commit.committedInsts 15175 # Number of instructions committed +system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 3674 # Number of memory references committed system.cpu.commit.loads 2226 # Number of loads committed @@ -270,6 +274,7 @@ system.cpu.rob.rob_writes 43308 # Th system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated +system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads @@ -285,26 +290,39 @@ system.cpu.icache.total_refs 4151 # To system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 193.216525 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.094344 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 4151 # number of ReadReq hits -system.cpu.icache.demand_hits 4151 # number of demand (read+write) hits -system.cpu.icache.overall_hits 4151 # number of overall hits -system.cpu.icache.ReadReq_misses 457 # number of ReadReq misses -system.cpu.icache.demand_misses 457 # number of demand (read+write) misses -system.cpu.icache.overall_misses 457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15956000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15956000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15956000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4608 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4608 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.099175 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.099175 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.099175 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34914.660832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34914.660832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34914.660832 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 193.216525 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.094344 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.094344 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4151 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4151 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4151 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4151 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4151 # number of overall hits +system.cpu.icache.overall_hits::total 4151 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 457 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 457 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 457 # number of overall misses +system.cpu.icache.overall_misses::total 457 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15956000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15956000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15956000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15956000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15956000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15956000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4608 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4608 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.099175 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.099175 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.099175 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34914.660832 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -313,27 +331,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 125 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 125 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 125 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11653500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11653500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11653500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.072049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.072049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.072049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 125 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 125 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 125 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 125 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 125 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11653500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11653500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11653500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11653500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11653500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11653500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35100.903614 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use @@ -341,34 +362,53 @@ system.cpu.dcache.total_refs 3712 # To system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 102.149831 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.024939 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 2672 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.demand_hits 3706 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 3706 # number of overall hits -system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses -system.cpu.dcache.demand_misses 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3994500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 14649500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 18644000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 18644000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 2786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 4228 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 4228 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.040919 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.123463 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.123463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35716.475096 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35716.475096 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 102.149831 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024939 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024939 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2672 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2672 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 3706 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3706 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3706 # number of overall hits +system.cpu.dcache.overall_hits::total 3706 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses +system.cpu.dcache.overall_misses::total 522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3994500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3994500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14649500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14649500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18644000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18644000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18644000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18644000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 4228 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4228 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4228 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4228 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040919 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.123463 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.123463 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35039.473684 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35905.637255 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,32 +417,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2241500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2985000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5226500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5226500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.022613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.034532 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.034532 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2241500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2241500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2985000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2985000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5226500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5226500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5226500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5226500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35579.365079 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35963.855422 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35797.945205 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35797.945205 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 228.374360 # Cycle average of tags in use @@ -410,31 +456,64 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 228.374360 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006969 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 393 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 476 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 476 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 13475000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2872000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16347000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16347000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 395 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994937 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995816 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995816 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34287.531807 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34602.409639 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34342.436975 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34342.436975 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 192.484909 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 35.889452 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005874 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001095 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006969 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 330 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 393 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 330 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses +system.cpu.l2cache.overall_misses::total 476 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11308000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2167000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13475000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2872000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2872000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11308000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5039000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16347000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11308000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5039000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16347000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 332 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993976 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993976 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993976 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34266.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34396.825397 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34602.409639 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34266.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34513.698630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34266.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34513.698630 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -443,30 +522,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 393 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 476 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 476 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12215000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2608500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14823500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14823500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994937 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995816 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995816 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.424936 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31427.710843 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 393 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10246500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1968500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12215000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2608500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2608500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10246500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4577000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14823500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10246500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14823500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31427.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |