Stats: Update stats for new default L1-to-L2 bus clock and width

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

1 files changed, 60 insertions, 60 deletions

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 4464561a4..af9b5d77e 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000043                       # Number of seconds simulated
-sim_ticks                                    43106000                       # Number of ticks simulated
-final_tick                                   43106000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000041                       # Number of seconds simulated
+sim_ticks                                    41368000                       # Number of ticks simulated
+final_tick                                   41368000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 377775                       # Simulator instruction rate (inst/s)
-host_op_rate                                   377609                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1073121241                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229408                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                 652409                       # Simulator instruction rate (inst/s)
+host_op_rate                                   651936                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1777530278                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220352                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total           17792                       # Nu
 system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   416                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            412749965                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            204890270                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               617640236                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       412749965                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          412749965                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           412749965                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           204890270                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              617640236                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            430090892                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            213498356                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               643589248                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       430090892                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          430090892                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           430090892                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           213498356                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              643589248                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            86212                       # number of cpu cycles simulated
+system.cpu.numCycles                            82736                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                       15162                       # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs                          3683                       # nu
 system.cpu.num_load_insts                        2231                       # Number of load instructions
 system.cpu.num_store_insts                       1452                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      86212                       # Number of busy cycles
+system.cpu.num_busy_cycles                      82736                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                152.957781                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                153.782734                       # Cycle average of tags in use
 system.cpu.icache.total_refs                    14928                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    280                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  53.314286                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     152.957781                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.074686                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.074686                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     153.782734                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.075089                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.075089                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst        14928                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total           14928                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst         14928                       # number of demand (read+write) hits
@@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst          280                       # n
 system.cpu.icache.demand_misses::total            280                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          280                       # number of overall misses
 system.cpu.icache.overall_misses::total           280                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     15596000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     15596000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     15596000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     15596000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     15596000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     15596000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15316000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15316000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15316000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15316000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15316000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15316000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst        15208                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total        15208                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst        15208                       # number of demand (read+write) accesses
@@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.018411
 system.cpu.icache.demand_miss_rate::total     0.018411                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.018411                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.018411                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        55700                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        55700                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        55700                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        55700                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        55700                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        55700                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        54700                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total        54700                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        54700                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total        54700                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        54700                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total        54700                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        52700
 system.cpu.icache.overall_avg_mshr_miss_latency::total        52700                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 97.669722                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 97.994344                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     3535                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  25.615942                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      97.669722                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.023845                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.023845                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      97.994344                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.023924                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.023924                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         2172                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            2172                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1357                       # number of WriteReq hits
@@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data          138                       # n
 system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.dcache.overall_misses::total           138                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      2968000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      2968000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      4760000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      4760000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7728000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7728000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7728000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7728000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      2915000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      2915000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4675000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4675000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7590000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7590000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7590000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7590000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         2225                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         2225                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
@@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.037633
 system.cpu.dcache.demand_miss_rate::total     0.037633                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.037633                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.037633                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        55000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        55000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        55000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        55000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -231,16 +231,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               183.688794                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               184.632038                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   331                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.006042                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    152.283537                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     31.405257                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004647                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000958                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005606                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    153.110886                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     31.521152                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004673                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000962                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005635                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits