diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt | |
parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt')
-rw-r--r-- | tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index b595d4238..ac8c29d55 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 82736 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use -system.cpu.icache.total_refs 14928 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -268,15 +268,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use -system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits |