stats: update stats for insts/ops and master id changes

1 files changed, 224 insertions, 146 deletions

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index f52890637..f7405d428 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds                                  0.000042                       # Nu
 sim_ticks                                    41800000                       # Number of ticks simulated
 final_tick                                   41800000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 146106                       # Simulator instruction rate (inst/s)
-host_tick_rate                              402347608                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212484                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                 399467                       # Simulator instruction rate (inst/s)
+host_op_rate                                   399277                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1099343547                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210560                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
+sim_ops                                         15175                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       26624                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  17792                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls                   18                       # Nu
 system.cpu.numCycles                            83600                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                            15175                       # Number of instructions executed
+system.cpu.committedInsts                       15175                       # Number of instructions committed
+system.cpu.committedOps                         15175                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                 12231                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         385                       # number of times a function call or return occured
@@ -46,26 +49,39 @@ system.cpu.icache.total_refs                    14941                       # To
 system.cpu.icache.sampled_refs                    280                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  53.360714                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            153.436702                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.074920                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                  14941                       # number of ReadReq hits
-system.cpu.icache.demand_hits                   14941                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                  14941                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  280                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   280                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  280                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       15596000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        15596000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       15596000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses              15221                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses               15221                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses              15221                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.018396                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.018396                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.018396                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency        55700                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency        55700                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency        55700                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     153.436702                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.074920                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.074920                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst        14941                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total           14941                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst         14941                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total            14941                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst        14941                       # number of overall hits
+system.cpu.icache.overall_hits::total           14941                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          280                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           280                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          280                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            280                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          280                       # number of overall misses
+system.cpu.icache.overall_misses::total           280                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15596000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15596000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15596000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15596000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15596000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15596000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst        15221                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total        15221                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst        15221                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total        15221                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst        15221                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total        15221                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.018396                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.018396                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.018396                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        55700                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        55700                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        55700                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             280                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              280                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             280                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     14756000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     14756000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     14756000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.018396                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.018396                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.018396                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        52700                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        52700                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        52700                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          280                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          280                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          280                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          280                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          280                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          280                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14756000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     14756000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14756000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     14756000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14756000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     14756000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.018396                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.018396                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.018396                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        52700                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        52700                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        52700                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 97.842991                       # Cycle average of tags in use
@@ -101,34 +115,53 @@ system.cpu.dcache.total_refs                     3536                       # To
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  25.623188                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             97.842991                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.023887                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   2173                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                  1357                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits                      6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits                    3530                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   3530                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   53                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                  85                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   138                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  138                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        2968000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       4760000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         7728000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        7728000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               2226                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses              1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses                  6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                3668                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               3668                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.023810                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.058946                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.037623                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.037623                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      97.842991                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.023887                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.023887                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         2173                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            2173                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1357                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1357                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data          3530                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             3530                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         3530                       # number of overall hits
+system.cpu.dcache.overall_hits::total            3530                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            53                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           85                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           85                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
+system.cpu.dcache.overall_misses::total           138                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      2968000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      2968000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4760000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4760000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7728000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7728000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7728000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7728000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         2226                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2226                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         3668                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         3668                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         3668                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         3668                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.023810                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.058946                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037623                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037623                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -137,30 +170,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              53                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             85                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2809000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      4505000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      7314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.023810                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.037623                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.037623                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           85                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           85                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2809000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2809000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4505000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4505000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7314000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7314000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023810                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               184.236128                       # Cycle average of tags in use
@@ -168,31 +201,64 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.sampled_refs                   331                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.006042                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           184.236128                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005622                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 331                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                85                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  416                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 416                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      17212000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      4420000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       21632000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      21632000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               333                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              85                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                418                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               418                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.993994                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.995215                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.995215                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    152.765242                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     31.470886                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004662                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000960                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005622                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          278                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          331                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           85                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           85                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           416                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          416                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14456000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2756000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     17212000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4420000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4420000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     14456000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7176000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     21632000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     14456000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7176000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     21632000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          280                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          333                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           85                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           85                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          280                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          418                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          280                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          418                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992857                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992857                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992857                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -201,30 +267,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            331                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           85                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             416                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            416                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     13240000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      3400000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     16640000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     16640000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.993994                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.995215                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.995215                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          278                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          331                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           85                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           85                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          416                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          416                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13240000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3400000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3400000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5520000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     16640000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5520000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     16640000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------