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author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
commit | 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch) | |
tree | 81108e7ff1951b652258f53bd5615a617b734ce2 /tests/quick/se/02.insttest/ref/sparc/linux/simple-timing | |
parent | ddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff) | |
download | gem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz |
update stats for preceeding changes
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux/simple-timing')
3 files changed, 30 insertions, 30 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index cd98523de..0cf9ff042 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -61,22 +61,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -92,22 +92,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -124,24 +124,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -151,10 +151,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -169,7 +169,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -193,7 +193,7 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index cacf98182..8494e13f4 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:28 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:40 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 43106000 because target called exit() +Exiting @ tick 41368000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index af9b5d77e..54610aef7 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 41368000 # Number of ticks simulated final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 652409 # Simulator instruction rate (inst/s) -host_op_rate 651936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1777530278 # Simulator tick rate (ticks/s) -host_mem_usage 220352 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 17560 # Simulator instruction rate (inst/s) +host_op_rate 17560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47909450 # Simulator tick rate (ticks/s) +host_mem_usage 220988 # Number of bytes of host memory used +host_seconds 0.86 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory |