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authorNilay Vaish <nilay@cs.wisc.edu>2015-08-30 12:24:19 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-30 12:24:19 -0500
commit66941163e50abceaa86c5eb6a18de6bbc2ec4ef8 (patch)
tree695a23cc938e997e1bc5f318576aa84c186a9aab /tests/quick/se/02.insttest/ref/sparc/linux
parenta60a93eb051d49b86e33ed8add06f65fcdb37604 (diff)
downloadgem5-66941163e50abceaa86c5eb6a18de6bbc2ec4ef8.tar.xz
stats: updates due to recent changes.
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux')
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini85
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini15
2 files changed, 47 insertions, 53 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 38517782e..fcd535567 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -150,7 +150,7 @@ localPredictorSize=2048
numThreads=1
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -159,7 +159,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -170,7 +170,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=IntAlu
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
@@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=IntMult
opLat=3
+pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
opClass=IntDiv
opLat=20
+pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
@@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=FloatAdd
opLat=2
+pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=FloatCmp
opLat=2
+pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=FloatCvt
opLat=2
+pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
@@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=FloatMult
opLat=4
+pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
-issueLat=12
opClass=FloatDiv
opLat=12
+pipelined=false
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
-issueLat=24
opClass=FloatSqrt
opLat=24
+pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=MemRead
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
@@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdAdd
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdAddAcc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdAlu
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdCmp
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdCvt
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdMisc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdMult
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdMultAcc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdShift
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdShiftAcc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdSqrt
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatAdd
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatAlu
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatCmp
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatCvt
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatDiv
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatMisc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatMult
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatMultAcc
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=SimdFloatSqrt
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
@@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=MemWrite
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
@@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=MemRead
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
-issueLat=1
opClass=MemWrite
opLat=1
+pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
@@ -493,12 +492,12 @@ opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
-issueLat=3
opClass=IprAccess
opLat=3
+pipelined=false
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -507,7 +506,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -518,7 +517,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -547,7 +545,7 @@ eventq_index=0
size=64
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -556,7 +554,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
-is_top_level=false
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -567,7 +565,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -611,7 +608,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
+executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
kvmInSE=false
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 5a5031a15..76cf5023d 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -87,7 +87,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -98,7 +98,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -119,7 +118,7 @@ eventq_index=0
size=64
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -128,7 +127,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -139,7 +138,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -168,7 +166,7 @@ eventq_index=0
size=64
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -177,7 +175,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
-is_top_level=false
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -188,7 +186,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]