diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/quick/se/02.insttest/ref/sparc/linux | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 903 | ||||
| -rw-r--r-- | tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt | 192 |
2 files changed, 557 insertions, 538 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index eba0d2782..85270cbb1 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27482500 # Number of ticks simulated -final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27401500 # Number of ticks simulated +final_tick 27401500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 15220 # Simulator instruction rate (inst/s) -host_op_rate 15220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28973949 # Simulator tick rate (ticks/s) -host_mem_usage 223564 # Number of bytes of host memory used -host_seconds 0.95 # Real time elapsed on the host +host_inst_rate 94035 # Simulator instruction rate (inst/s) +host_op_rate 94027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 178462571 # Simulator tick rate (ticks/s) +host_mem_usage 293360 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 22016 # Nu system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory system.physmem.num_reads::total 492 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 801091604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 344655690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1145747294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 801091604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 801091604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 801091604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 344655690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1145747294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 803459665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 345674507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1149134171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 803459665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 803459665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 803459665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 345674507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1149134171 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 492 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27431000 # Total gap between requests +system.physmem.totGap 27350000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -187,72 +187,71 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 404.732394 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 270.110571 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 339.824701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 18.31% 18.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 25.35% 43.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 405.633803 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 274.142926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 337.087748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 16.90% 16.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 26.76% 43.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 9 12.68% 56.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 7 9.86% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 9.86% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.41% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 11.27% 77.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 4 5.63% 83.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 2.82% 85.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 14.08% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation -system.physmem.totQLat 3613750 # Total ticks spent queuing -system.physmem.totMemAccLat 12838750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3217000 # Total ticks spent queuing +system.physmem.totMemAccLat 12442000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7345.02 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6538.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26095.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1145.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25288.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1149.13 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1145.75 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1149.13 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.95 # Data bus utilization in percentage -system.physmem.busUtilRead 8.95 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.98 # Data bus utilization in percentage +system.physmem.busUtilRead 8.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 412 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 55754.07 # Average gap between requests +system.physmem.avgGap 55589.43 # Average gap between requests system.physmem.pageHitRate 83.74 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2059200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2067000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15743115 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 361500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20156895 # Total energy per rank (pJ) -system.physmem_0.averagePower 853.427679 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 520250 # Time in different power states +system.physmem_0.actBackEnergy 15796980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 314250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20171310 # Total energy per rank (pJ) +system.physmem_0.averagePower 854.037999 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 440750 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22332250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22411750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15564420 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 518250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19277100 # Total energy per rank (pJ) -system.physmem_1.averagePower 816.177825 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2637000 # Time in different power states +system.physmem_1.actBackEnergy 15639660 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 452250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19286340 # Total energy per rank (pJ) +system.physmem_1.averagePower 816.569039 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2456000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22058500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22168500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 8538 # Number of BP lookups -system.cpu.branchPred.condPredicted 5461 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1059 # Number of conditional branches incorrect +system.cpu.branchPred.lookups 8543 # Number of BP lookups +system.cpu.branchPred.condPredicted 5466 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 5976 # Number of BTB lookups system.cpu.branchPred.BTBHits 3053 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. @@ -261,232 +260,232 @@ system.cpu.branchPred.usedRAS 609 # Nu system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 54966 # number of cpu cycles simulated +system.cpu.numCycles 54804 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14246 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 40057 # Number of instructions fetch has processed -system.cpu.fetch.Branches 8538 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 14234 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 40091 # Number of instructions fetch has processed +system.cpu.fetch.Branches 8543 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 3662 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 15957 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 15933 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1045 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 6438 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.235488 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.378208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 6440 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 32383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.238026 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.380017 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20898 64.46% 64.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5494 16.95% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 685 2.11% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 505 1.56% 85.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 819 2.53% 87.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 909 2.80% 90.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 334 1.03% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 371 1.14% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2407 7.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20844 64.37% 64.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5506 17.00% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 683 2.11% 83.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 516 1.59% 85.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 807 2.49% 87.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 911 2.81% 90.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 334 1.03% 91.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 372 1.15% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2410 7.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.155332 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.728760 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11347 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12433 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 6847 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 640 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 32383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.155883 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.731534 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11354 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12386 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 6823 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 665 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30502 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 30509 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11955 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1146 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9859 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 6898 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1409 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27684 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 11949 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1145 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9839 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 6913 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1382 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27687 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 1012 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 986 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 25054 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51692 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 42838 # Number of integer rename lookups +system.cpu.rename.RenameLookups 51693 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 42839 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 11235 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 767 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3842 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3673 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.serializingInsts 766 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 785 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3795 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2349 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23655 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 23661 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 21924 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9945 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6501 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 9951 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6530 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32422 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.676208 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.425800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 32383 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.677022 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.427893 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24009 74.05% 74.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3087 9.52% 83.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1572 4.85% 88.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1483 4.57% 93.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 954 2.94% 95.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 709 2.19% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 413 1.27% 99.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 155 0.48% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23977 74.04% 74.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3084 9.52% 83.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1575 4.86% 88.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1484 4.58% 93.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 922 2.85% 95.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 733 2.26% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 411 1.27% 99.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 157 0.48% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 40 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32422 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32383 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 111 49.33% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 49 21.78% 71.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 65 28.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111 49.55% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 49 21.88% 71.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 28.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16300 74.35% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3501 15.97% 90.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16295 74.32% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3505 15.99% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2124 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 21924 # Type of FU issued -system.cpu.iq.rate 0.398865 # Inst issue rate -system.cpu.iq.fu_busy_cnt 225 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010263 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76549 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 34352 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses +system.cpu.iq.rate 0.400044 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010217 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 76509 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 34365 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20239 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22149 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22148 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 901 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1147 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25507 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3673 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions +system.cpu.iew.iewBlockCycles 1144 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25514 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2349 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 260 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1194 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20914 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3347 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 20912 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1126 # number of nop insts executed -system.cpu.iew.exec_refs 5371 # number of memory reference insts executed -system.cpu.iew.exec_branches 4427 # Number of branches executed +system.cpu.iew.exec_nop 1127 # number of nop insts executed +system.cpu.iew.exec_refs 5373 # number of memory reference insts executed +system.cpu.iew.exec_branches 4424 # Number of branches executed system.cpu.iew.exec_stores 2024 # Number of stores executed -system.cpu.iew.exec_rate 0.380490 # Inst execution rate -system.cpu.iew.wb_sent 20501 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 20244 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9848 # num instructions producing a value -system.cpu.iew.wb_consumers 12670 # num instructions consuming a value +system.cpu.iew.exec_rate 0.381578 # Inst execution rate +system.cpu.iew.wb_sent 20497 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 20239 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9852 # num instructions producing a value +system.cpu.iew.wb_consumers 12795 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.368300 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.777269 # average fanout of values written-back +system.cpu.iew.wb_rate 0.369298 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.769988 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10287 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10294 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1059 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30361 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.499391 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.308685 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 30320 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.500066 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312560 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23816 78.44% 78.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3429 11.29% 89.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1193 3.93% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 637 2.10% 95.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 331 1.09% 96.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 224 0.74% 97.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 397 1.31% 98.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 272 0.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23779 78.43% 78.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3460 11.41% 89.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1176 3.88% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 592 1.95% 95.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 324 1.07% 96.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 261 0.86% 97.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 394 1.30% 98.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 63 0.21% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 271 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30361 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30320 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -532,36 +531,36 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 54715 # The number of ROB reads -system.cpu.rob.rob_writes 52974 # The number of ROB writes +system.cpu.commit.bw_lim_events 271 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 54682 # The number of ROB reads +system.cpu.rob.rob_writes 52990 # The number of ROB writes system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 22544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 22421 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.807564 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.807564 # CPI: Total CPI of All Threads -system.cpu.ipc 0.262635 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.262635 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 33408 # number of integer regfile reads -system.cpu.int_regfile_writes 18606 # number of integer regfile writes -system.cpu.misc_regfile_reads 7133 # number of misc regfile reads +system.cpu.cpi 3.796342 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.796342 # CPI: Total CPI of All Threads +system.cpu.ipc 0.263411 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.263411 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 33404 # number of integer regfile reads +system.cpu.int_regfile_writes 18604 # number of integer regfile writes +system.cpu.misc_regfile_reads 7136 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.556611 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.713941 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4125 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 28.061224 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.556611 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024062 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024062 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.713941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024100 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 9489 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 9489 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 3086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 3086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -572,64 +571,64 @@ system.cpu.dcache.demand_hits::cpu.data 4119 # nu system.cpu.dcache.demand_hits::total 4119 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 4119 # number of overall hits system.cpu.dcache.overall_hits::total 4119 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 137 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 137 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 138 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 138 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 546 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 546 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 546 # number of overall misses -system.cpu.dcache.overall_misses::total 546 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9397000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9397000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27538481 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27538481 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36935481 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36935481 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36935481 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36935481 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3223 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3223 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 547 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 547 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 547 # number of overall misses +system.cpu.dcache.overall_misses::total 547 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9332000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9332000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27213977 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27213977 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36545977 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36545977 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36545977 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36545977 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4665 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4665 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4665 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4665 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042507 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.042507 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042804 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042804 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117042 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117042 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117042 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68591.240876 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68591.240876 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67331.249389 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67331.249389 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67647.401099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67647.401099 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1052 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.117231 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117231 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117231 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117231 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67623.188406 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67623.188406 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66537.841076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66537.841076 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66811.658135 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66811.658135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66811.658135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66811.658135 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1080 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.818182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.538462 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 73 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 398 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 398 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 398 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 398 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 399 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 399 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 399 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 399 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -638,199 +637,204 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5143250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5143250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6389250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6389250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11532500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11532500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11532500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11532500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020168 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020168 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5162500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5162500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6419500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6419500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11582000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11582000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11582000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11582000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031726 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031726 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79126.923077 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79126.923077 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76978.915663 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76978.915663 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79423.076923 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79423.076923 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77343.373494 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77343.373494 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78256.756757 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78256.756757 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78256.756757 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78256.756757 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 190.975563 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5904 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 191.519539 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5908 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.063584 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.075145 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 190.975563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.093250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.093250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 191.519539 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.093515 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.093515 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13222 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13222 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 5904 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5904 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5904 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5904 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5904 # number of overall hits -system.cpu.icache.overall_hits::total 5904 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 534 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 534 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 534 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 534 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 534 # number of overall misses -system.cpu.icache.overall_misses::total 534 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37367000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37367000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37367000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37367000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37367000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37367000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6438 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6438 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6438 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6438 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6438 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6438 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69975.655431 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 13226 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13226 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5908 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5908 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5908 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5908 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5908 # number of overall hits +system.cpu.icache.overall_hits::total 5908 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 532 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 532 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 532 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 532 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68093.045113 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68093.045113 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68093.045113 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77938.461538 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77938.461538 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74630.813953 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76753.378378 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75269.308943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74630.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76753.378378 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75269.308943 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,55 +843,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21861250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4272750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26134000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5278250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5278250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21861250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31412250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21861250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31412250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5463500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5463500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22233000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22233000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4426000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4426000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22233000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9889500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32122500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22233000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9889500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32122500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994220 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63550.145349 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65734.615385 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63897.310513 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63593.373494 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63593.373494 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65825.301205 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65825.301205 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64630.813953 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64630.813953 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68092.307692 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68092.307692 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64630.813953 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66820.945946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65289.634146 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64630.813953 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66820.945946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65289.634146 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) @@ -908,14 +917,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 245000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 409 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 519000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadResp 408 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 409 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) @@ -931,9 +940,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 492 # Request fanout histogram -system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 593500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2599750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2604000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 9.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 56b893c5d..625747903 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 41368500 # Number of ticks simulated final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311873 # Simulator instruction rate (inst/s) -host_op_rate 311783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 850451247 # Simulator tick rate (ticks/s) -host_mem_usage 289340 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 372083 # Simulator instruction rate (inst/s) +host_op_rate 371955 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1014555487 # Simulator tick rate (ticks/s) +host_mem_usage 290028 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,14 +90,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.991492 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 97.989824 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.991492 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 97.989824 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id @@ -172,14 +172,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4547500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4547500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4590000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4590000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7452000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7452000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7452000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7452000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -188,24 +188,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 153.777491 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 153.774107 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 153.777491 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.075087 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.075087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 153.774107 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id @@ -262,33 +262,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14896500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14896500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14896500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14896500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14896500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14896500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15036500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15036500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15036500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15036500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15036500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15036500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53201.785714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53201.785714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53701.785714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53701.785714 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.625818 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.609803 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.105687 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.520131 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.092235 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517568 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy @@ -298,61 +298,66 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 331 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 138 # 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number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.510574 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency @@ -367,55 +372,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13405500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5589000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5589000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3612500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3612500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5865000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5865000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) @@ -440,10 +450,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 420000 # La system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 331 # Transaction distribution system.membus.trans_dist::ReadResp 331 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) |