diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/se/02.insttest/ref/sparc/linux | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux')
3 files changed, 540 insertions, 522 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index a74466584..698dda741 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28845500 # Number of ticks simulated -final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29089500 # Number of ticks simulated +final_tick 29089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66025 # Simulator instruction rate (inst/s) -host_op_rate 66018 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131902943 # Simulator tick rate (ticks/s) -host_mem_usage 248796 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 39190 # Simulator instruction rate (inst/s) +host_op_rate 39188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78964807 # Simulator tick rate (ticks/s) +host_mem_usage 252916 # Number of bytes of host memory used +host_seconds 0.37 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory system.physmem.bytes_read::total 32640 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 23232 # Nu system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 798638684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 323415665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1122054350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 798638684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 798638684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 798638684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 323415665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1122054350 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 511 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 28814000 # Total gap between requests +system.physmem.totGap 29058000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -188,309 +188,309 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 411.306667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 274.853259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.874505 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 25.33% 42.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12 16.00% 58.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 8.00% 66.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation -system.physmem.totQLat 3584250 # Total ticks spent queuing -system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3266500 # Total ticks spent queuing +system.physmem.totMemAccLat 12847750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6392.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25142.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1124.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1124.25 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.86 # Data bus utilization in percentage -system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.78 # Data bus utilization in percentage +system.physmem.busUtilRead 8.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 428 # Number of row buffer hits during reads +system.physmem.readRowHits 427 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 56387.48 # Average gap between requests -system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined +system.physmem.avgGap 56864.97 # Average gap between requests +system.physmem.pageHitRate 83.56 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2113800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ) -system.physmem_0.averagePower 856.515480 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states +system.physmem_0.actBackEnergy 16083405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 63000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20264970 # Total energy per rank (pJ) +system.physmem_0.averagePower 858.003493 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ) -system.physmem_1.averagePower 820.243027 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states +system.physmem_1.actBackEnergy 15332715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 721500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19350015 # Total energy per rank (pJ) +system.physmem_1.averagePower 819.264991 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4570750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21719750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 12618 # Number of BP lookups -system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 12614 # Number of BP lookups +system.cpu.branchPred.condPredicted 7656 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 9453 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 9453 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 7609 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 28845500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 57692 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 29089500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 58180 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed -system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 15554 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 59055 # Number of instructions fetch has processed +system.cpu.fetch.Branches 12614 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 17529 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1090 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 720 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 35776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.650688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.904189 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23025 64.36% 64.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4506 12.60% 76.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 507 1.42% 78.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 451 1.26% 79.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 761 2.13% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 707 1.98% 83.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 297 0.83% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 355 0.99% 85.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5167 14.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7933 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 35776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.216810 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.015040 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12463 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13012 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7932 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 797 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 42051 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 13239 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1819 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9760 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7921 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1465 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 37034 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1048 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 31990 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 66442 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54845 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 18171 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 796 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2920 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 28828 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15149 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 11337 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 35776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.708911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.503990 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26518 74.12% 74.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3268 9.13% 83.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1619 4.53% 87.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1541 4.31% 92.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1236 3.45% 95.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 752 2.10% 97.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 465 1.30% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 277 0.77% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 35776 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 154 52.56% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51 17.41% 69.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 88 30.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 18584 73.27% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 4272 16.84% 90.12% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 25362 # Type of FU issued -system.cpu.iq.rate 0.439610 # Inst issue rate -system.cpu.iq.fu_busy_cnt 294 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses +system.cpu.iq.rate 0.435923 # Inst issue rate +system.cpu.iq.fu_busy_cnt 293 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011553 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 86911 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 44761 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 22611 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 25655 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1472 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 1852 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 31164 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 2920 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 1624 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1835 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 23718 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1644 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1579 # number of nop insts executed -system.cpu.iew.exec_refs 6244 # number of memory reference insts executed +system.cpu.iew.exec_refs 6245 # number of memory reference insts executed system.cpu.iew.exec_branches 5021 # Number of branches executed -system.cpu.iew.exec_stores 2299 # Number of stores executed -system.cpu.iew.exec_rate 0.411045 # Inst execution rate -system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22607 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10530 # num instructions producing a value -system.cpu.iew.wb_consumers 13790 # num instructions consuming a value -system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit +system.cpu.iew.exec_stores 2300 # Number of stores executed +system.cpu.iew.exec_rate 0.407666 # Inst execution rate +system.cpu.iew.wb_sent 23107 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 22611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10526 # num instructions producing a value +system.cpu.iew.wb_consumers 13786 # num instructions consuming a value +system.cpu.iew.wb_rate 0.388639 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.763528 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 15913 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 32637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.464565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.243420 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25892 79.33% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3639 11.15% 90.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1211 3.71% 94.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 601 1.84% 96.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 338 1.04% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 300 0.92% 97.99% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 54 0.17% 99.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 32637 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,37 +537,37 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 62581 # The number of ROB reads -system.cpu.rob.rob_writes 65380 # The number of ROB writes -system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 62661 # The number of ROB reads +system.cpu.rob.rob_writes 65377 # The number of ROB writes +system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 22404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads -system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36850 # number of integer regfile reads -system.cpu.int_regfile_writes 20548 # number of integer regfile writes -system.cpu.misc_regfile_reads 8142 # number of misc regfile reads +system.cpu.cpi 4.030202 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.030202 # CPI: Total CPI of All Threads +system.cpu.ipc 0.248127 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.248127 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 36851 # number of integer regfile reads +system.cpu.int_regfile_writes 20552 # number of integer regfile writes +system.cpu.misc_regfile_reads 8143 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 99.825953 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 99.825953 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024372 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024372 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -586,14 +586,14 @@ system.cpu.dcache.demand_misses::cpu.data 549 # n system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses system.cpu.dcache.overall_misses::total 549 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9476500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9476500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27259981 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27259981 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36736481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36736481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36736481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36736481 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -612,19 +612,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67689.285714 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67689.285714 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66650.320293 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66650.320293 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66915.265938 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66915.265938 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.956522 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits @@ -642,14 +642,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5190500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5190500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6454500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6454500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11645000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11645000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -658,31 +658,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79853.846154 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79853.846154 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77765.060241 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77765.060241 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 206.188252 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 206.188252 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.100678 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.100678 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses system.cpu.icache.tags.data_accesses 15425 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits @@ -695,12 +695,12 @@ system.cpu.icache.demand_misses::cpu.inst 581 # n system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses system.cpu.icache.overall_misses::total 581 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40938500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40938500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40938500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40938500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40938500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40938500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses @@ -713,17 +713,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70462.134251 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70462.134251 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70462.134251 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70462.134251 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 194 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 97 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits @@ -737,43 +737,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27977500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27977500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27977500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27977500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27977500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27977500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.048473 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.048473 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76650.684932 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76650.684932 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 305.425349 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.546698 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 99.878652 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006273 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.009321 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -792,18 +792,18 @@ system.cpu.l2cache.demand_misses::total 511 # nu system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses system.cpu.l2cache.overall_misses::total 511 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6452500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6452500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27176000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27176000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5013500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5013500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27176000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11466000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 38642000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27176000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11466000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 38642000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6329000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6329000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27407000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27407000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5095500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5095500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27407000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11424500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 38831500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27407000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11424500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 38831500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) @@ -828,18 +828,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.996101 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76253.012048 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76253.012048 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75501.377410 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75501.377410 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78392.307692 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78392.307692 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75501.377410 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77192.567568 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75991.193738 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75501.377410 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77192.567568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75991.193738 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -858,18 +858,18 @@ system.cpu.l2cache.demand_mshr_misses::total 511 system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5499000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5499000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23777000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23777000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4465500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4465500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23777000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9964500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 33741500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23777000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9964500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 33741500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses @@ -882,25 +882,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66253.012048 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66253.012048 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65501.377410 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65501.377410 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68700 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68700 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution @@ -931,7 +931,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 547500 # La system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution @@ -952,9 +958,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 511 # Request fanout histogram -system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 623000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2693500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 9.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index f98d4e626..3be5d7ce8 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 348414 # Simulator instruction rate (inst/s) -host_op_rate 348210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174731638 # Simulator tick rate (ticks/s) -host_mem_usage 237012 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 110250 # Simulator instruction rate (inst/s) +host_op_rate 110244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55345027 # Simulator tick rate (ticks/s) +host_mem_usage 240104 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -100,6 +100,12 @@ system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 17432 # Transaction distribution system.membus.trans_dist::ReadResp 17432 # Transaction distribution @@ -116,14 +122,14 @@ system.membus.pkt_size::total 81270 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 18880 # Request fanout histogram -system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram -system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18880 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 18880 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 28b8d6695..387eea7ee 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000044 # Number of seconds simulated -sim_ticks 44282500 # Number of ticks simulated -final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000045 # Number of seconds simulated +sim_ticks 44698500 # Number of ticks simulated +final_tick 44698500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 322672 # Simulator instruction rate (inst/s) -host_op_rate 322568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 941828647 # Simulator tick rate (ticks/s) -host_mem_usage 247000 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 128576 # Simulator instruction rate (inst/s) +host_op_rate 128568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379003891 # Simulator tick rate (ticks/s) +host_mem_usage 250608 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory system.physmem.bytes_read::total 26624 # Number of bytes read from this memory @@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 398044677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 197590523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 595635200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 398044677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 398044677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 398044677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 197590523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 595635200 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 44282500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 88565 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 44698500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 89397 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles +system.cpu.num_busy_cycles 89396.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 3363 # Number of branches fetched @@ -92,23 +92,23 @@ system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 97.037351 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 97.037351 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023691 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023691 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits @@ -127,14 +127,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3339000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3339000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5355000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5355000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8694000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8694000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8694000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8694000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -153,14 +153,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -175,14 +175,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3286000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3286000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8556000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8556000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8556000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8556000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -191,31 +191,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 151.480746 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 151.480746 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073965 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073965 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses system.cpu.icache.tags.data_accesses 30696 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -228,12 +228,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17542500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17542500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17542500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17542500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17542500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17542500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -246,12 +246,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62651.785714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62651.785714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62651.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62651.785714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -264,43 +264,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17262500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17262500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17262500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17262500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17262500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17262500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61651.785714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61651.785714 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 247.870917 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 416 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.004808 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 150.801148 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 97.069768 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004602 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007564 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012695 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -319,18 +319,18 @@ system.cpu.l2cache.demand_misses::total 416 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5142500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5142500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8349000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25168500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8349000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25168500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) @@ -355,18 +355,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995215 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.201923 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.201923 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,18 +385,18 @@ system.cpu.l2cache.demand_mshr_misses::total 416 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4292500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4292500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6969000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21008500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6969000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21008500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses @@ -409,25 +409,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution @@ -458,7 +458,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 420000 # La system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 331 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution |