diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/quick/se/02.insttest/ref/sparc/linux | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc/linux')
3 files changed, 389 insertions, 379 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 48563010b..17eb8fa43 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -598,7 +600,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/insttest/bin/sparc/linux/insttest +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -627,9 +629,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -640,27 +642,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 9f4e08c11..f333d0ba2 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:04:27 -gem5 started Jan 22 2014 17:29:34 -gem5 executing on u200540-lin -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing +gem5 compiled Jun 21 2014 11:07:38 +gem5 started Jun 21 2014 11:08:19 +gem5 executing on phenom +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -18,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 26616500 because target called exit() +Exiting @ tick 26706500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 68fda33e0..d600e3436 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,46 +4,46 @@ sim_seconds 0.000027 # Nu sim_ticks 26706500 # Number of ticks simulated final_tick 26706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64712 # Simulator instruction rate (inst/s) -host_op_rate 64708 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119701044 # Simulator tick rate (ticks/s) -host_mem_usage 272800 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 22395 # Simulator instruction rate (inst/s) +host_op_rate 22394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41428038 # Simulator tick rate (ticks/s) +host_mem_usage 228784 # Number of bytes of host memory used +host_seconds 0.64 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 30848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 802800816 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 483 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 805197237 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 352273791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1155074607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 802800816 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 802800816 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 802800816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 1157471028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 805197237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 805197237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 805197237 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 352273791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1155074607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 482 # Number of read requests accepted +system.physmem.bw_total::total 1157471028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 483 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 483 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 30912 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side +system.physmem.bytesReadSys 30912 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 102 # Per bank write bursts system.physmem.perBankRdBursts::1 29 # Per bank write bursts -system.physmem.perBankRdBursts::2 50 # Per bank write bursts +system.physmem.perBankRdBursts::2 51 # Per bank write bursts system.physmem.perBankRdBursts::3 24 # Per bank write bursts system.physmem.perBankRdBursts::4 19 # Per bank write bursts system.physmem.perBankRdBursts::5 0 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.readPktSize::2 0 # Re system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 482 # Read request sizes (log2) +system.physmem.readPktSize::6 483 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -187,156 +187,156 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 403.200000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 265.551535 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.027861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 404.114286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 265.832819 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.256092 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 22 31.43% 48.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 9 12.86% 61.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3 4.29% 65.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 4 5.71% 71.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 3 4.29% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 8.57% 84.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.43% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 7.14% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.86% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation -system.physmem.totQLat 2602000 # Total ticks spent queuing -system.physmem.totMemAccLat 11639500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5398.34 # Average queueing delay per DRAM burst +system.physmem.totQLat 2649500 # Total ticks spent queuing +system.physmem.totMemAccLat 11705750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5485.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24148.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1155.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24235.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1157.47 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1155.07 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1157.47 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.02 # Data bus utilization in percentage -system.physmem.busUtilRead 9.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.04 # Data bus utilization in percentage +system.physmem.busUtilRead 9.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 403 # Number of row buffer hits during reads +system.physmem.readRowHits 404 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 55073.65 # Average gap between requests -system.physmem.pageHitRate 83.61 # Row buffer hit rate, read and write combined +system.physmem.avgGap 54959.63 # Average gap between requests +system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 1553250 # Time in different power states system.physmem.memoryStateTime::REF 780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 21299250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1155074607 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 399 # Transaction distribution -system.membus.trans_dist::ReadResp 399 # Transaction distribution +system.membus.throughput 1157471028 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 400 # Transaction distribution +system.membus.trans_dist::ReadResp 400 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30848 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 966 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 966 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30912 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 606500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 603000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 4499500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 16.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4506000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 16.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 6716 # Number of BP lookups -system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted +system.cpu.branchPred.lookups 6723 # Number of BP lookups +system.cpu.branchPred.condPredicted 4462 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2432 # Number of BTB hits +system.cpu.branchPred.BTBLookups 5029 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2435 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.419169 # BTB Hit Percentage system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 53414 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12411 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31121 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9132 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9191 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12428 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31151 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6723 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2879 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9139 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3047 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8960 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33531 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.928126 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.121319 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 33327 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.934708 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.127415 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24399 72.77% 72.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4510 13.45% 86.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 474 1.41% 87.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 392 1.17% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 680 2.03% 90.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 706 2.11% 92.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.70% 93.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 253 0.75% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1882 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24188 72.58% 72.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4512 13.54% 86.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 474 1.42% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 392 1.18% 88.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 683 2.05% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 706 2.12% 92.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.71% 93.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 253 0.76% 94.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1884 5.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33531 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125735 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.582638 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12927 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10191 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8340 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 201 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13569 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 456 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9204 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7948 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 482 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 33327 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125866 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.583199 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12851 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 10052 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8399 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 150 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1875 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29050 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1875 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13476 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 163 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9186 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7977 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 650 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 26689 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 152 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 40918 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 339 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 23975 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49504 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 40958 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10156 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2747 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 2667 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2291 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22517 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22544 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21121 # Number of instructions issued +system.cpu.iq.iqInstsIssued 21140 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7903 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 7925 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5519 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33531 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.629895 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.256216 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 33327 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.634321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.264898 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24281 72.41% 72.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3570 10.65% 83.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2315 6.90% 89.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1704 5.08% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 886 2.64% 97.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 470 1.40% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 240 0.72% 99.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.13% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24173 72.53% 72.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3454 10.36% 82.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2274 6.82% 89.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1733 5.20% 94.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 917 2.75% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 1.41% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 241 0.72% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33531 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33327 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available @@ -372,7 +372,7 @@ system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15650 74.10% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15664 74.10% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued @@ -401,84 +401,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2109 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3362 15.90% 90.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2114 10.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21121 # Type of FU issued -system.cpu.iq.rate 0.395421 # Inst issue rate +system.cpu.iq.FU_type_0::total 21140 # Type of FU issued +system.cpu.iq.rate 0.395776 # Inst issue rate system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76017 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31101 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.006954 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75851 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31150 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19533 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21268 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21287 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 843 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 300 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24306 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 403 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewSquashCycles 1875 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 148 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24333 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 2291 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 946 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 947 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1211 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20085 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1047 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1055 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1134 # number of nop insts executed -system.cpu.iew.exec_refs 5224 # number of memory reference insts executed -system.cpu.iew.exec_branches 4239 # Number of branches executed -system.cpu.iew.exec_stores 2022 # Number of stores executed -system.cpu.iew.exec_rate 0.375819 # Inst execution rate -system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19522 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9116 # num instructions producing a value -system.cpu.iew.wb_consumers 11226 # num instructions consuming a value +system.cpu.iew.exec_refs 5227 # number of memory reference insts executed +system.cpu.iew.exec_branches 4240 # Number of branches executed +system.cpu.iew.exec_stores 2025 # Number of stores executed +system.cpu.iew.exec_rate 0.376025 # Inst execution rate +system.cpu.iew.wb_sent 19760 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19533 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9201 # num instructions producing a value +system.cpu.iew.wb_consumers 11404 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.365485 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.812043 # average fanout of values written-back +system.cpu.iew.wb_rate 0.365691 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.806822 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9046 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9073 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31659 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.478916 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.176623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 31452 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.482068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.184176 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 24337 76.87% 76.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4081 12.89% 89.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1353 4.27% 94.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 763 2.41% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 348 1.10% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 270 0.85% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 322 1.02% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 68 0.21% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 24226 77.03% 77.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3950 12.56% 89.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1330 4.23% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 819 2.60% 96.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 349 1.11% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 271 0.86% 98.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 322 1.02% 99.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31659 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31452 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -526,90 +526,90 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # system.cpu.commit.op_class_0::total 15162 # Class of committed instruction system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54927 # The number of ROB reads -system.cpu.rob.rob_writes 50296 # The number of ROB writes -system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19883 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54747 # The number of ROB reads +system.cpu.rob.rob_writes 50353 # The number of ROB writes +system.cpu.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20087 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.cpi 3.700055 # CPI: Cycles Per Instruction system.cpu.cpi_total 3.700055 # CPI: Total CPI of All Threads system.cpu.ipc 0.270266 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.270266 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32043 # number of integer regfile reads -system.cpu.int_regfile_writes 17841 # number of integer regfile writes -system.cpu.misc_regfile_reads 6919 # number of misc regfile reads +system.cpu.int_regfile_reads 32058 # number of integer regfile reads +system.cpu.int_regfile_writes 17849 # number of integer regfile writes +system.cpu.misc_regfile_reads 6922 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1159867448 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution +system.cpu.toL2Bus.throughput 1162263868 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 31040 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 242500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 564000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 566000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 235000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 187.422918 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 188.199882 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.414201 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 187.422918 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.091515 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.091515 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 188.199882 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091894 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091894 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.164551 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11095 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11095 # Number of data accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.165039 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11098 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11098 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits system.cpu.icache.overall_hits::total 4872 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses -system.cpu.icache.overall_misses::total 507 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31638750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31638750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31638750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31638750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31638750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31638750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62403.846154 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62403.846154 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62403.846154 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62403.846154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62403.846154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62403.846154 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 508 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 508 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 508 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 508 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 508 # number of overall misses +system.cpu.icache.overall_misses::total 508 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31702750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31702750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31702750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31702750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31702750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31702750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094424 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094424 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094424 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094424 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094424 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094424 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62406.988189 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62406.988189 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62406.988189 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62406.988189 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62406.988189 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62406.988189 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -624,109 +624,109 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 170 system.cpu.icache.demand_mshr_hits::total 170 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22516000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22516000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66813.056380 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66813.056380 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66813.056380 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66813.056380 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66813.056380 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66813.056380 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22584000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22584000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22584000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22584000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22584000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22584000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062825 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.062825 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.062825 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66816.568047 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66816.568047 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66816.568047 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66816.568047 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66816.568047 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66816.568047 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.271055 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 222.048188 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 400 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.815406 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.455649 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005701 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006753 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.592876 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.455312 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005725 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001051 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006776 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4354 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4354 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012207 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4363 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4363 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 482 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses +system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses -system.cpu.l2cache.overall_misses::total 482 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22159000 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::total 483 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22226000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4637250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26796250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6037250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6037250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22159000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10674500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32833500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22159000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10674500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32833500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::total 26863250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6075250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6075250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22226000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10712500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32938500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22226000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10712500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32938500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 337 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994065 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994083 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.995012 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994083 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66146.268657 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66148.809524 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72457.031250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67158.521303 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72737.951807 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72737.951807 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66146.268657 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72615.646259 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68119.294606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66146.268657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72615.646259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68119.294606 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67158.125000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73195.783133 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73195.783133 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66148.809524 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72874.149660 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68195.652174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66148.809524 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72874.149660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68195.652174 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -735,58 +735,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 482 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17946500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18000000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3851750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21798250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5016750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5016750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17946500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8868500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26815000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17946500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8868500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26815000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21851750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5060250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5060250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26912000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26912000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53571.641791 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53571.428571 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60183.593750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54632.205514 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60442.771084 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60442.771084 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53571.641791 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60329.931973 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55632.780083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53571.641791 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60329.931973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55632.780083 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54629.375000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60966.867470 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60966.867470 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53571.428571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60625.850340 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55718.426501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53571.428571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60625.850340 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55718.426501 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.054052 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 99.055513 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.054052 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 99.055513 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.024183 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.024183 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id @@ -813,14 +813,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7967250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7967250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25697977 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25697977 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33665227 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33665227 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33665227 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33665227 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7969250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7969250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25782224 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25782224 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33751474 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33751474 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33751474 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33751474 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -839,19 +839,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63232.142857 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63232.142857 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62831.239609 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62831.239609 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62925.657944 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62925.657944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62925.657944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62925.657944 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 776 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63248.015873 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63248.015873 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63037.222494 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63037.222494 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63086.867290 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63086.867290 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63086.867290 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63086.867290 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 851 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 25 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.040000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.392857 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -873,12 +873,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 147 system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4701750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4701750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6121250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6121250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10823000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10823000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10823000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10823000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6159250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6159250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10861000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10861000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10861000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10861000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -889,12 +889,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73464.843750 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73464.843750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73625.850340 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73625.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73625.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73625.850340 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74207.831325 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74207.831325 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73884.353741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73884.353741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73884.353741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73884.353741 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |