diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/quick/se/02.insttest/ref/sparc | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc')
3 files changed, 651 insertions, 651 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 2b7ec11ce..e278da8a8 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25614500 # Number of ticks simulated -final_tick 25614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 25317500 # Number of ticks simulated +final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72825 # Simulator instruction rate (inst/s) -host_op_rate 72819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 123010334 # Simulator tick rate (ticks/s) -host_mem_usage 229416 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 47783 # Simulator instruction rate (inst/s) +host_op_rate 47781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79779918 # Simulator tick rate (ticks/s) +host_mem_usage 220364 # Number of bytes of host memory used +host_seconds 0.32 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 744578266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 344804700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1089382967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 744578266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 744578266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 744578266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 344804700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1089382967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 753312926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 348849610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1102162536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 753312926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 753312926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 753312926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 348849610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1102162536 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 51230 # number of cpu cycles simulated +system.cpu.numCycles 50636 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 5020 # Number of BP lookups @@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 11058 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 22262 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 22132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 524 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33874 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17356 # Number of cycles cpu stages are processed. -system.cpu.activity 33.878587 # Percentage of cycles cpu is active +system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33281 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17355 # Number of cycles cpu stages are processed. +system.cpu.activity 34.274034 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -75,36 +75,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.378842 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.339665 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.378842 # CPI: Total CPI of All Threads -system.cpu.ipc 0.295959 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.339665 # CPI: Total CPI of All Threads +system.cpu.ipc 0.299431 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.295959 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 38098 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.299431 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37504 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 25.633418 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 42042 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.934804 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 42414 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 17.208667 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48346 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 25.934118 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 41449 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9187 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 18.143218 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 41821 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8815 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 17.408563 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47752 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.629514 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41913 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9317 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 18.186609 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 5.695553 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41318 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 18.401927 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 164.536889 # Cycle average of tags in use +system.cpu.icache.tagsinuse 164.702089 # Cycle average of tags in use system.cpu.icache.total_refs 2586 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 164.536889 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080340 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080340 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 164.702089 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080421 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080421 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits @@ -117,12 +117,12 @@ system.cpu.icache.demand_misses::cpu.inst 369 # n system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20585000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20585000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20585000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20585000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20585000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20585000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20235000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20235000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20235000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20235000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20235000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20235000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses @@ -135,12 +135,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.124873 system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55785.907859 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55785.907859 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55785.907859 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55785.907859 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55785.907859 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55785.907859 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54837.398374 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54837.398374 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54837.398374 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -161,34 +161,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16326500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16326500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16329000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16329000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54240.863787 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54240.863787 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54240.863787 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54240.863787 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54240.863787 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54240.863787 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54249.169435 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54249.169435 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 96.547387 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 96.602865 # Cycle average of tags in use system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 96.547387 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023571 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023571 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 96.602865 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023585 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023585 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits @@ -207,14 +207,14 @@ system.cpu.dcache.demand_misses::cpu.data 359 # n system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses system.cpu.dcache.overall_misses::total 359 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3488000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3488000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18458000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18458000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21946000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21946000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21946000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21946000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3411000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3411000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16758500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16758500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20169500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20169500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20169500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20169500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -233,20 +233,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097900 system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60137.931034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60137.931034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61322.259136 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61322.259136 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61130.919220 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61130.919220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61130.919220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61130.919220 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58810.344828 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58810.344828 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55676.079734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55676.079734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56182.451253 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2258500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50188.888889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits @@ -265,14 +265,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2987500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2987500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4730000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4730000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7717500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7717500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7717500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7717500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2994500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2994500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4733000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4733000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7727500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7727500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7727500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7727500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -281,26 +281,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56367.924528 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56367.924528 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55647.058824 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55647.058824 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55923.913043 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55923.913043 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55682.352941 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55682.352941 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.042677 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.229432 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 163.928542 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.114135 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 164.095749 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.133683 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000950 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005952 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005958 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -318,17 +318,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15989500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2926500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18916000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4635000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4635000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15989500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7561500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23551000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15989500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7561500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23551000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16005500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18945500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4645500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4645500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16005500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7585500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23591000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16005500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7585500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23591000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -351,17 +351,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53476.588629 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55216.981132 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53738.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54529.411765 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54529.411765 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53476.588629 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53892.448513 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53476.588629 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53892.448513 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53530.100334 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55471.698113 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53822.443182 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54652.941176 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54652.941176 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53983.981693 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53983.981693 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12379500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2285000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14664500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12379500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5889000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18268500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12379500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5889000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18268500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12396000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2298500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14694500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3614500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3614500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12396000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18309000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12396000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18309000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -403,17 +403,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41403.010033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43113.207547 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41660.511364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42400 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42400 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41458.193980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43367.924528 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41745.738636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42523.529412 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42523.529412 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index c96167523..5ed8e97b3 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,267 +1,267 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20275500 # Number of ticks simulated -final_tick 20275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19879000 # Number of ticks simulated +final_tick 19879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60587 # Simulator instruction rate (inst/s) -host_op_rate 60583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85082969 # Simulator tick rate (ticks/s) -host_mem_usage 230436 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 39676 # Simulator instruction rate (inst/s) +host_op_rate 39674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54630622 # Simulator tick rate (ticks/s) +host_mem_usage 221392 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory -system.physmem.bytes_read::total 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory -system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1063746887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 460851767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524598654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1063746887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1063746887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1063746887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 460851767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524598654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 481 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1078525077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 470043765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1548568841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1078525077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1078525077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1078525077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 470043765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1548568841 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 40552 # number of cpu cycles simulated +system.cpu.numCycles 39759 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6886 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4580 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1118 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5120 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2601 # Number of BTB hits +system.cpu.BPredUnit.lookups 6854 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4554 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1112 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4710 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2490 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 458 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 477 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12252 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 32221 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6886 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3059 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9555 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3174 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7365 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12088 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31936 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6854 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2967 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9404 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3148 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7222 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 767 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5498 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 31903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.009968 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.184021 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 741 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5545 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 478 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 31399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.017102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.199996 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22348 70.05% 70.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4753 14.90% 84.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 493 1.55% 86.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 436 1.37% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 686 2.15% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 773 2.42% 92.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 236 0.74% 93.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 275 0.86% 94.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1903 5.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21995 70.05% 70.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4682 14.91% 84.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 472 1.50% 86.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 410 1.31% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 687 2.19% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 719 2.29% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.75% 93.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 265 0.84% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1934 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 31903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.169807 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.794560 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12897 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8133 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8716 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1960 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30041 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1960 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13576 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 285 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7298 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8274 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 510 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27346 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 31399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.172389 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.803240 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12738 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7939 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8587 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 195 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1940 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29749 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1940 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13426 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7130 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8156 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 488 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27133 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 172 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24383 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 50854 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 50854 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 140 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24210 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 50486 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 50486 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10564 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 704 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2903 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3638 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2471 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 10391 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 723 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2887 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3597 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2432 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23123 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 669 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21711 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8357 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 194 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 31903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.680532 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.296567 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 22935 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 673 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21597 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 91 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8291 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5610 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 198 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 31399 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.687824 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.304127 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 22407 70.23% 70.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3681 11.54% 81.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2373 7.44% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1722 5.40% 94.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 903 2.83% 97.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 494 1.55% 98.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 242 0.76% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.20% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 22002 70.07% 70.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3599 11.46% 81.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2373 7.56% 89.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1680 5.35% 94.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 925 2.95% 97.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 497 1.58% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 251 0.80% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.18% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 31903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 31399 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45 26.16% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 13.95% 40.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 103 59.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 47 27.33% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27 15.70% 43.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 98 56.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16013 73.76% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2266 10.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15947 73.84% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3395 15.72% 89.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2255 10.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21711 # Type of FU issued -system.cpu.iq.rate 0.535387 # Inst issue rate +system.cpu.iq.FU_type_0::total 21597 # Type of FU issued +system.cpu.iq.rate 0.543198 # Inst issue rate system.cpu.iq.fu_busy_cnt 172 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007922 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75603 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32175 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19936 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.007964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 74856 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31925 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19878 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21883 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21769 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1413 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1372 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1023 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 984 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1960 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 99 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24957 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 410 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3638 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2471 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 669 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1940 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24765 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 456 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3597 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2432 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 673 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 290 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 957 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 268 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 979 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1247 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20532 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3272 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1179 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 20456 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3252 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1141 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1165 # number of nop insts executed -system.cpu.iew.exec_refs 5418 # number of memory reference insts executed -system.cpu.iew.exec_branches 4292 # Number of branches executed -system.cpu.iew.exec_stores 2146 # Number of stores executed -system.cpu.iew.exec_rate 0.506313 # Inst execution rate -system.cpu.iew.wb_sent 20199 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19936 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9239 # num instructions producing a value -system.cpu.iew.wb_consumers 11338 # num instructions consuming a value +system.cpu.iew.exec_nop 1157 # number of nop insts executed +system.cpu.iew.exec_refs 5386 # number of memory reference insts executed +system.cpu.iew.exec_branches 4298 # Number of branches executed +system.cpu.iew.exec_stores 2134 # Number of stores executed +system.cpu.iew.exec_rate 0.514500 # Inst execution rate +system.cpu.iew.wb_sent 20129 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19878 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9203 # num instructions producing a value +system.cpu.iew.wb_consumers 11321 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.491616 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.814870 # average fanout of values written-back +system.cpu.iew.wb_rate 0.499962 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.812914 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9713 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9531 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1118 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.506075 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.188090 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1112 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514385 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.202047 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22536 75.22% 75.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4135 13.80% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1423 4.75% 93.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 788 2.63% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 331 1.10% 97.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 258 0.86% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 318 1.06% 99.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.24% 99.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22110 75.01% 75.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4076 13.83% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1418 4.81% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 772 2.62% 96.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 337 1.14% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 264 0.90% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 327 1.11% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.24% 99.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 100 0.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29476 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -272,68 +272,68 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 100 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 53914 # The number of ROB reads -system.cpu.rob.rob_writes 51717 # The number of ROB writes -system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8649 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 53246 # The number of ROB reads +system.cpu.rob.rob_writes 51332 # The number of ROB writes +system.cpu.timesIdled 190 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8360 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 2.809088 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.809088 # CPI: Total CPI of All Threads -system.cpu.ipc 0.355987 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.355987 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32709 # number of integer regfile reads -system.cpu.int_regfile_writes 18169 # number of integer regfile writes -system.cpu.misc_regfile_reads 7069 # number of misc regfile reads +system.cpu.cpi 2.754156 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.754156 # CPI: Total CPI of All Threads +system.cpu.ipc 0.363088 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.363088 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32578 # number of integer regfile reads +system.cpu.int_regfile_writes 18091 # number of integer regfile writes +system.cpu.misc_regfile_reads 7032 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 199.209373 # Cycle average of tags in use -system.cpu.icache.total_refs 5019 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.805310 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 199.192019 # Cycle average of tags in use +system.cpu.icache.total_refs 5061 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15.017804 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 199.209373 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.097270 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.097270 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5019 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5019 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5019 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5019 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5019 # number of overall hits -system.cpu.icache.overall_hits::total 5019 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses -system.cpu.icache.overall_misses::total 479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16863000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16863000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16863000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16863000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16863000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16863000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5498 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5498 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5498 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5498 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5498 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5498 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087123 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.087123 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.087123 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.087123 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.087123 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.087123 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35204.592902 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35204.592902 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35204.592902 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35204.592902 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35204.592902 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35204.592902 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 199.192019 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.097262 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.097262 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5061 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5061 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5061 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5061 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5061 # number of overall hits +system.cpu.icache.overall_hits::total 5061 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 484 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 484 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 484 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 484 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 484 # number of overall misses +system.cpu.icache.overall_misses::total 484 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16465500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16465500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16465500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16465500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16465500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16465500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5545 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5545 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5545 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5545 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087286 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.087286 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.087286 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.087286 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.087286 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.087286 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34019.628099 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34019.628099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34019.628099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34019.628099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,56 +342,56 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 140 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 140 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 140 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 140 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 140 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 140 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12213000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12213000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12213000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12213000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12213000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12213000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061659 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.061659 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.061659 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36026.548673 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36026.548673 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060775 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.060775 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.060775 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36034.124629 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36034.124629 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36034.124629 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36034.124629 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36034.124629 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36034.124629 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.759786 # Cycle average of tags in use -system.cpu.dcache.total_refs 4074 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 103.051665 # Cycle average of tags in use +system.cpu.dcache.total_refs 4061 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.904110 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.815068 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.759786 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025088 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025088 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3035 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 103.051665 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025159 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025159 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3022 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3022 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4068 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4068 # number of overall hits -system.cpu.dcache.overall_hits::total 4068 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 4055 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4055 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4055 # number of overall hits +system.cpu.dcache.overall_hits::total 4055 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses @@ -400,40 +400,40 @@ system.cpu.dcache.demand_misses::cpu.data 530 # n system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses system.cpu.dcache.overall_misses::total 530 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4649500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17651000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17651000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22300500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22300500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22300500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22300500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4244000 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038498 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.038498 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115268 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115268 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115268 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38425.619835 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38425.619835 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43156.479218 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43156.479218 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42076.415094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42076.415094 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.115594 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115594 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35074.380165 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35074.380165 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38009.779951 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38009.779951 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37339.622642 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37339.622642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37339.622642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37339.622642 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -458,103 +458,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5811000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5811000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5811000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5811000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2501000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2501000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5823000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5823000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5823000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5823000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020045 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020045 # 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average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031843 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031843 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031843 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031843 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39698.412698 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39698.412698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40024.096386 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40024.096386 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39883.561644 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 39883.561644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39883.561644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 39883.561644 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 234.457580 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 234.574534 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005025 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 198.470180 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 35.987400 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.006057 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001098 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.007155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 198.449350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 36.125184 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.006056 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001102 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.007159 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 337 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses +system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses -system.cpu.l2cache.overall_misses::total 483 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11867000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2431500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14298500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3194500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3194500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11867000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5626000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17493000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11867000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5626000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17493000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 481 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2437500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14242000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3238000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3238000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11804500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5675500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11804500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5675500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17480000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 400 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 337 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994100 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994065 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995000 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994100 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.995859 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35213.649852 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38595.238095 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35746.250000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38487.951807 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38487.951807 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35213.649852 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38534.246575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36217.391304 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35213.649852 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38534.246575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36217.391304 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995859 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35237.313433 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38690.476190 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35783.919598 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39012.048193 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39012.048193 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35237.313433 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38873.287671 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36340.956341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35237.313433 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38873.287671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36340.956341 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,50 +563,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10794500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2238500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13033000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2937500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2937500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10794500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5176000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15970500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10794500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5176000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15970500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10738000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2244000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12982000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2981500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2981500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10738000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5225500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15963500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10738000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5225500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15963500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995859 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32031.157270 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35531.746032 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32582.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35391.566265 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35391.566265 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32031.157270 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35452.054795 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33065.217391 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32031.157270 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35452.054795 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33065.217391 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995859 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32053.731343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35619.047619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32618.090452 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35921.686747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35921.686747 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32053.731343 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35791.095890 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33188.149688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32053.731343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35791.095890 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33188.149688 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 4464561a4..af9b5d77e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000043 # Number of seconds simulated -sim_ticks 43106000 # Number of ticks simulated -final_tick 43106000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000041 # Number of seconds simulated +sim_ticks 41368000 # Number of ticks simulated +final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377775 # Simulator instruction rate (inst/s) -host_op_rate 377609 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1073121241 # Simulator tick rate (ticks/s) -host_mem_usage 229408 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 652409 # Simulator instruction rate (inst/s) +host_op_rate 651936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1777530278 # Simulator tick rate (ticks/s) +host_mem_usage 220352 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 412749965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 204890270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 617640236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 412749965 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 412749965 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 412749965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 204890270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 617640236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 86212 # number of cpu cycles simulated +system.cpu.numCycles 82736 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 86212 # Number of busy cycles +system.cpu.num_busy_cycles 82736 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 152.957781 # Cycle average of tags in use +system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use system.cpu.icache.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 152.957781 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074686 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074686 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15596000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15596000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15596000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15596000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15596000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15596000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55700 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.669722 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.669722 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023845 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023845 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits @@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2968000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2968000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4760000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4760000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -231,16 +231,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 183.688794 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 152.283537 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.405257 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000958 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005606 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits |