diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/quick/se/02.insttest/ref/sparc | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/quick/se/02.insttest/ref/sparc')
| -rw-r--r-- | tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt | 433 | ||||
| -rw-r--r-- | tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 684 |
2 files changed, 580 insertions, 537 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 4c8817e23..260a10b90 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27705000 # Number of ticks simulated -final_tick 27705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27725000 # Number of ticks simulated +final_tick 27725000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 23200 # Simulator instruction rate (inst/s) -host_op_rate 23199 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42390050 # Simulator tick rate (ticks/s) -host_mem_usage 236824 # Number of bytes of host memory used -host_seconds 0.65 # Real time elapsed on the host +host_inst_rate 72342 # Simulator instruction rate (inst/s) +host_op_rate 72337 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132265036 # Simulator tick rate (ticks/s) +host_mem_usage 269700 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19008 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory -system.physmem.bytes_read::total 27904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 27840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 297 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory -system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 688395596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 318787223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1007182819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 688395596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 688395596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 688395596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 318787223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1007182819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 435 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 685590622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 318557259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1004147881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 685590622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 685590622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 685590622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 318557259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1004147881 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27671500 # Total gap between requests +system.physmem.totGap 27691500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 117 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -154,55 +154,76 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.743118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 502.320204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 21 32.81% 32.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 10 15.62% 48.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5 7.81% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 8 12.50% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 3.12% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2 3.12% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2 3.12% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.56% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1 1.56% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.56% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.56% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.56% 85.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 3.12% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 2 3.12% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 1 1.56% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 1 1.56% 95.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 3.12% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 1 1.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation -system.physmem.totQLat 2393750 # Total ticks spent queuing -system.physmem.totMemAccLat 10830000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 487.111111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 330.231493 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 390.430808 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3 8.33% 8.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9 25.00% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 22.22% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 5.56% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 5.56% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 2.78% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 30.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation +system.physmem.totQLat 2136500 # Total ticks spent queuing +system.physmem.totMemAccLat 10682750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6256250 # Total ticks spent accessing banks -system.physmem.avgQLat 5490.25 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14349.20 # Average bank access latency per DRAM burst +system.physmem.totBankLat 6366250 # Total ticks spent accessing banks +system.physmem.avgQLat 4900.23 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14601.49 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24839.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1007.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24501.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1006.46 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1007.18 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1006.46 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.87 # Data bus utilization in percentage -system.physmem.busUtilRead 7.87 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.86 # Data bus utilization in percentage +system.physmem.busUtilRead 7.86 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.39 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 372 # Number of row buffer hits during reads +system.physmem.readRowHits 362 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.32 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.03 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 63466.74 # Average gap between requests -system.physmem.pageHitRate 85.32 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.29 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1004872767 # Throughput (bytes/s) +system.physmem.avgGap 63512.61 # Average gap between requests +system.physmem.pageHitRate 83.03 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.51 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1004147881 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution @@ -213,9 +234,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 27840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4048750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4047500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 5146 # Number of BP lookups @@ -228,7 +249,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 55411 # number of cpu cycles simulated +system.cpu.numCycles 55451 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -250,12 +271,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21832 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21862 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 436 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 37843 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 439 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 37883 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 31.704896 # Percentage of cycles cpu is active +system.cpu.activity 31.682026 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -267,39 +288,39 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.654597 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.657235 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.654597 # CPI: Total CPI of All Threads -system.cpu.ipc 0.273628 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.657235 # CPI: Total CPI of All Threads +system.cpu.ipc 0.273431 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.273628 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 41985 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.273431 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 42025 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.229846 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46058 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.212368 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46098 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 16.879320 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46608 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 16.867144 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46648 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 15.886737 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 52533 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 15.875277 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 52573 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.193915 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46102 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.190168 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46142 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 16.799913 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 16.787795 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 169.234439 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 168.846335 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 169.234439 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082634 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 168.846335 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082444 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082444 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.145996 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 7069 # Number of tag accesses system.cpu.icache.tags.data_accesses 7069 # Number of data accesses @@ -315,12 +336,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26803000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26803000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26803000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26803000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26803000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26803000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25942000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25942000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25942000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25942000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25942000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25942000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -333,12 +354,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70349.081365 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70349.081365 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70349.081365 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70349.081365 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68089.238845 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68089.238845 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68089.238845 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68089.238845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68089.238845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68089.238845 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,26 +380,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20772000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20772000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20772000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20772000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20772000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20772000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20512000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20512000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20512000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20512000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20512000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20512000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69009.966777 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69009.966777 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68146.179402 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68146.179402 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68146.179402 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68146.179402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68146.179402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68146.179402 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1009492871 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1008764653 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -393,21 +414,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 501000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 499500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 221750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 221500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 200.306060 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.869816 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.564740 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.741320 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005144 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006113 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.179067 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.690749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005132 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000967 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006100 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id @@ -431,17 +452,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20448500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3701250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24149750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5902500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5902500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20448500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9603750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30052250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20448500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9603750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30052250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20188500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3701000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23889500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6006500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6006500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20188500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9707500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29896000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20188500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9707500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29896000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -464,17 +485,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68389.632107 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69834.905660 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68607.244318 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69441.176471 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69441.176471 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68769.450801 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68769.450801 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67520.066890 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69830.188679 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67867.897727 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70664.705882 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70664.705882 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67520.066890 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70344.202899 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68411.899314 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67520.066890 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70344.202899 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68411.899314 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -494,17 +515,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16729000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3042250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19771250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4860000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4860000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16729000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7902250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24631250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16729000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7902250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24631250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16473000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3042500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19515500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4962500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4962500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16473000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8005000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24478000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16473000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8005000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24478000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -516,27 +537,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55949.832776 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57400.943396 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56168.323864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57176.470588 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57176.470588 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55093.645485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57405.660377 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55441.761364 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58382.352941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58382.352941 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55093.645485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58007.246377 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56013.729977 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55093.645485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58007.246377 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56013.729977 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.671839 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.543212 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.671839 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024090 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024090 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.543212 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024058 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024058 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -561,14 +582,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4274250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4274250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25400750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25400750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29675000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29675000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29675000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29675000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4273500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4273500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25910250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25910250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30183750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30183750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30183750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30183750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -587,19 +608,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73693.965517 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73693.965517 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60191.350711 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60191.350711 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61822.916667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61822.916667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73681.034483 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73681.034483 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61398.696682 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61398.696682 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62882.812500 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62882.812500 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62882.812500 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62882.812500 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1097 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.969697 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.242424 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -619,14 +640,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3755750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3755750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5990500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5990500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9746250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9746250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9746250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9746250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3755500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3755500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6094500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6094500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9850000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9850000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9850000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9850000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -635,14 +656,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70863.207547 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70863.207547 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70476.470588 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70476.470588 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70858.490566 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70858.490566 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71700 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71700 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71376.811594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71376.811594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71376.811594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71376.811594 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 7bcabaaf6..48a264b11 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 26616500 # Number of ticks simulated -final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26743500 # Number of ticks simulated +final_tick 26743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19079 # Simulator instruction rate (inst/s) -host_op_rate 19079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35176168 # Simulator tick rate (ticks/s) -host_mem_usage 237844 # Number of bytes of host memory used -host_seconds 0.76 # Real time elapsed on the host +host_inst_rate 53060 # Simulator instruction rate (inst/s) +host_op_rate 53057 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98286640 # Simulator tick rate (ticks/s) +host_mem_usage 272776 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 805515376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 353464956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1158980332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 805515376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 805515376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 805515376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 353464956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1158980332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 801690130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 351786415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1153476546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 801690130 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 801690130 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 801690130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 351786415 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1153476546 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 482 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26455500 # Total gap between requests +system.physmem.totGap 26582500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -154,55 +154,77 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 386.782609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.135099 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 508.628284 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 23 33.33% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 10 14.49% 47.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 13.04% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 6 8.70% 69.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 2.90% 72.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2 2.90% 75.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 2.90% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 2 2.90% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.45% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.45% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 2 2.90% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 1.45% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 2.90% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.45% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 1 1.45% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 1 1.45% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 2.90% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 1 1.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation -system.physmem.totQLat 2423000 # Total ticks spent queuing -system.physmem.totMemAccLat 11611750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 298.774659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 377.002918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5 12.20% 12.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12 29.27% 41.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 17.07% 58.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 4.88% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 4.88% 68.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 2.44% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 4.88% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 24.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation +system.physmem.totQLat 2269000 # Total ticks spent queuing +system.physmem.totMemAccLat 11609000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6778750 # Total ticks spent accessing banks -system.physmem.avgQLat 5026.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14063.80 # Average bank access latency per DRAM burst +system.physmem.totBankLat 6930000 # Total ticks spent accessing banks +system.physmem.avgQLat 4707.47 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14377.59 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24090.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1158.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24085.06 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1153.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1158.98 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1153.48 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.05 # Data bus utilization in percentage -system.physmem.busUtilRead 9.05 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.01 # Data bus utilization in percentage +system.physmem.busUtilRead 9.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.44 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 413 # Number of row buffer hits during reads +system.physmem.readRowHits 403 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.68 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54886.93 # Average gap between requests -system.physmem.pageHitRate 85.68 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.39 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1158980332 # Throughput (bytes/s) +system.physmem.avgGap 55150.41 # Average gap between requests +system.physmem.pageHitRate 83.61 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.72 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1153476546 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution @@ -213,105 +235,105 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 16.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4495000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 16.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 6713 # Number of BP lookups -system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted +system.cpu.branchPred.lookups 6710 # Number of BP lookups +system.cpu.branchPred.condPredicted 4453 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5019 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 5017 # Number of BTB lookups system.cpu.branchPred.BTBHits 2432 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.455868 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.475184 # BTB Hit Percentage system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 53234 # number of cpu cycles simulated +system.cpu.numCycles 53488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12410 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31113 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 12425 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31097 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6710 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9131 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8795 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 9129 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3043 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 9229 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched +system.cpu.fetch.CacheLines 5378 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33133 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.939034 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.131220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 33579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.926085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.119056 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24002 72.44% 72.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4510 13.61% 86.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 474 1.43% 87.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 392 1.18% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 680 2.05% 90.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 706 2.13% 92.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 253 0.76% 94.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1881 5.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24450 72.81% 72.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4510 13.43% 86.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 474 1.41% 87.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 392 1.17% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 680 2.03% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 706 2.10% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.70% 93.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 253 0.75% 94.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1879 5.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33133 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126104 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.584457 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12933 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9787 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8343 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13575 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8758 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7952 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 33579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125449 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.581383 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12934 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 10235 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8342 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1871 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 28992 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1871 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13577 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 435 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9274 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7946 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 476 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 26641 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 40918 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 148 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 23939 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49429 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 40899 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10120 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2745 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3528 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2282 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22511 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21122 # Number of instructions issued +system.cpu.iq.iqInstsIssued 21117 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 7892 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5484 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33133 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.637491 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.262113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 33579 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.628875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.255627 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23891 72.11% 72.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3555 10.73% 82.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2321 7.01% 89.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1704 5.14% 94.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 887 2.68% 97.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24339 72.48% 72.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3553 10.58% 83.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2322 6.92% 89.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1704 5.07% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 887 2.64% 97.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 469 1.40% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 240 0.71% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.13% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33579 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available @@ -347,7 +369,7 @@ system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15651 74.10% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15648 74.10% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued @@ -377,39 +399,39 @@ system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2107 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21122 # Type of FU issued -system.cpu.iq.rate 0.396776 # Inst issue rate +system.cpu.iq.FU_type_0::total 21117 # Type of FU issued +system.cpu.iq.rate 0.394799 # Inst issue rate system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75621 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.006961 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 76057 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31084 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21269 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21264 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1303 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 834 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 359 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24307 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1871 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 286 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 399 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 3528 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2282 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -419,41 +441,41 @@ system.cpu.iew.predictedNotTakenIncorrect 946 # N system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1048 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1043 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1134 # number of nop insts executed +system.cpu.iew.exec_nop 1133 # number of nop insts executed system.cpu.iew.exec_refs 5224 # number of memory reference insts executed system.cpu.iew.exec_branches 4239 # Number of branches executed system.cpu.iew.exec_stores 2022 # Number of stores executed -system.cpu.iew.exec_rate 0.377090 # Inst execution rate +system.cpu.iew.exec_rate 0.375299 # Inst execution rate system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit system.cpu.iew.wb_count 19522 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9120 # num instructions producing a value -system.cpu.iew.wb_consumers 11235 # num instructions consuming a value +system.cpu.iew.wb_producers 9122 # num instructions producing a value +system.cpu.iew.wb_consumers 11233 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.366721 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back +system.cpu.iew.wb_rate 0.364979 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.812072 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31261 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.183057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 31708 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.478176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.176132 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23946 76.60% 76.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4068 13.01% 89.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 764 2.44% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 348 1.11% 97.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 24394 76.93% 76.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4067 12.83% 89.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1357 4.28% 94.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 765 2.41% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 348 1.10% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 270 0.85% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 322 1.02% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.21% 99.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31261 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31708 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -466,22 +488,22 @@ system.cpu.commit.int_insts 12174 # Nu system.cpu.commit.function_calls 187 # Number of function calls committed. system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54530 # The number of ROB reads -system.cpu.rob.rob_writes 50298 # The number of ROB writes -system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20101 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54969 # The number of ROB reads +system.cpu.rob.rob_writes 50281 # The number of ROB writes +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19909 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.687587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.687587 # CPI: Total CPI of All Threads -system.cpu.ipc 0.271180 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.271180 # IPC: Total IPC of All Threads +system.cpu.cpi 3.705181 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.705181 # CPI: Total CPI of All Threads +system.cpu.ipc 0.269892 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.269892 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 32043 # number of integer regfile reads system.cpu.int_regfile_writes 17841 # number of integer regfile writes system.cpu.misc_regfile_reads 6919 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1163789379 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1158262755 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution @@ -496,61 +518,61 @@ system.cpu.toL2Bus.data_through_bus 30976 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 564500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 562250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 233750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 187.514405 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 187.339200 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4870 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.451039 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 187.339200 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091474 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091474 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.164551 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11095 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11095 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits -system.cpu.icache.overall_hits::total 4872 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses -system.cpu.icache.overall_misses::total 507 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31694500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31694500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31694500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31694500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31694500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31694500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62513.806706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62513.806706 # average overall miss latency +system.cpu.icache.tags.tag_accesses 11093 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11093 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4870 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4870 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4870 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4870 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4870 # number of overall hits +system.cpu.icache.overall_hits::total 4870 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 508 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 508 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 508 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 508 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 508 # number of overall misses +system.cpu.icache.overall_misses::total 508 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31654500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31654500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31654500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31654500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5378 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5378 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5378 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5378 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094459 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094459 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094459 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094459 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094459 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094459 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62312.007874 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62312.007874 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62312.007874 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62312.007874 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62312.007874 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62312.007874 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -559,48 +581,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 170 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 170 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 170 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 170 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 171 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 171 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 171 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 171 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 171 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22488500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22488500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22488500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22488500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22488500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22488500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22543250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22543250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22543250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22543250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22543250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22543250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062663 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.062663 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.062663 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66893.916914 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66893.916914 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66893.916914 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66893.916914 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66893.916914 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66893.916914 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.363231 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.171170 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.907225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.732473 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.438696 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005699 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001051 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006750 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id @@ -624,17 +646,17 @@ system.cpu.l2cache.demand_misses::total 482 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 482 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22131500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5102250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27233750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5727000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5727000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22131500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10829250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32960750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22131500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10829250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32960750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22186250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4642250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 26828500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6101000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6101000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22186250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10743250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32929500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22186250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10743250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32929500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) @@ -657,17 +679,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995868 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66227.611940 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72535.156250 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67239.348371 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73506.024096 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73506.024096 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66227.611940 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73083.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68318.464730 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66227.611940 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73083.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68318.464730 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -687,17 +709,17 @@ system.cpu.l2cache.demand_mshr_misses::total 482 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17918000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4316250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22234250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4712000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4712000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17918000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9028250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26946250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17918000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9028250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26946250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17979250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3856250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21835500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5083000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5083000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17979250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8939250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17979250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8939250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26918500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses @@ -709,27 +731,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53669.402985 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60253.906250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54725.563910 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61240.963855 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61240.963855 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53669.402985 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60811.224490 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55847.510373 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53669.402985 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.224490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55847.510373 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.106073 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 99.038544 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 99.038544 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024179 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024179 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id @@ -754,14 +776,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8431750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8431750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24708724 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24708724 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33140474 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33140474 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33140474 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33140474 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7972250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7972250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25777976 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25777976 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33750226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33750226 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33750226 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33750226 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -780,19 +802,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61944.811215 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61944.811215 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63271.825397 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63271.825397 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63026.836186 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63026.836186 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63084.534579 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63084.534579 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63084.534579 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63084.534579 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.035714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.461538 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -812,14 +834,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5166750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5166750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5811000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5811000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10977750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10977750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10977750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10977750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4706750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4706750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6185000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6185000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10891750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10891750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10891750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10891750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -828,14 +850,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73542.968750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73542.968750 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74518.072289 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74518.072289 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74093.537415 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74093.537415 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74093.537415 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74093.537415 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |