diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-08-15 10:38:05 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-08-15 10:38:05 -0400 |
| commit | 73e9e923d00c6f5df9e79a6c40ecc159894d2bc5 (patch) | |
| tree | f84188c6697fe79f0521b73d9d38855ce7e04d29 /tests/quick/se/02.insttest/ref | |
| parent | dd1b346584e520ba970e62aa3bcc7d32828cdeba (diff) | |
| download | gem5-73e9e923d00c6f5df9e79a6c40ecc159894d2bc5.tar.xz | |
stats: Update stats for syscall emulation Linux kernel changes.
Diffstat (limited to 'tests/quick/se/02.insttest/ref')
12 files changed, 620 insertions, 620 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini index 09d24317c..122f72766 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -214,7 +214,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index 6fbf990e1..e5fdf01a9 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 11:30:48 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:17 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 25615500 because target called exit() +Exiting @ tick 25614500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index c2589ee2d..2b7ec11ce 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25615500 # Number of ticks simulated -final_tick 25615500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25614500 # Number of ticks simulated +final_tick 25614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51797 # Simulator instruction rate (inst/s) -host_op_rate 51795 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87424707 # Simulator tick rate (ticks/s) -host_mem_usage 219936 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host -sim_insts 15175 # Number of instructions simulated -sim_ops 15175 # Number of ops (including micro ops) simulated +host_inst_rate 72825 # Simulator instruction rate (inst/s) +host_op_rate 72819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 123010334 # Simulator tick rate (ticks/s) +host_mem_usage 229416 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +sim_insts 15162 # Number of instructions simulated +sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory system.physmem.bytes_read::total 27904 # Number of bytes read from this memory @@ -19,128 +19,128 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 744549199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 344791240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1089340438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 744549199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 744549199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 744549199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 344791240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1089340438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 744578266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 344804700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1089382967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 744578266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 744578266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 744578266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 344804700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1089382967 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 51232 # number of cpu cycles simulated +system.cpu.numCycles 51230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 5014 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 3353 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 2379 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 3331 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 2040 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 174 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 5020 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 3412 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 3517 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2141 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 61.242870 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 2214 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2800 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 14401 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 25512 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.branch_predictor.BTBHitPct 60.875746 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 2317 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 2703 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 14367 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 25466 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 4991 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3950 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 1316 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1000 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 2316 # Number of Branches Incorrectly Predicted +system.cpu.regfile_manager.regForwards 5027 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3931 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 1367 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 948 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 2315 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 1043 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 68.949092 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 11084 # Number of Instructions Executed. +system.cpu.execution_unit.mispredictPct 68.939845 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 11058 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches system.cpu.threadCycles 22262 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 525 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33883 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17349 # Number of cycles cpu stages are processed. -system.cpu.activity 33.863601 # Percentage of cycles cpu is active -system.cpu.comLoads 2226 # Number of Load instructions committed +system.cpu.timesIdled 524 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33874 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17356 # Number of cycles cpu stages are processed. +system.cpu.activity 33.878587 # Percentage of cycles cpu is active +system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed -system.cpu.comBranches 3359 # Number of Branches instructions committed +system.cpu.comBranches 3358 # Number of Branches instructions committed system.cpu.comNops 726 # Number of Nop instructions committed system.cpu.comNonSpec 222 # Number of Non-Speculative instructions committed -system.cpu.comInts 7177 # Number of Integer instructions committed +system.cpu.comInts 7166 # Number of Integer instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 15175 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 15175 # Number of Ops committed (Per-Thread) +system.cpu.committedInsts 15162 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 15175 # Number of Instructions committed (Total) -system.cpu.cpi 3.376079 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) +system.cpu.cpi 3.378842 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.376079 # CPI: Total CPI of All Threads -system.cpu.ipc 0.296202 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.378842 # CPI: Total CPI of All Threads +system.cpu.ipc 0.295959 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.296202 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 38139 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 13093 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 25.556293 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 42033 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9199 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.955575 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 42406 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8826 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 17.227514 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48347 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 2885 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.631246 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41905 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9327 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 18.205418 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.295959 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 38098 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 25.633418 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 42042 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 17.934804 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 42414 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 17.208667 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48346 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 5.629514 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41913 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9317 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 18.186609 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 164.555255 # Cycle average of tags in use -system.cpu.icache.total_refs 2600 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 164.536889 # Cycle average of tags in use +system.cpu.icache.total_refs 2586 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.695652 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 164.555255 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080349 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080349 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 2600 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2600 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2600 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2600 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2600 # number of overall hits -system.cpu.icache.overall_hits::total 2600 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses -system.cpu.icache.overall_misses::total 371 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20687000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20687000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20687000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20687000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20687000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20687000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2971 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2971 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2971 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2971 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124874 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124874 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124874 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124874 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124874 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124874 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55760.107817 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55760.107817 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55760.107817 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55760.107817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55760.107817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55760.107817 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 164.536889 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080340 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080340 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2586 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2586 # number of overall hits +system.cpu.icache.overall_hits::total 2586 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses +system.cpu.icache.overall_misses::total 369 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20585000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20585000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20585000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20585000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20585000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20585000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2955 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2955 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2955 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124873 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124873 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124873 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55785.907859 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55785.907859 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55785.907859 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55785.907859 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55785.907859 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55785.907859 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -149,56 +149,56 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16327000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16327000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16327000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16327000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16327000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16327000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101313 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101313 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101313 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.101313 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101313 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.101313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54242.524917 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54242.524917 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54242.524917 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54242.524917 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54242.524917 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54242.524917 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16326500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16326500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16326500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16326500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16326500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16326500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54240.863787 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54240.863787 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54240.863787 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54240.863787 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54240.863787 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54240.863787 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 96.551113 # Cycle average of tags in use -system.cpu.dcache.total_refs 3315 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 96.547387 # Cycle average of tags in use +system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 24.021739 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 96.551113 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023572 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023572 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 2168 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2168 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 96.547387 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023571 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023571 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1141 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3309 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3309 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3309 # number of overall hits -system.cpu.dcache.overall_hits::total 3309 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 3308 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3308 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3308 # number of overall hits +system.cpu.dcache.overall_hits::total 3308 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 301 # number of WriteReq misses @@ -215,24 +215,24 @@ system.cpu.dcache.demand_miss_latency::cpu.data 21946000 system.cpu.dcache.demand_miss_latency::total 21946000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 21946000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 21946000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3668 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3668 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.026056 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208738 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.208738 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097874 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097874 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097874 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097874 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.097900 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60137.931034 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 60137.931034 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61322.259136 # average WriteReq miss latency @@ -273,14 +273,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7717500 system.cpu.dcache.demand_mshr_miss_latency::total 7717500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7717500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7717500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56367.924528 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56367.924528 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55647.058824 # average WriteReq mshr miss latency @@ -291,16 +291,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55923.913043 system.cpu.dcache.overall_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.062761 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.042677 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 163.946873 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.115888 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 163.928542 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.114135 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000950 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005953 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005952 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -318,17 +318,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15990000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15989500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2926500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18916500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18916000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4635000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4635000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15990000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15989500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7561500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23551500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15990000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 23551000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15989500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7561500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23551500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23551000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -351,17 +351,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53478.260870 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53476.588629 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55216.981132 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53740.056818 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53738.636364 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54529.411765 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54529.411765 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53478.260870 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53476.588629 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53893.592677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53478.260870 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53892.448513 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53476.588629 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53893.592677 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53892.448513 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index f6619bb03..c2f5f7c25 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -512,7 +512,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 47b15000f..d7d566072 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 11:30:59 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:20 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 20274500 because target called exit() +Exiting @ tick 20275500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 49a67051b..37adfc3c4 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20274500 # Number of ticks simulated -final_tick 20274500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20275500 # Number of ticks simulated +final_tick 20275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55162 # Simulator instruction rate (inst/s) -host_op_rate 55159 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77392529 # Simulator tick rate (ticks/s) -host_mem_usage 220968 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host -sim_insts 14449 # Number of instructions simulated -sim_ops 14449 # Number of ops (including micro ops) simulated +host_inst_rate 60587 # Simulator instruction rate (inst/s) +host_op_rate 60583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85082969 # Simulator tick rate (ticks/s) +host_mem_usage 230436 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host +sim_insts 14436 # Number of instructions simulated +sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory system.physmem.bytes_read::total 30912 # Number of bytes read from this memory @@ -19,323 +19,323 @@ system.physmem.bytes_inst_read::total 21568 # Nu system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1063799354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 460874498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524673851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1063799354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1063799354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1063799354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 460874498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524673851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1063746887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 460851767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1524598654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1063746887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1063746887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1063746887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 460851767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1524598654 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 40550 # number of cpu cycles simulated +system.cpu.numCycles 40552 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6892 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4586 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1120 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5125 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2600 # Number of BTB hits +system.cpu.BPredUnit.lookups 6886 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4580 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1118 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5120 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2601 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 458 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12259 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 32259 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6892 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3058 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9557 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3181 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 12252 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 32221 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6886 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3059 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9555 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3174 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 7365 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 767 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5500 # Number of cache lines fetched +system.cpu.fetch.CacheLines 5498 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 31917 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.010715 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.185460 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 31903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.009968 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.184021 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22360 70.06% 70.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4750 14.88% 84.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 493 1.54% 86.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 436 1.37% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 686 2.15% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 773 2.42% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.74% 93.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 276 0.86% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1908 5.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22348 70.05% 70.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4753 14.90% 84.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 493 1.55% 86.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 436 1.37% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 686 2.15% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 773 2.42% 92.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 236 0.74% 93.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 275 0.86% 94.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1903 5.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 31917 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.169963 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.795536 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12903 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 31903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.169807 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.794560 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12897 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 8133 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8719 # Number of cycles decode is running +system.cpu.decode.RunCycles 8716 # Number of cycles decode is running system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1965 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30080 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1965 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13582 # Number of cycles rename is idle +system.cpu.decode.SquashCycles 1960 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 30041 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1960 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13576 # Number of cycles rename is idle system.cpu.rename.BlockCycles 285 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 7298 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8277 # Number of cycles rename is running +system.cpu.rename.RunCycles 8274 # Number of cycles rename is running system.cpu.rename.UnblockCycles 510 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27385 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 27346 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 172 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24421 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 50913 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 50913 # Number of integer rename lookups -system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10589 # Number of HB maps that are undone due to squashing +system.cpu.rename.RenamedOperands 24383 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 50854 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 50854 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 10564 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 704 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 2903 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3640 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2472 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 3638 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2471 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23148 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 23123 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 669 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21730 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8364 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5915 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21711 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8357 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5906 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 194 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 31917 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.680828 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.297413 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 31903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.680532 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.296567 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 22417 70.24% 70.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3682 11.54% 81.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2373 7.43% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1722 5.40% 94.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 904 2.83% 97.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 493 1.54% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 244 0.76% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 65 0.20% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 22407 70.23% 70.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3681 11.54% 81.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2373 7.44% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1722 5.40% 94.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 903 2.83% 97.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 494 1.55% 98.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 242 0.76% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 64 0.20% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 31917 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 31903 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 46 26.59% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 13.87% 40.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 103 59.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45 26.16% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24 13.95% 40.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 103 59.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16031 73.77% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3433 15.80% 89.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2266 10.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16013 73.76% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2266 10.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21730 # Type of FU issued -system.cpu.iq.rate 0.535882 # Inst issue rate -system.cpu.iq.fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007961 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75658 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32207 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19957 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21711 # Type of FU issued +system.cpu.iq.rate 0.535387 # Inst issue rate +system.cpu.iq.fu_busy_cnt 172 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007922 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75603 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32175 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19936 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21903 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21883 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1414 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1413 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1024 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1023 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1965 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1960 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 99 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24982 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 417 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3640 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2472 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 24957 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 410 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3638 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2471 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 669 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 291 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 958 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20553 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3273 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1177 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 290 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 957 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1247 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20532 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3272 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1179 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1165 # number of nop insts executed -system.cpu.iew.exec_refs 5419 # number of memory reference insts executed -system.cpu.iew.exec_branches 4294 # Number of branches executed +system.cpu.iew.exec_refs 5418 # number of memory reference insts executed +system.cpu.iew.exec_branches 4292 # Number of branches executed system.cpu.iew.exec_stores 2146 # Number of stores executed -system.cpu.iew.exec_rate 0.506856 # Inst execution rate -system.cpu.iew.wb_sent 20221 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19957 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9257 # num instructions producing a value -system.cpu.iew.wb_consumers 11359 # num instructions consuming a value +system.cpu.iew.exec_rate 0.506313 # Inst execution rate +system.cpu.iew.wb_sent 20199 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19936 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9239 # num instructions producing a value +system.cpu.iew.wb_consumers 11338 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.492158 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.814948 # average fanout of values written-back +system.cpu.iew.wb_rate 0.491616 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.814870 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions -system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9725 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 15162 # The number of committed instructions +system.cpu.commit.commitCommittedOps 15162 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9713 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1120 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29969 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.506357 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.189037 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1118 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.506075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.188090 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22543 75.22% 75.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4136 13.80% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1421 4.74% 93.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 789 2.63% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 331 1.10% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 259 0.86% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22536 75.22% 75.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4135 13.80% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1423 4.75% 93.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 788 2.63% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 331 1.10% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 258 0.86% 98.37% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 318 1.06% 99.43% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 73 0.24% 99.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 99 0.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29969 # Number of insts commited each cycle -system.cpu.commit.committedInsts 15175 # Number of instructions committed -system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 29960 # Number of insts commited each cycle +system.cpu.commit.committedInsts 15162 # Number of instructions committed +system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 3674 # Number of memory references committed -system.cpu.commit.loads 2226 # Number of loads committed +system.cpu.commit.refs 3673 # Number of memory references committed +system.cpu.commit.loads 2225 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 3359 # Number of branches committed +system.cpu.commit.branches 3358 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 12186 # Number of committed integer instructions. +system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 99 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 53947 # The number of ROB reads -system.cpu.rob.rob_writes 51773 # The number of ROB writes +system.cpu.rob.rob_reads 53914 # The number of ROB reads +system.cpu.rob.rob_writes 51717 # The number of ROB writes system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8633 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 14449 # Number of Instructions Simulated -system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.806423 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.806423 # CPI: Total CPI of All Threads -system.cpu.ipc 0.356326 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.356326 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32739 # number of integer regfile reads -system.cpu.int_regfile_writes 18191 # number of integer regfile writes -system.cpu.misc_regfile_reads 7070 # number of misc regfile reads +system.cpu.idleCycles 8649 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 14436 # Number of Instructions Simulated +system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 14436 # Number of Instructions Simulated +system.cpu.cpi 2.809088 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.809088 # CPI: Total CPI of All Threads +system.cpu.ipc 0.355987 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.355987 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32709 # number of integer regfile reads +system.cpu.int_regfile_writes 18169 # number of integer regfile writes +system.cpu.misc_regfile_reads 7069 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 199.218311 # Cycle average of tags in use -system.cpu.icache.total_refs 5020 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 199.209373 # Cycle average of tags in use +system.cpu.icache.total_refs 5019 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.808260 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 14.805310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 199.218311 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.097275 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.097275 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5020 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5020 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5020 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5020 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5020 # number of overall hits -system.cpu.icache.overall_hits::total 5020 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses -system.cpu.icache.overall_misses::total 480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16877500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16877500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16877500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16877500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16877500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16877500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5500 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5500 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5500 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5500 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087273 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.087273 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.087273 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.087273 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.087273 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.087273 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35161.458333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35161.458333 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35161.458333 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35161.458333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35161.458333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35161.458333 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 199.209373 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.097270 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.097270 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5019 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5019 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5019 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5019 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5019 # number of overall hits +system.cpu.icache.overall_hits::total 5019 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses +system.cpu.icache.overall_misses::total 479 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16863000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16863000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16863000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16863000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16863000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16863000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5498 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5498 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5498 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5498 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5498 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5498 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087123 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.087123 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.087123 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.087123 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.087123 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.087123 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35204.592902 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35204.592902 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35204.592902 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35204.592902 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35204.592902 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35204.592902 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,12 +344,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 141 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 141 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 141 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 141 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 141 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 141 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 140 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 140 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 140 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 140 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 140 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 140 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses @@ -362,12 +362,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12213000 system.cpu.icache.demand_mshr_miss_latency::total 12213000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12213000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12213000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061636 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.061636 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.061636 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061659 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.061659 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.061659 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36026.548673 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36026.548673 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency @@ -376,24 +376,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36026.548673 system.cpu.icache.overall_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.764065 # Cycle average of tags in use -system.cpu.dcache.total_refs 4075 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.759786 # Cycle average of tags in use +system.cpu.dcache.total_refs 4074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.910959 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.904110 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.764065 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025089 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025089 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3036 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3036 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 102.759786 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025088 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025088 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3035 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4069 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4069 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4069 # number of overall hits -system.cpu.dcache.overall_hits::total 4069 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 4068 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4068 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4068 # number of overall hits +system.cpu.dcache.overall_hits::total 4068 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses @@ -410,24 +410,24 @@ system.cpu.dcache.demand_miss_latency::cpu.data 22300500 system.cpu.dcache.demand_miss_latency::total 22300500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 22300500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 22300500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3157 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3157 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 3156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3156 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4599 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4599 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4599 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4599 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038328 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.038328 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4598 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4598 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4598 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4598 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038340 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.038340 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115242 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115242 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115242 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115242 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.115268 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115268 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115268 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115268 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38425.619835 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 38425.619835 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43156.479218 # average WriteReq miss latency @@ -468,14 +468,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5811000 system.cpu.dcache.demand_mshr_miss_latency::total 5811000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5811000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5811000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019956 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019956 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019962 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031746 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031746 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031746 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031746 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031753 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031753 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031753 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031753 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39968.253968 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39968.253968 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39674.698795 # average WriteReq mshr miss latency @@ -486,13 +486,13 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39801.369863 system.cpu.dcache.overall_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 234.467813 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 234.457580 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 198.479082 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 35.988731 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 198.470180 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 35.987400 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.006057 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001098 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.007155 # Average percentage of cache occupancy diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 9dd70f314..2d696d139 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -99,8 +99,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index 0a6c1bd0d..ffad57b6b 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:04 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:25 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 7618500 because target called exit() +Exiting @ tick 7612000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index a62ce7951..feda286ec 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000008 # Number of seconds simulated -sim_ticks 7618500 # Number of ticks simulated -final_tick 7618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 7612000 # Number of ticks simulated +final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 949089 # Simulator instruction rate (inst/s) -host_op_rate 948034 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 475431989 # Simulator tick rate (ticks/s) -host_mem_usage 212076 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 15175 # Number of instructions simulated -sim_ops 15175 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 60880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11343 # Number of bytes read from this memory -system.physmem.bytes_read::total 72223 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60880 # Number of instructions bytes read from this memory +host_inst_rate 1344667 # Simulator instruction rate (inst/s) +host_op_rate 1342613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 673049198 # Simulator tick rate (ticks/s) +host_mem_usage 220960 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +sim_insts 15162 # Number of instructions simulated +sim_ops 15162 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory +system.physmem.bytes_read::total 72170 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60828 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory system.physmem.bytes_written::total 9042 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2226 # Number of read requests responded to by this memory -system.physmem.num_reads::total 17446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 15207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2225 # Number of read requests responded to by this memory +system.physmem.num_reads::total 17432 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory system.physmem.num_other::total 6 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7991074358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1488875763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9479950121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7991074358 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7991074358 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1186847805 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1186847805 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7991074358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2675723568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10666797926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7991066737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1490015765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9481082501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7991066737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7991066737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1187861272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1187861272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 15238 # number of cpu cycles simulated +system.cpu.numCycles 15225 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 15175 # Number of instructions committed -system.cpu.committedOps 15175 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses +system.cpu.committedInsts 15162 # Number of instructions committed +system.cpu.committedOps 15162 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 385 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 2435 # number of instructions that are conditional controls -system.cpu.num_int_insts 12231 # number of integer instructions +system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls +system.cpu.num_int_insts 12219 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29059 # number of times the integer registers were read -system.cpu.num_int_register_writes 13832 # number of times the integer registers were written +system.cpu.num_int_register_reads 29037 # number of times the integer registers were read +system.cpu.num_int_register_writes 13819 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 3684 # number of memory refs -system.cpu.num_load_insts 2232 # Number of load instructions +system.cpu.num_mem_refs 3683 # number of memory refs +system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 15238 # Number of busy cycles +system.cpu.num_busy_cycles 15225 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index 10c1546b5..a7594cb67 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -181,7 +181,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index 71ca2d641..cacf98182 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 11:31:22 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:28 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 43120000 because target called exit() +Exiting @ tick 43106000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 54833842f..4464561a4 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000043 # Number of seconds simulated -sim_ticks 43120000 # Number of ticks simulated -final_tick 43120000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 43106000 # Number of ticks simulated +final_tick 43106000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107758 # Simulator instruction rate (inst/s) -host_op_rate 107745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 306125993 # Simulator tick rate (ticks/s) -host_mem_usage 219936 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host -sim_insts 15175 # Number of instructions simulated -sim_ops 15175 # Number of ops (including micro ops) simulated +host_inst_rate 377775 # Simulator instruction rate (inst/s) +host_op_rate 377609 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1073121241 # Simulator tick rate (ticks/s) +host_mem_usage 229408 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +sim_insts 15162 # Number of instructions simulated +sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory system.physmem.bytes_read::total 26624 # Number of bytes read from this memory @@ -19,52 +19,52 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 412615955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 204823748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 617439703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 412615955 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 412615955 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 412615955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 204823748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 617439703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 412749965 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 204890270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 617640236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 412749965 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 412749965 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 412749965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 204890270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 617640236 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 86240 # number of cpu cycles simulated +system.cpu.numCycles 86212 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 15175 # Number of instructions committed -system.cpu.committedOps 15175 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses +system.cpu.committedInsts 15162 # Number of instructions committed +system.cpu.committedOps 15162 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 385 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 2435 # number of instructions that are conditional controls -system.cpu.num_int_insts 12231 # number of integer instructions +system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls +system.cpu.num_int_insts 12219 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29059 # number of times the integer registers were read -system.cpu.num_int_register_writes 13831 # number of times the integer registers were written +system.cpu.num_int_register_reads 29037 # number of times the integer registers were read +system.cpu.num_int_register_writes 13818 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 3684 # number of memory refs -system.cpu.num_load_insts 2232 # Number of load instructions +system.cpu.num_mem_refs 3683 # number of memory refs +system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 86240 # Number of busy cycles +system.cpu.num_busy_cycles 86212 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 152.912665 # Cycle average of tags in use -system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 152.957781 # Cycle average of tags in use +system.cpu.icache.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 152.912665 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074664 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074664 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14941 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14941 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14941 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14941 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14941 # number of overall hits -system.cpu.icache.overall_hits::total 14941 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 152.957781 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074686 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074686 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits +system.cpu.icache.overall_hits::total 14928 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses @@ -77,18 +77,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 15596000 system.cpu.icache.demand_miss_latency::total 15596000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 15596000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 15596000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15221 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15221 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15221 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15221 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018396 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.018396 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.018396 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.018396 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.018396 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency @@ -115,12 +115,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018396 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.018396 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.018396 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency @@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.642881 # Cycle average of tags in use -system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 97.669722 # Cycle average of tags in use +system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.642881 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023839 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023839 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 2173 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2173 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 97.669722 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023845 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023845 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3530 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3530 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3530 # number of overall hits -system.cpu.dcache.overall_hits::total 3530 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits +system.cpu.dcache.overall_hits::total 3529 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses @@ -163,24 +163,24 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7728000 system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3668 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3668 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023810 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023810 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037623 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037623 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037623 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037623 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency @@ -213,14 +213,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency @@ -231,16 +231,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 183.636297 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 183.688794 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 152.238639 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.397658 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004646 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 152.283537 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.405257 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000958 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005604 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005606 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits |