diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
| commit | 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch) | |
| tree | 81108e7ff1951b652258f53bd5615a617b734ce2 /tests/quick/se/02.insttest/ref | |
| parent | ddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff) | |
| download | gem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz | |
update stats for preceeding changes
Diffstat (limited to 'tests/quick/se/02.insttest/ref')
12 files changed, 804 insertions, 778 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini index ddb8a4949..b0053eeff 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -92,22 +92,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,22 +123,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -155,24 +155,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -182,10 +182,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -200,7 +200,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -222,15 +222,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index e5fdf01a9..3730e9192 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:17 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:40 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 25614500 because target called exit() +Exiting @ tick 22838500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 165716ee5..87550aab2 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22522500 # Number of ticks simulated -final_tick 22522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 22838500 # Number of ticks simulated +final_tick 22838500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65265 # Simulator instruction rate (inst/s) -host_op_rate 65259 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96930117 # Simulator tick rate (ticks/s) -host_mem_usage 222888 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 15645 # Simulator instruction rate (inst/s) +host_op_rate 15645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23565036 # Simulator tick rate (ticks/s) +host_mem_usage 221420 # Number of bytes of host memory used +host_seconds 0.97 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 846797647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 392141192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1238938839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 846797647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 846797647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 846797647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 392141192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1238938839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 835081113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 386715415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1221796528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 835081113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 835081113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 835081113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 386715415 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1221796528 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 22489000 # Total gap between requests +system.physmem.totGap 22805000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,64 +164,64 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1783436 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10779436 # Sum of mem lat for all requests +system.physmem.totQLat 2327934 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11337934 # Sum of mem lat for all requests system.physmem.totBusLat 1744000 # Total cycles spent in databus access -system.physmem.totBankLat 7252000 # Total cycles spent in bank access -system.physmem.avgQLat 4090.45 # Average queueing delay per request -system.physmem.avgBankLat 16633.03 # Average bank access latency per request +system.physmem.totBankLat 7266000 # Total cycles spent in bank access +system.physmem.avgQLat 5339.30 # Average queueing delay per request +system.physmem.avgBankLat 16665.14 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24723.48 # Average memory access latency -system.physmem.avgRdBW 1238.94 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26004.44 # Average memory access latency +system.physmem.avgRdBW 1221.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1238.94 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1221.80 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.74 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.48 # Average read queue length over time +system.physmem.busUtil 7.64 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.50 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 359 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 51580.28 # Average gap between requests +system.physmem.avgGap 52305.05 # Average gap between requests system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 45046 # number of cpu cycles simulated +system.cpu.numCycles 45678 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 5017 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 3408 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 3514 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 2140 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 5149 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 3529 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 2365 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 4104 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2723 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 173 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 60.899260 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 2316 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2701 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 14466 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 66.349903 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 2896 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 25565 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 25496 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 4899 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3932 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 1367 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 948 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 2315 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 1043 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 68.939845 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 11058 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 5052 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3844 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 1540 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 762 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 2302 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 1056 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 68.552710 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 11045 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21840 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21901 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 501 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27681 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17365 # Number of cycles cpu stages are processed. -system.cpu.activity 38.549483 # Percentage of cycles cpu is active +system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28111 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17567 # Number of cycles cpu stages are processed. +system.cpu.activity 38.458339 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -233,72 +233,72 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 2.970980 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.012663 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 2.970980 # CPI: Total CPI of All Threads -system.cpu.ipc 0.336589 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.012663 # CPI: Total CPI of All Threads +system.cpu.ipc 0.331932 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.336589 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 31894 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 13152 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 29.196821 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 35835 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9211 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 20.447987 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36237 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8809 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 19.555565 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 42168 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.331932 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32253 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 13425 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 29.390516 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36325 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 20.475940 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 36875 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 19.271860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 42800 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 6.389025 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 35732 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9314 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 20.676642 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 6.300626 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36370 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9308 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 20.377425 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 171.605866 # Cycle average of tags in use -system.cpu.icache.total_refs 2584 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 172.580385 # Cycle average of tags in use +system.cpu.icache.total_refs 2999 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.642140 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10.030100 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 171.605866 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.083792 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.083792 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 2584 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2584 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2584 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2584 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2584 # number of overall hits -system.cpu.icache.overall_hits::total 2584 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 372 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 372 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 372 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 372 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 372 # number of overall misses -system.cpu.icache.overall_misses::total 372 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18064500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18064500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18064500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18064500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18064500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18064500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.125846 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.125846 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.125846 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.125846 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.125846 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.125846 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48560.483871 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48560.483871 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48560.483871 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48560.483871 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48560.483871 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48560.483871 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.580385 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084268 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084268 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2999 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2999 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2999 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2999 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2999 # number of overall hits +system.cpu.icache.overall_hits::total 2999 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 381 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 381 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 381 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses +system.cpu.icache.overall_misses::total 381 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18870500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18870500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18870500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18870500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18870500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18870500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3380 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3380 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3380 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3380 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3380 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3380 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112722 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.112722 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.112722 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.112722 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.112722 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.112722 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49528.871391 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49528.871391 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49528.871391 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49528.871391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49528.871391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49528.871391 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,46 +307,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14600500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14600500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14600500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14600500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14600500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14600500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101827 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.101827 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.101827 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48506.644518 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48506.644518 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48506.644518 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48506.644518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48506.644518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48506.644518 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15159500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15159500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15159500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15159500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15159500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15159500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.089053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.089053 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.089053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.089053 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.089053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.089053 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50363.787375 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50363.787375 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50363.787375 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50363.787375 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50363.787375 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50363.787375 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.150895 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 99.521292 # Cycle average of tags in use system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 99.150895 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024207 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024207 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 99.521292 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024297 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024297 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -365,14 +365,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3300500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19262500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19262500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22563000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22563000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22563000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22563000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3301000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3301000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19263500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19263500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22564500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22564500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22564500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22564500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -391,14 +391,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56905.172414 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56905.172414 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45645.734597 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45645.734597 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47006.250000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47006.250000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47006.250000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47006.250000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56913.793103 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56913.793103 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45648.104265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45648.104265 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47009.375000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47009.375000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 680 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked @@ -423,14 +423,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4513000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4513000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7413000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7413000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7413000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7413000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7414500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7414500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7414500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7414500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -439,26 +439,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54716.981132 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54716.981132 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53094.117647 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53094.117647 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54726.415094 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54726.415094 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53105.882353 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53105.882353 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 202.986818 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 204.089765 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 170.969481 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.017336 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005218 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000977 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006195 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.939057 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.150708 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005247 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000981 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006228 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -476,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14317500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2845500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17163000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4425000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4425000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14317500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7270500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21588000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14317500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7270500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21588000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14876500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2846000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17722500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4426000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4426000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14876500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7272000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22148500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14876500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7272000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22148500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -509,17 +509,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47884.615385 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53688.679245 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48758.522727 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52058.823529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52058.823529 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49400.457666 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49400.457666 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49754.180602 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53698.113208 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50348.011364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52070.588235 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52070.588235 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49754.180602 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50683.066362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49754.180602 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50683.066362 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -539,17 +539,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547482 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11107481 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12729050 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13289049 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547482 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11107481 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16111114 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547482 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16671113 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11107481 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16111114 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16671113 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -561,17 +561,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35275.859532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37148.765886 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36162.073864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37752.980114 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37148.765886 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37148.765886 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38149 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index d68715156..9a57b4e8b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -129,18 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +423,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -455,24 +455,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +482,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -522,15 +522,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index d7d566072..9433cbefd 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:20 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:40 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 20275500 because target called exit() +Exiting @ tick 23190500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 39a395968..e7a1232b3 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,50 +1,50 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23428500 # Number of ticks simulated -final_tick 23428500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 23190500 # Number of ticks simulated +final_tick 23190500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53742 # Simulator instruction rate (inst/s) -host_op_rate 53738 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87205048 # Simulator tick rate (ticks/s) -host_mem_usage 223912 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 24201 # Simulator instruction rate (inst/s) +host_op_rate 24200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38875523 # Simulator tick rate (ticks/s) +host_mem_usage 222232 # Number of bytes of host memory used +host_seconds 0.60 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory -system.physmem.bytes_read::total 30848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory +system.physmem.bytes_read::total 30912 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory -system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 917856457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 398830484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1316686941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 917856457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 917856457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 917856457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 398830484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1316686941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 482 # Total number of read requests seen +system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory +system.physmem.num_reads::total 483 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 927276255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 405683362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1332959617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 927276255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 927276255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 927276255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 405683362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1332959617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 483 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30848 # Total number of bytes read from memory +system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30912 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23376000 # Total gap between requests +system.physmem.totGap 23130500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 482 # Categorize read packet sizes +system.physmem.readPktSize::6 483 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,262 +164,262 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2488982 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12396982 # Sum of mem lat for all requests -system.physmem.totBusLat 1928000 # Total cycles spent in databus access -system.physmem.totBankLat 7980000 # Total cycles spent in bank access -system.physmem.avgQLat 5163.86 # Average queueing delay per request -system.physmem.avgBankLat 16556.02 # Average bank access latency per request +system.physmem.totQLat 2984483 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12938483 # Sum of mem lat for all requests +system.physmem.totBusLat 1932000 # Total cycles spent in databus access +system.physmem.totBankLat 8022000 # Total cycles spent in bank access +system.physmem.avgQLat 6179.05 # Average queueing delay per request +system.physmem.avgBankLat 16608.70 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25719.88 # Average memory access latency -system.physmem.avgRdBW 1316.69 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26787.75 # Average memory access latency +system.physmem.avgRdBW 1332.96 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1316.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1332.96 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 8.23 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.53 # Average read queue length over time +system.physmem.busUtil 8.33 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.56 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 393 # Number of row buffer hits during reads +system.physmem.readRowHits 394 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48497.93 # Average gap between requests +system.physmem.avgGap 47889.23 # Average gap between requests system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 46858 # number of cpu cycles simulated +system.cpu.numCycles 46382 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6941 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4630 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5115 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2636 # Number of BTB hits +system.cpu.BPredUnit.lookups 6758 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4516 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1074 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4657 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2448 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12393 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 32407 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6941 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3078 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9616 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3187 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8221 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31427 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6758 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3075 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8320 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 943 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5564 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 468 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33142 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.977823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.154937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5337 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 32520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.966390 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.158060 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23526 70.99% 70.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4767 14.38% 85.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 497 1.50% 86.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 473 1.43% 88.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 713 2.15% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 723 2.18% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 250 0.75% 93.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 284 0.86% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1909 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23340 71.77% 71.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4525 13.91% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 464 1.43% 87.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 371 1.14% 88.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1896 5.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33142 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.148128 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.691600 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13096 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9104 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8780 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1965 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30240 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1965 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 355 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8257 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8329 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 447 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27456 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 134 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24477 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 50943 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 50943 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 32520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.145703 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.677569 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8404 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29366 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13469 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8329 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8008 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 128 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24166 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49969 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 49969 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10658 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 696 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 697 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2830 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3653 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 691 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2732 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2330 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23144 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 660 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21674 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6018 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 185 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.653974 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.274325 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 22740 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21250 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 137 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8195 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5897 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 32520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.653444 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.275128 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23639 71.33% 71.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3658 11.04% 82.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2441 7.37% 89.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1702 5.14% 94.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 894 2.70% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 488 1.47% 99.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 244 0.74% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 60 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 16 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23284 71.60% 71.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3476 10.69% 82.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 913 2.81% 97.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 49 28.16% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.94% 43.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 99 56.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27 17.65% 47.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16000 73.82% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3426 15.81% 89.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2248 10.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15763 74.18% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3339 15.71% 89.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2148 10.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21674 # Type of FU issued -system.cpu.iq.rate 0.462546 # Inst issue rate -system.cpu.iq.fu_busy_cnt 174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008028 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76777 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32254 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19887 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21250 # Type of FU issued +system.cpu.iq.rate 0.458152 # Inst issue rate +system.cpu.iq.fu_busy_cnt 153 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007200 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75310 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31611 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19572 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21848 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21403 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1965 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 238 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24981 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 536 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3653 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 660 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24529 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 387 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2330 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 295 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 957 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20477 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3262 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1197 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20156 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3213 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1094 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1177 # number of nop insts executed -system.cpu.iew.exec_refs 5386 # number of memory reference insts executed -system.cpu.iew.exec_branches 4289 # Number of branches executed -system.cpu.iew.exec_stores 2124 # Number of stores executed -system.cpu.iew.exec_rate 0.437001 # Inst execution rate -system.cpu.iew.wb_sent 20145 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19887 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9217 # num instructions producing a value -system.cpu.iew.wb_consumers 11299 # num instructions consuming a value +system.cpu.iew.exec_nop 1139 # number of nop insts executed +system.cpu.iew.exec_refs 5233 # number of memory reference insts executed +system.cpu.iew.exec_branches 4247 # Number of branches executed +system.cpu.iew.exec_stores 2020 # Number of stores executed +system.cpu.iew.exec_rate 0.434565 # Inst execution rate +system.cpu.iew.wb_sent 19807 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19572 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9210 # num instructions producing a value +system.cpu.iew.wb_consumers 11373 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.424410 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.815736 # average fanout of values written-back +system.cpu.iew.wb_rate 0.421974 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9729 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9292 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31194 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.486055 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.173479 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 30632 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.494973 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.191764 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23830 76.39% 76.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4047 12.97% 89.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1444 4.63% 94.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 788 2.53% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 343 1.10% 97.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 244 0.78% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 322 1.03% 99.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 69 0.22% 99.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 107 0.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23334 76.18% 76.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1377 4.50% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 324 1.06% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 65 0.21% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30632 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -430,68 +430,68 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 55155 # The number of ROB reads -system.cpu.rob.rob_writes 51753 # The number of ROB writes -system.cpu.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13716 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54149 # The number of ROB reads +system.cpu.rob.rob_writes 50819 # The number of ROB writes +system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13862 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.245913 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.245913 # CPI: Total CPI of All Threads -system.cpu.ipc 0.308080 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.308080 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32584 # number of integer regfile reads -system.cpu.int_regfile_writes 18115 # number of integer regfile writes -system.cpu.misc_regfile_reads 7035 # number of misc regfile reads +system.cpu.cpi 3.212940 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.212940 # CPI: Total CPI of All Threads +system.cpu.ipc 0.311241 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.311241 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32188 # number of integer regfile reads +system.cpu.int_regfile_writes 17920 # number of integer regfile writes +system.cpu.misc_regfile_reads 6865 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 194.443697 # Cycle average of tags in use -system.cpu.icache.total_refs 5086 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 191.561206 # Cycle average of tags in use +system.cpu.icache.total_refs 4845 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15.047337 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 14.334320 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 194.443697 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.094943 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.094943 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5086 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5086 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5086 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5086 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5086 # number of overall hits -system.cpu.icache.overall_hits::total 5086 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses -system.cpu.icache.overall_misses::total 478 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21903000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21903000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21903000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21903000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21903000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21903000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5564 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5564 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5564 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5564 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5564 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5564 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085909 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085909 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085909 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085909 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085909 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085909 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45822.175732 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45822.175732 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45822.175732 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45822.175732 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45822.175732 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45822.175732 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 191.561206 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.093536 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.093536 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4845 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4845 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4845 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4845 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4845 # number of overall hits +system.cpu.icache.overall_hits::total 4845 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 492 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 492 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 492 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 492 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 492 # number of overall misses +system.cpu.icache.overall_misses::total 492 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23061000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23061000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23061000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23061000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23061000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23061000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5337 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5337 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5337 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5337 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5337 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5337 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092187 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092187 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092187 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092187 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092187 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092187 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46871.951220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46871.951220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46871.951220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46871.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46871.951220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46871.951220 # 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Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.944828 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 99.978765 # Cycle average of tags in use +system.cpu.dcache.total_refs 4011 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 27.285714 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 100.624732 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024567 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024567 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3013 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3013 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 99.978765 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024409 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024409 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2972 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2972 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4046 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4046 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4046 # number of overall hits -system.cpu.dcache.overall_hits::total 4046 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 129 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 129 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4005 # 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number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6945000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6945000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19513974 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19513974 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26458974 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26458974 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26458974 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26458974 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3102 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3102 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4584 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4584 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4584 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4584 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041057 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.041057 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4544 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4544 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4544 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4544 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041908 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.041908 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117365 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117365 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117365 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117365 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52996.124031 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52996.124031 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47695.535452 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47695.535452 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48966.494424 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48966.494424 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48966.494424 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48966.494424 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 427 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.118618 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118618 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118618 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118618 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53423.076923 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53423.076923 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47711.427873 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47711.427873 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49089.005566 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49089.005566 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49089.005566 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49089.005566 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.724138 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -608,50 +608,50 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 392 system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3776500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3776500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4497000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4497000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8273500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8273500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8273500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8273500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020051 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020051 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4507500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4507500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8344500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8344500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8344500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8344500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020632 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020632 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031850 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031850 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031850 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031850 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59944.444444 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59944.444444 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54180.722892 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54180.722892 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56667.808219 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56667.808219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56667.808219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56667.808219 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032350 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032350 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032350 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032350 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59953.125000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59953.125000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54307.228916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54307.228916 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56765.306122 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56765.306122 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56765.306122 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56765.306122 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 229.081422 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 225.876311 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 193.844447 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 35.236975 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005916 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001075 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006991 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 190.966695 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.909617 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005828 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001065 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006893 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -659,60 +659,60 @@ system.cpu.l2cache.demand_hits::total 2 # nu system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 336 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994083 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.995012 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994083 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48130.952381 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59603.174603 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49942.355890 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53168.674699 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53168.674699 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48130.952381 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55945.205479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50497.925311 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48130.952381 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55945.205479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50497.925311 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49696.428571 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58945.312500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51176.250000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53295.180723 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53295.180723 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49696.428571 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55755.102041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51540.372671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49696.428571 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55755.102041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51540.372671 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -722,49 +722,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 482 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6369122 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18312638 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12468016 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2980062 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15448078 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3402062 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3402062 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12468016 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6382124 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18850140 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12468016 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6382124 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18850140 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35546.178571 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47223.174603 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37389.914787 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40892.313253 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40892.313253 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35546.178571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43624.123288 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37993.024896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35546.178571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43624.123288 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37993.024896 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37107.190476 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38620.195000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40988.698795 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40988.698795 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37107.190476 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43415.809524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39027.204969 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37107.190476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43415.809524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39027.204969 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 8143784d6..eec9abdb9 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -82,7 +82,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -106,7 +106,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index ffad57b6b..a099312ec 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:25 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:46:06 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index feda286ec..fb1046e47 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1344667 # Simulator instruction rate (inst/s) -host_op_rate 1342613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 673049198 # Simulator tick rate (ticks/s) -host_mem_usage 220960 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 19584 # Simulator instruction rate (inst/s) +host_op_rate 19584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9831731 # Simulator tick rate (ticks/s) +host_mem_usage 212388 # Number of bytes of host memory used +host_seconds 0.77 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index cd98523de..0cf9ff042 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -61,22 +61,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -92,22 +92,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -124,24 +124,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -151,10 +151,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -169,7 +169,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 @@ -193,7 +193,7 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index cacf98182..8494e13f4 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:28 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:40 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 43106000 because target called exit() +Exiting @ tick 41368000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index af9b5d77e..54610aef7 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 41368000 # Number of ticks simulated final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 652409 # Simulator instruction rate (inst/s) -host_op_rate 651936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1777530278 # Simulator tick rate (ticks/s) -host_mem_usage 220352 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 17560 # Simulator instruction rate (inst/s) +host_op_rate 17560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47909450 # Simulator tick rate (ticks/s) +host_mem_usage 220988 # Number of bytes of host memory used +host_seconds 0.86 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory |