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authorAli Saidi <Ali.Saidi@ARM.com>2013-01-07 13:05:54 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2013-01-07 13:05:54 -0500
commit9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch)
treefab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/quick/se/02.insttest
parent009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff)
downloadgem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz
stats: update stats for previous changes.
Diffstat (limited to 'tests/quick/se/02.insttest')
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini28
-rwxr-xr-xtests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout8
-rw-r--r--tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt712
3 files changed, 369 insertions, 379 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 9a57b4e8b..37d5abdb3 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -425,21 +422,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -448,6 +440,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -459,21 +454,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -500,7 +490,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=/gem5/dist/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
index 9433cbefd..c7e6fdca4 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:40
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:16:54
+gem5 started Jan 4 2013 21:59:36
+gem5 executing on u200540
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -18,4 +18,4 @@ LDTX: Passed
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 23190500 because target called exit()
+Exiting @ tick 23180500 because target called exit()
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index e7a1232b3..a62497bbb 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000023 # Number of seconds simulated
-sim_ticks 23190500 # Number of ticks simulated
-final_tick 23190500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 23180500 # Number of ticks simulated
+final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 24201 # Simulator instruction rate (inst/s)
-host_op_rate 24200 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38875523 # Simulator tick rate (ticks/s)
-host_mem_usage 222232 # Number of bytes of host memory used
-host_seconds 0.60 # Real time elapsed on the host
+host_inst_rate 21899 # Simulator instruction rate (inst/s)
+host_op_rate 21897 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 35159544 # Simulator tick rate (ticks/s)
+host_mem_usage 223288 # Number of bytes of host memory used
+host_seconds 0.66 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21504 # Nu
system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 927276255 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 405683362 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1332959617 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 927276255 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 927276255 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 927276255 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 405683362 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1332959617 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 927676280 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 405858372 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1333534652 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 927676280 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 927676280 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 927676280 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 405858372 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1333534652 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 483 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady
@@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 23130500 # Total gap between requests
+system.physmem.totGap 23120500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -98,8 +98,8 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
@@ -164,17 +164,17 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2984483 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12938483 # Sum of mem lat for all requests
+system.physmem.totQLat 3040483 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12980483 # Sum of mem lat for all requests
system.physmem.totBusLat 1932000 # Total cycles spent in databus access
-system.physmem.totBankLat 8022000 # Total cycles spent in bank access
-system.physmem.avgQLat 6179.05 # Average queueing delay per request
-system.physmem.avgBankLat 16608.70 # Average bank access latency per request
+system.physmem.totBankLat 8008000 # Total cycles spent in bank access
+system.physmem.avgQLat 6295.00 # Average queueing delay per request
+system.physmem.avgBankLat 16579.71 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26787.75 # Average memory access latency
-system.physmem.avgRdBW 1332.96 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26874.71 # Average memory access latency
+system.physmem.avgRdBW 1333.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1332.96 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1333.53 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 8.33 # Data bus utilization in percentage
@@ -184,59 +184,59 @@ system.physmem.readRowHits 394 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 47889.23 # Average gap between requests
+system.physmem.avgGap 47868.53 # Average gap between requests
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 46382 # number of cpu cycles simulated
+system.cpu.numCycles 46362 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6758 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 4516 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 6759 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 4517 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1074 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 4657 # Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 4658 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 2448 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 31427 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6758 # Number of branches that fetch encountered
+system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 9180 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3075 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 8320 # Number of cycles fetch has spent blocked
+system.cpu.fetch.Cycles 9181 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3076 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 8341 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 5337 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 32520 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.966390 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.158060 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 5338 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 32543 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.965953 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.157796 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 23340 71.77% 71.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4525 13.91% 85.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 464 1.43% 87.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 371 1.14% 88.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 23362 71.79% 71.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4525 13.90% 85.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 464 1.43% 87.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 371 1.14% 88.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1896 5.83% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1897 5.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 32520 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.145703 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.677569 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::total 32543 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.145787 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.678034 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9195 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 8404 # Number of cycles decode is running
+system.cpu.decode.BlockedCycles 9216 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 8405 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 29366 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13469 # Number of cycles rename is idle
+system.cpu.decode.SquashCycles 1906 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 29374 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1906 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13470 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 8329 # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles 8350 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 8008 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename
@@ -249,27 +249,27 @@ system.cpu.rename.CommittedMaps 13819 # Nu
system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 691 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2732 # count of insts added to the skid buffer
+system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 2330 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 2331 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 22740 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 22748 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21250 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 137 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8195 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 5897 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 21285 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 8188 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 5672 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 32520 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.653444 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.275128 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 32543 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.654058 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.275967 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 23284 71.60% 71.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3476 10.69% 82.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 913 2.81% 97.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 23299 71.59% 71.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3475 10.68% 82.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 922 2.83% 97.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle
@@ -277,7 +277,7 @@ system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 32520 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 32543 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available
@@ -313,69 +313,69 @@ system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # at
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 15763 74.18% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 3339 15.71% 89.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 2148 10.11% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 15766 74.07% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 3371 15.84% 89.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 2148 10.09% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 21250 # Type of FU issued
-system.cpu.iq.rate 0.458152 # Inst issue rate
+system.cpu.iq.FU_type_0::total 21285 # Type of FU issued
+system.cpu.iq.rate 0.459104 # Inst issue rate
system.cpu.iq.fu_busy_cnt 153 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007200 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 75310 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 31611 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19572 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.007188 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 75371 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 31612 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21403 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21438 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 883 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 1906 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 24529 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 387 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispatchedInsts 24537 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2330 # Number of dispatched store instructions
+system.cpu.iew.iewDispStoreInsts 2331 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
@@ -383,33 +383,33 @@ system.cpu.iew.memOrderViolationEvents 26 # Nu
system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20156 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 3213 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1094 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 20207 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 3221 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1078 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1139 # number of nop insts executed
-system.cpu.iew.exec_refs 5233 # number of memory reference insts executed
+system.cpu.iew.exec_refs 5276 # number of memory reference insts executed
system.cpu.iew.exec_branches 4247 # Number of branches executed
-system.cpu.iew.exec_stores 2020 # Number of stores executed
-system.cpu.iew.exec_rate 0.434565 # Inst execution rate
-system.cpu.iew.wb_sent 19807 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 19572 # cumulative count of insts written-back
+system.cpu.iew.exec_stores 2055 # Number of stores executed
+system.cpu.iew.exec_rate 0.435853 # Inst execution rate
+system.cpu.iew.wb_sent 19873 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 19647 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9210 # num instructions producing a value
system.cpu.iew.wb_consumers 11373 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.421974 # insts written-back per cycle
+system.cpu.iew.wb_rate 0.423774 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 9292 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9300 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 30632 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.494973 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.191764 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 30637 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.494892 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.191683 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 23334 76.18% 76.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 23339 76.18% 76.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1377 4.50% 93.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1377 4.49% 93.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle
@@ -419,7 +419,7 @@ system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 30632 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 30637 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -432,66 +432,66 @@ system.cpu.commit.int_insts 12174 # Nu
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 54149 # The number of ROB reads
-system.cpu.rob.rob_writes 50819 # The number of ROB writes
+system.cpu.rob.rob_reads 54162 # The number of ROB reads
+system.cpu.rob.rob_writes 50836 # The number of ROB writes
system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13862 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 13819 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
-system.cpu.cpi 3.212940 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.212940 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.311241 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.311241 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 32188 # number of integer regfile reads
-system.cpu.int_regfile_writes 17920 # number of integer regfile writes
-system.cpu.misc_regfile_reads 6865 # number of misc regfile reads
+system.cpu.cpi 3.211554 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.211554 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.311376 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.311376 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 32290 # number of integer regfile reads
+system.cpu.int_regfile_writes 17967 # number of integer regfile writes
+system.cpu.misc_regfile_reads 6967 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 191.561206 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 191.466325 # Cycle average of tags in use
system.cpu.icache.total_refs 4845 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14.334320 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 191.561206 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.093536 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.093536 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 191.466325 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.093489 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.093489 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4845 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4845 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4845 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4845 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4845 # number of overall hits
system.cpu.icache.overall_hits::total 4845 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 492 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 492 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 492 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 492 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 492 # number of overall misses
-system.cpu.icache.overall_misses::total 492 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 23061000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 23061000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 23061000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 23061000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 23061000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 23061000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5337 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5337 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5337 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5337 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5337 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5337 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092187 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.092187 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.092187 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.092187 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.092187 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.092187 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46871.951220 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 46871.951220 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 46871.951220 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 46871.951220 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 46871.951220 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 46871.951220 # average overall miss latency
+system.cpu.icache.ReadReq_misses::cpu.inst 493 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 493 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 493 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 493 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 493 # number of overall misses
+system.cpu.icache.overall_misses::total 493 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 23383000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 23383000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 23383000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 23383000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 23383000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 23383000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5338 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5338 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5338 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5338 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5338 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5338 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092357 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.092357 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.092357 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.092357 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.092357 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.092357 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47430.020284 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 47430.020284 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 47430.020284 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 47430.020284 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses
@@ -754,17 +644,127 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37107.190476 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37107.190476 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.tagsinuse 99.943036 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4019 # Total number of references to valid blocks.
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+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------