diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
| commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
| tree | 5d32efd82f884376573604727d971a80458ed04a /tests/quick/se/02.insttest | |
| parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
| download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz | |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/quick/se/02.insttest')
13 files changed, 244 insertions, 83 deletions
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini index 8b9b39b0d..b15f5671c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index b2566a0a7..30eeb514f 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:53 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 5325eaa70..73324a4d5 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000025 # Nu sim_ticks 25007500 # Number of ticks simulated final_tick 25007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55900 # Simulator instruction rate (inst/s) -host_op_rate 55897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92110077 # Simulator tick rate (ticks/s) -host_mem_usage 220976 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 72389 # Simulator instruction rate (inst/s) +host_op_rate 72383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119272701 # Simulator tick rate (ticks/s) +host_mem_usage 221376 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 27904 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19072 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 436 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1115825252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 762651205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1115825252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 27904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 436 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 762651205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 353174048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1115825252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 762651205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 762651205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 762651205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 353174048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1115825252 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 50016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -123,11 +130,17 @@ system.cpu.icache.demand_accesses::total 2970 # nu system.cpu.icache.overall_accesses::cpu.inst 2970 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2970 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123906 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123906 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.123906 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123906 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.123906 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123906 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54900.815217 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54900.815217 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54900.815217 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54900.815217 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -155,11 +168,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 15872000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.101347 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.101347 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52730.897010 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 97.041769 # Cycle average of tags in use @@ -207,13 +226,21 @@ system.cpu.dcache.demand_accesses::total 3668 # nu system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026056 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.208044 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.097601 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097601 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097601 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097601 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56577.586207 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56577.586207 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54656.666667 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54656.666667 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54967.877095 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54967.877095 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -247,13 +274,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7382000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7382000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7382000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53528.301887 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53528.301887 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53470.588235 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53492.753623 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53492.753623 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 196.205624 # Cycle average of tags in use @@ -307,18 +342,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993355 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994350 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993355 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995444 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52386.792453 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.625000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52264.705882 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52064.073227 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52064.073227 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,18 +394,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 system.cpu.l2cache.overall_mshr_miss_latency::total 17464500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39910.511364 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40188.235294 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 64273b3fe..e306accf8 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 076570d2f..f0f4b69ef 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:02 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 693d12ddb..a887522dd 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000020 # Nu sim_ticks 19744500 # Number of ticks simulated final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52427 # Simulator instruction rate (inst/s) -host_op_rate 52424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71633039 # Simulator tick rate (ticks/s) -host_mem_usage 221536 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 74885 # Simulator instruction rate (inst/s) +host_op_rate 74878 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 102311932 # Simulator tick rate (ticks/s) +host_mem_usage 222004 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated sim_ops 14449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30976 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 484 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1568841956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1095596242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1568841956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory +system.physmem.bytes_read::total 30976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory +system.physmem.num_reads::total 484 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1095596242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 473245714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1568841956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1095596242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1095596242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1095596242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 473245714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1568841956 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 39490 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -318,11 +325,17 @@ system.cpu.icache.demand_accesses::total 5506 # nu system.cpu.icache.overall_accesses::cpu.inst 5506 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.088267 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.088267 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.088267 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.088267 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.088267 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34414.609053 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34414.609053 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34414.609053 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,11 +363,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 11937500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061751 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.061751 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.061751 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 103.476464 # Cycle average of tags in use @@ -402,13 +421,21 @@ system.cpu.dcache.demand_accesses::total 4603 # nu system.cpu.dcache.overall_accesses::cpu.data 4603 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 4603 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037330 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.114273 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.114273 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.114273 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.114273 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34682.203390 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35768.382353 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35524.714829 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35524.714829 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,13 +469,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5223000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5223000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019930 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031718 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031718 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35897.590361 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 236.259194 # Cycle average of tags in use @@ -502,18 +537,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 146 system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994118 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995037 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994118 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995885 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.751479 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34293.017456 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34339.876033 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34339.876033 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,18 +589,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.034913 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 63fce3718..9dd70f314 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index c5ff1dac8..0a6c1bd0d 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:04 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index b4eb79291..a62ce7951 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.000008 # Nu sim_ticks 7618500 # Number of ticks simulated final_tick 7618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147764 # Simulator instruction rate (inst/s) -host_op_rate 147721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74142280 # Simulator tick rate (ticks/s) -host_mem_usage 211580 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 949089 # Simulator instruction rate (inst/s) +host_op_rate 948034 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 475431989 # Simulator tick rate (ticks/s) +host_mem_usage 212076 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 72223 # Number of bytes read from this memory -system.physmem.bytes_inst_read 60880 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9042 # Number of bytes written to this memory -system.physmem.num_reads 17446 # Number of read requests responded to by this memory -system.physmem.num_writes 1442 # Number of write requests responded to by this memory -system.physmem.num_other 6 # Number of other requests responded to by this memory -system.physmem.bw_read 9479950121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7991074358 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1186847805 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10666797926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 60880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11343 # Number of bytes read from this memory +system.physmem.bytes_read::total 72223 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory +system.physmem.bytes_written::total 9042 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2226 # Number of read requests responded to by this memory +system.physmem.num_reads::total 17446 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory +system.physmem.num_other::total 6 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7991074358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1488875763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9479950121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7991074358 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7991074358 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186847805 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1186847805 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7991074358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2675723568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10666797926 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 15238 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index ad6d2cdd3..cfbf65944 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index 9346f2ccc..423d84a63 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:42:54 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:13 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index dfba79da8..f6532c6ee 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000042 # Nu sim_ticks 41800000 # Number of ticks simulated final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130693 # Simulator instruction rate (inst/s) -host_op_rate 130661 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 359830859 # Simulator tick rate (ticks/s) -host_mem_usage 220580 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 488993 # Simulator instruction rate (inst/s) +host_op_rate 488707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1345414902 # Simulator tick rate (ticks/s) +host_mem_usage 221064 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 416 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 636937799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 425645933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 636937799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 26624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 416 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 425645933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 211291866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 636937799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 425645933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 425645933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 425645933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 211291866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 636937799 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 83600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 15221 # nu system.cpu.icache.overall_accesses::cpu.inst 15221 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 15221 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018396 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.018396 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.018396 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.018396 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.018396 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55700 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 14756000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018396 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.018396 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.018396 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use @@ -155,13 +174,21 @@ system.cpu.dcache.demand_accesses::total 3668 # nu system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023810 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.037623 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037623 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037623 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,13 +214,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7314000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use @@ -247,18 +282,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -291,18 +334,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |